1. 28 Sep, 2018 1 commit
  2. 21 Sep, 2018 1 commit
  3. 30 Oct, 2017 1 commit
  4. 27 Oct, 2017 5 commits
  5. 12 Dec, 2014 1 commit
  6. 05 Dec, 2014 1 commit
  7. 04 Dec, 2014 2 commits
  8. 02 Dec, 2014 1 commit
  9. 01 Dec, 2014 1 commit
  10. 26 Nov, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      hdl: Additions to rear test logic · 30f02bf6
      Theodor-Adrian Stana authored
      The additions are:
      - checking the fail-safe lines before passing the input pulse to the pulse
        counters
      - adding a delay to the pulse generators, to account for hardware delay
        appearing on enable
      30f02bf6
  11. 17 Nov, 2014 1 commit
  12. 12 Nov, 2014 4 commits
  13. 11 Nov, 2014 2 commits
  14. 10 Nov, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      hdl: Work on changing for V2 card · 70750c9a
      Theodor-Adrian Stana authored
      The V2 card has the front-panel LEDs non-negated (the Schmitt-trigger inverters
      have been removed) and has LEDs added for each inverter channel. The relevant
      changes have been made in this respect as follows:
      - changed signal names in UCF and top-level VHDL file
      - changed polarity of pulse LED outputs to active-high
      - added the inverter LED outputs
      - added the inverter LEDs in the LED sequencing scheme for the LED test
      70750c9a
  15. 04 Nov, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      hdl: Made SFP EEPROM test work · 31edd84f
      Theodor-Adrian Stana authored
      The issue was an error in the schematics, where the names of the SDA line and
      the RATE_SELECT lines were swapped. This led to the definitions of the pins in
      the UCF file to be wrong and the SFP test not working.
      
      With the proper pin names in the UCF file, the SFP test now works.
      31edd84f
  16. 03 Nov, 2014 4 commits
  17. 31 Oct, 2014 4 commits
  18. 30 Oct, 2014 3 commits