Skip to content

C
Conv TTL RS485 - Testing
Commit e9f2131e authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
Browse files
Options

sw: Updated the names of some bits in the CSR 

Also updated the scripts with the according names and the Makefile with the new
link to the binary file.
parent 1126dcb7
Hide whitespace changes
Inline Side-by-side
Showing with 39 additions and 39 deletions
pts/Makefile
View file @ e9f2131e
...@@ -28,7 +28,7 @@ all: ...@@ -28,7 +28,7 @@ all:
mkdir -p ubuntu/t485/boot mkdir -p ubuntu/t485/boot
mv ubuntu/t485/shell/program ubuntu/t485/boot mv ubuntu/t485/shell/program ubuntu/t485/boot
mv ubuntu/t485/shell/flash ubuntu/t485/boot mv ubuntu/t485/shell/flash ubuntu/t485/boot
wget -P ubuntu/t485/boot http://www.ohwr.org/attachments/download/3689/pts.bit wget -P ubuntu/t485/boot http://www.ohwr.org/attachments/download/3690/pts.bit
wget -P ubuntu/t485/boot http://www.ohwr.org/attachments/download/3650/flash_load.bit wget -P ubuntu/t485/boot http://www.ohwr.org/attachments/download/3650/flash_load.bit
wget -P ubuntu/t485/boot http://www.ohwr.org/attachments/download/3657/golden-v0.0_release-v1.0.bin wget -P ubuntu/t485/boot http://www.ohwr.org/attachments/download/3657/golden-v0.0_release-v1.0.bin
......
pts/python/leds.py
View file @ e9f2131e
...@@ -76,7 +76,7 @@ def main(bus,tname,inf,log): ...@@ -76,7 +76,7 @@ def main(bus,tname,inf,log):
# First phase of LED test, enable pulse LED sequencing # First phase of LED test, enable pulse LED sequencing
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val |= (1 << CSR_FRONT_LED_EN_OFS) val |= (1 << CSR_CHLEDT_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
# The gateware should blink the LEDs, ask the operator for input # The gateware should blink the LEDs, ask the operator for input
...@@ -93,8 +93,8 @@ def main(bus,tname,inf,log): ...@@ -93,8 +93,8 @@ def main(bus,tname,inf,log):
inp = raw_input('Please type "yes" or "no" to continue: ') inp = raw_input('Please type "yes" or "no" to continue: ')
# Second phase of LED test, enable status LED sequencing # Second phase of LED test, enable status LED sequencing
val &= ~(1 << CSR_FRONT_LED_EN_OFS) val &= ~(1 << CSR_CHLEDT_OFS)
val |= 1 << CSR_STAT_LED_EN_OFS val |= 1 << CSR_STLEDT_OFS
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
# The gateware should blink the LEDs, ask the operator for input # The gateware should blink the LEDs, ask the operator for input
...@@ -121,6 +121,6 @@ def main(bus,tname,inf,log): ...@@ -121,6 +121,6 @@ def main(bus,tname,inf,log):
finally: finally:
# Clean-up -- clear status and front LED test bits # Clean-up -- clear status and front LED test bits
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val &= ~((1 << CSR_FRONT_LED_EN_OFS) | (1 << CSR_STAT_LED_EN_OFS)) val &= ~((1 << CSR_CHLEDT_OFS) | (1 << CSR_STLEDT_OFS))
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
pts/python/ptsdefine.py
View file @ e9f2131e
...@@ -50,22 +50,22 @@ BIDR = 0x000 ...@@ -50,22 +50,22 @@ BIDR = 0x000
BIDR_ARR = [ "TBLO", "T485" ] BIDR_ARR = [ "TBLO", "T485" ]
# Control and Status Register # Control and Status Register
CSR = 0x004 CSR = 0x004
CSR_FRONT_LED_EN_OFS = 0 CSR_CHLEDT_OFS = 0
CSR_REAR_LED_EN_OFS = 1 CSR_STLEDT_OFS = 1
CSR_STAT_LED_EN_OFS = 2 #CSR_RLEDT_OFS = 2
CSR_TTL_EN_OFS = 3 CSR_TTLPT_OFS = 3
CSR_REAR_EN_OFS = 4 CSR_REARPT_OFS = 4
CSR_TESTER_VCC_OFS = 5 CSR_TSTCVCC_OFS = 5
CSR_TESTER_MUX_EN_OFS = 6 CSR_TSTCMUXEN_OFS = 6
CSR_TESTER_MUX_S0_OFS = 7 CSR_TSTCS0_OFS = 7
CSR_TESTER_MUX_S1_OFS = 8 CSR_TSTCS1_OFS = 8
CSR_RST_UNLOCK_OFS = 14 CSR_RST_UNLOCK_OFS = 14
CSR_RST_OFS = 15 CSR_RST_OFS = 15
CSR_SWITCHES_OFS = 16 CSR_SWITCH_OFS = 16
CSR_RTM_OFS = 24 CSR_RTM_OFS = 24
CSR_I2C_ERR_OFS = 30 CSR_I2C_ERR_OFS = 30
CSR_I2C_WDTO_OFS = 31 CSR_I2C_WDTO_OFS = 31
# Line Status Register # Line Status Register
LSR = 0x008 LSR = 0x008
......
pts/python/rs485_pulse_rtm.py
View file @ e9f2131e
...@@ -88,24 +88,24 @@ class CPulseCounter: ...@@ -88,24 +88,24 @@ class CPulseCounter:
#-------------------------------------------------------------------------------------------------- #--------------------------------------------------------------------------------------------------
def mux_sel(bus, sel): def mux_sel(bus, sel):
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val &= ~(1 << CSR_TESTER_MUX_S0_OFS) val &= ~(1 << CSR_TSTCS0_OFS)
val &= ~(1 << CSR_TESTER_MUX_S1_OFS) val &= ~(1 << CSR_TSTCS1_OFS)
if (sel & 0x1): if (sel & 0x1):
val |= (1 << CSR_TESTER_MUX_S0_OFS) val |= (1 << CSR_TSTCS0_OFS)
if (sel & 0x2): if (sel & 0x2):
val |= (1 << CSR_TESTER_MUX_S1_OFS) val |= (1 << CSR_TSTCS1_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
time.sleep(0.1) time.sleep(0.1)
def en_pulse_gen(bus): def en_pulse_gen(bus):
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val |= (1 << CSR_REAR_EN_OFS) val |= (1 << CSR_REARPT_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
time.sleep(0.1) time.sleep(0.1)
def dis_pulse_gen(bus): def dis_pulse_gen(bus):
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val &= ~(1 << CSR_REAR_EN_OFS) val &= ~(1 << CSR_REARPT_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
time.sleep(0.1) time.sleep(0.1)
...@@ -209,7 +209,7 @@ def main(bus, tname, inf, log): ...@@ -209,7 +209,7 @@ def main(bus, tname, inf, log):
# Power on the tester card # Power on the tester card
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val |= (1 << CSR_TESTER_VCC_OFS) val |= (1 << CSR_TSTCVCC_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
time.sleep(1) time.sleep(1)
...@@ -237,7 +237,7 @@ def main(bus, tname, inf, log): ...@@ -237,7 +237,7 @@ def main(bus, tname, inf, log):
# Enable multiplexer # Enable multiplexer
print("Enabling multiplexers") print("Enabling multiplexers")
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val |= (1 << CSR_TESTER_MUX_EN_OFS) val |= (1 << CSR_TSTCMUXEN_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
time.sleep(1) time.sleep(1)
...@@ -267,7 +267,7 @@ def main(bus, tname, inf, log): ...@@ -267,7 +267,7 @@ def main(bus, tname, inf, log):
# Disable multiplexer # Disable multiplexer
print("Disabling multiplexers") print("Disabling multiplexers")
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val &= ~(1 << CSR_TESTER_MUX_EN_OFS) val &= ~(1 << CSR_TSTCMUXEN_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
time.sleep(1) time.sleep(1)
...@@ -303,7 +303,7 @@ def main(bus, tname, inf, log): ...@@ -303,7 +303,7 @@ def main(bus, tname, inf, log):
# Enable multiplexer # Enable multiplexer
print("Enabling multiplexers") print("Enabling multiplexers")
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val |= (1 << CSR_TESTER_MUX_EN_OFS) val |= (1 << CSR_TSTCMUXEN_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
time.sleep(1) time.sleep(1)
...@@ -333,7 +333,7 @@ def main(bus, tname, inf, log): ...@@ -333,7 +333,7 @@ def main(bus, tname, inf, log):
# Disable multiplexer # Disable multiplexer
print("Disabling multiplexers") print("Disabling multiplexers")
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val &= ~(1 << CSR_TESTER_MUX_EN_OFS) val &= ~(1 << CSR_TSTCMUXEN_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
return pel.get() return pel.get()
...@@ -346,8 +346,8 @@ def main(bus, tname, inf, log): ...@@ -346,8 +346,8 @@ def main(bus, tname, inf, log):
finally: finally:
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val &= ~(1 << CSR_TESTER_VCC_OFS) val &= ~(1 << CSR_TSTCVCC_OFS)
val &= ~(1 << CSR_TESTER_MUX_EN_OFS) val &= ~(1 << CSR_TSTCMUXEN_OFS)
val &= ~(1 << CSR_TESTER_MUX_S0_OFS) val &= ~(1 << CSR_TSTCS0_OFS)
val &= ~(1 << CSR_TESTER_MUX_S1_OFS) val &= ~(1 << CSR_TSTCS1_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
pts/python/ttl_pulse_switch.py
View file @ e9f2131e
...@@ -163,12 +163,12 @@ def main(bus, tname, inf, log): ...@@ -163,12 +163,12 @@ def main(bus, tname, inf, log):
# Enable pulse generation # Enable pulse generation
val = bus.vv_read(CSR) val = bus.vv_read(CSR)
val |= (1 << CSR_TTL_EN_OFS) val |= (1 << CSR_TTLPT_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
# wait one second, then disable pulse generation # wait one second, then disable pulse generation
time.sleep(1) time.sleep(1)
val &= ~(1 << CSR_TTL_EN_OFS) val &= ~(1 << CSR_TTLPT_OFS)
bus.vv_write(CSR, val) bus.vv_write(CSR, val)
# Read the channel registers # Read the channel registers
...@@ -200,7 +200,7 @@ def main(bus, tname, inf, log): ...@@ -200,7 +200,7 @@ def main(bus, tname, inf, log):
pel.set(msg) pel.set(msg)
# Switches test # Switches test
switches = (bus.vv_read(CSR) >> CSR_SWITCHES_OFS) & 0xff switches = (bus.vv_read(CSR) >> CSR_SWITCH_OFS) & 0xff
if (switches != 0x80): if (switches != 0x80):
msg = "ERROR: Switches readout (0x%x) incorrect - expected 0x80" % switches msg = "ERROR: Switches readout (0x%x) incorrect - expected 0x80" % switches
pel.set(msg) pel.set(msg)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment