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Conv TTL RS485 - Testing
Commit c80e204a authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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hdl: Made DAC, PLL test logic work 

The issue was an errant reset signal presented to the clock counters, which had
an active-high reset signal instead of the normally-used active-low reset. This
has been fixed and the test logic now works as expected.
parent 544bd0d1
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Showing with 56 additions and 52 deletions
hdl/top/pts.ucf
View file @ c80e204a
......@@ -275,19 +275,19 @@ NET "vme_ga_i[4]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# DAC control
#-----------------------------------------------------------------------------
NET "dac20_din_o" LOC = AB14;
NET "dac20_din_o" IOSTANDARD = LVCMOS33;
NET "dac20_sclk_o" LOC = AA14;
NET "dac20_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac20_sync_n_o" LOC = AB15;
NET "dac20_sync_n_o" IOSTANDARD = LVCMOS33;
NET "dac125_din_o" LOC = W14;
NET "dac125_din_o" IOSTANDARD = LVCMOS33;
NET "dac125_sclk_o" LOC = Y14;
NET "dac125_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac125_sync_n_o" LOC = W13;
NET "dac125_sync_n_o" IOSTANDARD = LVCMOS33;
NET "dac_20_din_o" LOC = AB14;
NET "dac_20_din_o" IOSTANDARD = LVCMOS33;
NET "dac_20_sclk_o" LOC = AA14;
NET "dac_20_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac_20_sync_n_o" LOC = AB15;
NET "dac_20_sync_n_o" IOSTANDARD = LVCMOS33;
NET "dac_125_din_o" LOC = W14;
NET "dac_125_din_o" IOSTANDARD = LVCMOS33;
NET "dac_125_sclk_o" LOC = Y14;
NET "dac_125_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac_125_sync_n_o" LOC = W13;
NET "dac_125_sync_n_o" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# SFP connection
......
hdl/top/pts.vhd
View file @ c80e204a
......@@ -97,13 +97,13 @@ entity pts is
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o : out std_logic;
dac20_sclk_o : out std_logic;
dac20_sync_n_o : out std_logic;
dac_20_din_o : out std_logic;
dac_20_sclk_o : out std_logic;
dac_20_sync_n_o : out std_logic;
-- 125 MHz clock generator control
dac125_din_o : out std_logic;
dac125_sclk_o : out std_logic;
dac125_sync_n_o : out std_logic;
dac_125_din_o : out std_logic;
dac_125_sclk_o : out std_logic;
dac_125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
......@@ -182,20 +182,20 @@ architecture arch of pts is
constant c_addr_endpoint : t_wishbone_address := x"00000200";
constant c_addr_minic : t_wishbone_address := x"00000400";
constant c_addr_dpram : t_wishbone_address := x"00000800";
constant c_addr_pulse_cntrs : t_wishbone_address := x"00000C00";
constant c_addr_pulse_cntrs : t_wishbone_address := x"00000c00";
-- address mask definitions
constant c_mask_pts_regs : t_wishbone_address := x"00000FF0";
constant c_mask_onewire_mst : t_wishbone_address := x"00000FF0";
constant c_mask_dac_spi_125 : t_wishbone_address := x"00000FE0";
constant c_mask_dac_spi_20 : t_wishbone_address := x"00000FE0";
constant c_mask_clk_info_125 : t_wishbone_address := x"00000F60";
constant c_mask_clk_info_20 : t_wishbone_address := x"00000F60";
constant c_mask_sfp_i2c : t_wishbone_address := x"00000F60";
constant c_mask_endpoint : t_wishbone_address := x"00000E00";
constant c_mask_minic : t_wishbone_address := x"00000C00";
constant c_mask_dpram : t_wishbone_address := x"00000C00";
constant c_mask_pulse_cntrs : t_wishbone_address := x"00000C00";
constant c_mask_pts_regs : t_wishbone_address := x"00000ff0";
constant c_mask_onewire_mst : t_wishbone_address := x"00000ff0";
constant c_mask_dac_spi_125 : t_wishbone_address := x"00000fe0";
constant c_mask_dac_spi_20 : t_wishbone_address := x"00000fe0";
constant c_mask_clk_info_125 : t_wishbone_address := x"00000f60";
constant c_mask_clk_info_20 : t_wishbone_address := x"00000f60";
constant c_mask_sfp_i2c : t_wishbone_address := x"00000f60";
constant c_mask_endpoint : t_wishbone_address := x"00000e00";
constant c_mask_minic : t_wishbone_address := x"00000c00";
constant c_mask_dpram : t_wishbone_address := x"00000c00";
constant c_mask_pulse_cntrs : t_wishbone_address := x"00000c00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
......@@ -443,9 +443,9 @@ architecture arch of pts is
pulse_cnt_rearch6o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch6o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6ICR'
pulse_cnt_rearch16_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch16_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch16_load_o : out std_logic
pulse_cnt_rearch6i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch6i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch6i_load_o : out std_logic
);
end component pulse_cnt_wb;
......@@ -508,6 +508,7 @@ architecture arch of pts is
-- Reset signals
signal rst_20_n : std_logic;
signal rst_20 : std_logic;
signal rst_125_n : std_logic;
signal rst_ext : std_logic;
......@@ -636,7 +637,10 @@ begin
rst_n_o => rst_20_n
);
-- Synchronize 20-MHz reset signal into 125-MHz clock domain
-- Create an active-high reset signal
rst_20 <= not rst_20_n;
-- Create a reset signal in the 125-MHz clock domain
cmp_rst_125_sync : gc_sync_ffs
port map
(
......@@ -841,14 +845,14 @@ begin
-- 20-MHz VCXO test
-----------------------------------------------------------------------------
-- First, create the reset signal for the 20-MHz clock counter
cnt_20_actual_rst <= cnt_20_rst or (not rst_20_n);
cnt_20_actual_rst <= cnt_20_rst or rst_20;
-- Instantiate clock info slave
cmp_clk_info_20 : clk_info_wb_slave
port map
(
wb_clk_i => clk_20_i,
rst_i => rst_20_n,
rst_i => rst_20,
wb_cyc_i => xbar_master_out(c_slv_clk_info_20).cyc,
wb_stb_i => xbar_master_out(c_slv_clk_info_20).stb,
......@@ -907,26 +911,23 @@ begin
wb_stall_o => xbar_master_in(c_slv_dac_spi_20).stall,
pad_cs_o => dac_20_sync_n,
pad_sclk_o => dac20_sclk_o,
pad_mosi_o => dac20_din_o,
pad_sclk_o => dac_20_sclk_o,
pad_mosi_o => dac_20_din_o,
pad_miso_i => '0'
);
-- Finally, assign the SYNC_N output to the DAC
dac20_sync_n_o <= dac_20_sync_n(0);
dac_20_sync_n_o <= dac_20_sync_n(0);
-----------------------------------------------------------------------------
-- 125-MHz PLL test
-----------------------------------------------------------------------------
-- First, create a reset signal for the 125-MHz clock counter
cnt_125_actual_rst <= cnt_125_rst or (not rst_125_n);
-- Instantiate clock info slave
cmp_clk_info_125 : clk_info_wb_slave
port map
(
wb_clk_i => clk_20_i,
rst_i => rst_20_n,
rst_i => rst_20,
wb_cyc_i => xbar_master_out(c_slv_clk_info_125).cyc,
wb_stb_i => xbar_master_out(c_slv_clk_info_125).stb,
......@@ -1000,6 +1001,9 @@ begin
rd_i => '1'
);
-- Create a reset signal for the 125-MHz clock counter
cnt_125_actual_rst <= cnt_125_rst or (not rst_125_n);
-- Instantiate increment counter for 125-MHz clock
cmp_incr_counter_125 : incr_counter
generic map
......@@ -1041,13 +1045,13 @@ begin
wb_stall_o => xbar_master_in(c_slv_dac_spi_125).stall,
pad_cs_o => dac_125_sync_n,
pad_sclk_o => dac125_sclk_o,
pad_mosi_o => dac125_din_o,
pad_sclk_o => dac_125_sclk_o,
pad_mosi_o => dac_125_din_o,
pad_miso_i => '0'
);
-- Finally, assign the SYNC_N output to the DAC
dac125_sync_n_o <= dac_125_sync_n(0);
dac_125_sync_n_o <= dac_125_sync_n(0);
--============================================================================
-- Thermometer test logic
......@@ -1119,11 +1123,11 @@ begin
pulse_o => ttl_pulses(0)
);
-- Assign the trigger inputs to internal signals
-- Assign the TTL, INV-TTL inputs to internal signals
ttl_trigs_a(5 downto 0) <= not ttl_n_i;
ttl_trigs_a(9 downto 6) <= not inv_n_i;
-- Synchronize these triggers in the 20-MHz clock domain
-- Synchronize these signals in the 20-MHz clock domain
gen_ttl_sync_chains : for i in 0 to 9 generate
cmp_ttl_sync_chain : gc_sync_ffs
port map
......@@ -1325,9 +1329,9 @@ begin
pulse_cnt_rearch6o_o => opcr_ldval(15),
pulse_cnt_rearch6o_i => std_logic_vector(opcr(15)),
pulse_cnt_rearch6o_load_o => opcr_ld(15),
pulse_cnt_rearch16_o => ipcr_ldval(15),
pulse_cnt_rearch16_i => std_logic_vector(ipcr(15)),
pulse_cnt_rearch16_load_o => ipcr_ld(15)
pulse_cnt_rearch6i_o => ipcr_ldval(15),
pulse_cnt_rearch6i_i => std_logic_vector(ipcr(15)),
pulse_cnt_rearch6i_load_o => ipcr_ld(15)
);
--============================================================================
......
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