hdl: Added logic for clock test, not yet working

a0db8422 · Theodor-Adrian Stana · 644df85b · a0db8422 · a0db8422
Commit a0db8422 authored Oct 31, 2014 by Theodor-Adrian Stana
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Showing with 327 additions and 11 deletions

clk_info_wb_slave.vhd hdl/modules/clk_info_wb_slave.vhd +1 -1

pts.vhd hdl/top/pts.vhd +326 -10

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--- a/hdl/modules/clk_info_wb_slave.vhd
+++ b/hdl/modules/clk_info_wb_slave.vhd
@@ -113,7 +113,7 @@ begin
        clk_err_synch <= (others => '0');
      else
        clk_ok_synch  <= clk_ok_synch(0) & (counter_is_full_i);
-        clk_err_synch <= clk_ok_synch(0) & (clk_err);
+        clk_err_synch <= clk_err_synch(0) & (clk_err);
 		end if;
    end if;
  end process;

--- a/hdl/top/pts.vhd
+++ b/hdl/top/pts.vhd