Commit 8c198c17 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Added wbgen-generated tex files for registers in HDL guide

parent 2a022891
\subsection{Clock counter registers}
\label{app:clk-info}
Base address (125-MHz counter): 0x100 \\
Base address (20-MHz counter): 0x120
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x00 & 0x00000000 & CNTFULLR & Counter full register \\
0x04 & & & \textit{Reserved} \\
0x08 & & & \textit{Reserved} \\
0x0c & 0x00000000 & CNTMAXR & Counter max value register \\
0x10 & 0x00000000 & CNTVALR & Counter current value register \\
0x14 & 0x00000000 & CNTRSTR & Counter reset register \\
0x18 & 0x00000000 & CNTENR & Counter enable register \\
0x1c & 0xc000ffee & CNTCHKR & Module check register \\
\end{longtable}
}
\subsubsection{CNTFULLR}
\label{app:clk-info-cntfullr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FULL
} [\emph{read-only}]: Full status bit
\\
1 -- Counter has reached value in MAX register \\ 0 -- Counter not full
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CNTMAXR -- Counter maximum value}
\label{app:clk-info-cntmaxr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CNTMAX
} [\emph{read-write}]: Maximum value for the counter to count to. \\
When this value is reached, the counter will stop and needs to be reset via the CNTRSTR register.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CNTVALR -- Counter current value register}
\label{app:clk-info-cntvalr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CNTVAL
} [\emph{read-only}]: Current value of the counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CNTRSTR}
\label{app:clk-info-cntrstr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CNTRST}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CNTRST
} [\emph{read-write}]: Counter reset bit
\\
1 -- Reset counter \\ 0 -- No effect
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CNTENR}
\label{app:clk-info-cntenr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CNTEN}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CNTEN
} [\emph{read-write}]: Counter enable bit
\\
1 -- Enable counter \\ 0 -- No effect
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CNTCHKR -- Module check register}
\label{app:clk-info-cntchckr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CNTCHK
} [\emph{read-only}]: Module check bits
\\
Reset value: 0xc000ffee
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsection{PTS control and status registers}
\label{subsec:wbgen:pts}
Registers of the PTS firmware
Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x0 & g\_board\_id & BIDR & Board ID Register\\
0x4 & 0xf{}f{}f{}f{}f{}f{}f{}f & CSR & Control and Status Register\\
0x8 & 0xf{}f{}f{}f{}f{}f{}f{}f & LSR & Line Status Register\\
0xc & 0xf{}f{}f{}f{}f{}f{}f{}f & TER & Termination Enable Register\\
\end{longtable}
}
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: g\_board\_id
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CSR -- Control and Status Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCH[7:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}TSTCS1}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}TSTCS0} & \multicolumn{1}{|c|}{\cellcolor{gray!25}TSTCMUXEN} & \multicolumn{1}{|c|}{\cellcolor{gray!25}TSTCVCC} & \multicolumn{1}{|c|}{\cellcolor{gray!25}REARPT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}TTLPT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RLEDT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}STLEDT} & \multicolumn{1}{|c|}{\cellcolor{gray!25}CHLEDT}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CHLEDT
} [\emph{read/write}]: Channel pulse LED enable
\\
1 -- Enable channel LED sequencing 0 -- No effect
\end{small}
\item \begin{small}
{\bf
STLEDT
} [\emph{read/write}]: Status LED enable
\\
1 -- Enable front panel bicolor LED sequencing 0 -- No effect
\end{small}
\item \begin{small}
{\bf
RLEDT
} [\emph{read/write}]: Rear pulse LED line
\\
1 -- Set LED lines high 0 -- No effect
\end{small}
\item \begin{small}
{\bf
TTLPT
} [\emph{read/write}]: TTL test enable
\\
1 -- Enable pulse generation from CH1 0 -- No effect
\end{small}
\item \begin{small}
{\bf
REARPT
} [\emph{read/write}]: Rear pulse enable
\\
1 -- Enable rear panel pulse generation 0 -- No effect
\end{small}
\item \begin{small}
{\bf
TSTCVCC
} [\emph{read/write}]: RS485 tester card VCC
\\
1 -- Power on the RS485 tester 0 -- No effect
\end{small}
\item \begin{small}
{\bf
TSTCMUXEN
} [\emph{read/write}]: RS485 tester card MUX enable
\\
1 -- Enable multiplexers on RS485 tester 0 -- No effect
\end{small}
\item \begin{small}
{\bf
TSTCS0
} [\emph{read/write}]: RS485 tester card MUX S0 line
\\
RS485 tester S0 line on multiplexers
\end{small}
\item \begin{small}
{\bf
TSTCS1
} [\emph{read/write}]: RS485 tester card MUX S1 line
\\
RS485 tester S1 line on multiplexers
\end{small}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 -- Reset bit unlocked 0 -- Reset bit locked
\end{small}
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit
\\
1 -- initiate logic reset 0 -- no reset
\end{small}
\item \begin{small}
{\bf
SWITCH
} [\emph{read-only}]: switches
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM
\end{small}
\item \begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{LSR -- Line Status Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[3:2]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONTFS[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[3:2]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONT[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FRONT
} [\emph{read-only}]: Front panel channel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTINV
} [\emph{read-only}]: Front panel INV-TTL input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REAR
} [\emph{read-only}]: Rear panel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTFS
} [\emph{read-only}]: Front panel input failsafe state
\\
High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTINVFS
} [\emph{read-only}]: Front panel inverter input failsafe state
\\
High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REARFS
} [\emph{read-only}]: Rear panel input failsafe state
\\
High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TER -- Termination Enable Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}OTERM[5:2]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}OTERM[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}ITERM[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
ITERM
} [\emph{read/write}]: Input termination enable
\\
Set high to enable the channel input termination\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
OTERM
} [\emph{read/write}]: Output termination enable
\\
Set high to enable the channel output terminations\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
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