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Conv TTL RS485 - Testing
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Conv TTL RS485 - Testing
Commits
8a96cf52
Commit
8a96cf52
authored
Oct 27, 2017
by
Denia Bouhired-Ferrag
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modified pts-regs port map to reflect new 3 bit addressing instead of 2
parent
072a4bc4
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pts.vhd
hdl/top/pts.vhd
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hdl/top/pts.vhd
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8a96cf52
...
...
@@ -271,7 +271,7 @@ architecture arch of pts is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
...
...
@@ -940,7 +940,7 @@ begin
(
rst_n_i
=>
rst_20_n
,
clk_sys_i
=>
clk_20_i
,
wb_adr_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
adr
(
3
downto
2
),
wb_adr_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
adr
(
4
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_pts_regs
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
cyc
,
...
...
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