Commit 8a61389f authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

sw: PTS makefile now in place and LED test works

parent 0e2e30ab
ELMAIP = cfvm-864-celma1
ELMAPWD = Gr@nBr@st0
ELMASLOT = 1
all:
mkdir -p pts-conv-ttl-rs485/boot
mkdir -p pts-conv-ttl-rs485/tests
mkdir -p pts-conv-ttl-rs485/lib
cp -r shell/ pts-conv-ttl-rs485/
mv pts-conv-ttl-rs485/shell/program pts-conv-ttl-rs485/boot
wget -P pts-conv-ttl-rs485/boot http://www.ohwr.org/attachments/download/3639/pts.bit
cp pts.py pts-conv-ttl-rs485
cp jpts.py pts-conv-ttl-rs485
cp leds.py pts-conv-ttl-rs485/tests/test00.py
cp python/pts.py pts-conv-ttl-rs485
cp python/jpts.py pts-conv-ttl-rs485
cp python/vv_pts.py pts-conv-ttl-rs485/lib/
cp python/ptsexcept.py pts-conv-ttl-rs485/lib/
cp python/ptsdefine.py pts-conv-ttl-rs485/lib/
sed -i "s/ELMAIP = \"\"/ELMAIP = \"$(ELMAIP)\"/" pts-conv-ttl-rs485/lib/ptsdefine.py
sed -i "s/ELMAPWD = \"\"/ELMAPWD = \"$(ELMAPWD)\"/" pts-conv-ttl-rs485/lib/ptsdefine.py
sed -i "s/ELMASLOT = 4/ELMASLOT = $(ELMASLOT)/" pts-conv-ttl-rs485/lib/ptsdefine.py
cp python/leds.py pts-conv-ttl-rs485/tests/
ln -s tests/leds.py pts-conv-ttl-rs485/test01.py
clean:
rm -rf pts-conv-ttl-rs485
......@@ -48,7 +48,9 @@
## Import
##------------------------------------------------------------------------------------------------
import sys
sys.path.append('lib/')
import ptsexcept
import ptsdefine
import time
import traceback
import socket
......@@ -56,8 +58,6 @@ from optparse import OptionParser
from vv_pts import *
from os import path, access, R_OK, readlink
sys.path.append('.')
##-------------------------------------------------------------------------------------------------
## Method to get the test program a symlink points to
##-------------------------------------------------------------------------------------------------
......@@ -105,7 +105,7 @@ if __name__ == '__main__':
use = "Usage: %prog [--lun=0 --snum=1234 5678 --debug] test_num,run_count test_num,run_count..."
parser = OptionParser(usage=use, version="pts version 2.0")
parser.add_option("-l", "--lun", help="Logical Unit Number", type="int", default=4, dest="lun")
parser.add_option("-l", "--lun", help="Logical Unit Number", type="int", default=ELMASLOT, dest="lun")
parser.add_option("-s", "--snum", help="Serial number(s)", dest="snum", action="store", nargs=2, default=("0","0"))
parser.add_option("-n", "--name", help="Board name", dest="board_name", default="ttlbl")
parser.add_option("-b", "--bus", help="Bus VME/PCI/SKT", dest="bus_type", default="SKT")
......@@ -217,7 +217,7 @@ if __name__ == '__main__':
try:
# First load a firmware and read back a register to confirm correct load.
if bus.vv_load()==1:
msg = "INFO:Found TTLBL board in slot:%d OK\n" % (lun)
msg = "INFO:Found CONV-TTL-RS485 board in slot:%d OK\n" % (lun)
inf.write(msg + '\n')
# Each test is passed the test name, the log and info files and the
......
......@@ -47,6 +47,7 @@
# Import system modules
import sys
sys.path.append("../lib/")
import time
import os, errno, re, sys, struct
import os.path
......@@ -56,7 +57,7 @@ import traceback
from ctypes import *
from ptsexcept import *
from vv_pts import *
from pts_memmap import *
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## main --
......@@ -73,7 +74,7 @@ def main(bus,tname,inf,log):
try:
# First phase of LED test, enable pulse LED sequencing
bus.vv_write(CSR, 1 << CSR_PULSE_LED_EN_OFS)
bus.vv_write(CSR, 1 << CSR_FRONT_LED_EN_OFS)
# The firmware should blink the LEDs, ask the operator for input
inp = raw_input("--> Are the channel LEDs blinking one by one? yes/no: ")
......
......@@ -127,7 +127,8 @@ if __name__ == '__main__':
# Clear the log dir (if any) and (re-)create it to store log and info files
subprocess.call("rm -rf ./log; mkdir log; chmod 777 log", shell=True, stdout=fnull, stderr=fnull)
men_off()
print "---Turn off ELMA!!"
#men_off()
# Scan the first barcode
while True:
......@@ -162,16 +163,18 @@ if __name__ == '__main__':
ok = raw_input("--> Please type 'ok' to continue: ")
print "\n"
men_on()
print "---Turn on ELMA!!"
#men_on()
print "Loading FPGA bitstream..."
subprocess.call("cd boot; ./flash.sh; cd ..", shell=True, stdout=fnull, stderr=fnull)
time.sleep(1)
print "FPGA BITSTREAM......"
# print "Loading FPGA bitstream..."
# subprocess.call("cd boot; ./program; cd ..", shell=True, stdout=fnull, stderr=fnull)
# time.sleep(1)
# Run JPTS in another shell script; JPTS will handle running each of the test scripts
cmd = "xterm -e ./jpts.py -s %s %s" % (sn1, sn2)
print "Running tests :%s\n" % (cmd)
subprocess.call(cmd, shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call(cmd, shell=True, stdout=fnull, stderr=fnull)
# # After JPTS has finished, download release bitstream to EEPROM chip if none of the tests has failed
# print "Loading CONV-TTL-RS485 release bitstream\n"
......@@ -208,16 +211,17 @@ if __name__ == '__main__':
#
# We're done, turn off the VME crate
print "\nTesting completed!"
men_off()
print "---Turn off ELMA!!"
#men_off()
# Finally, print anything that went wrong throughout the test programs by grepping the log and info files and
# exit when the user desires.
msg = "\n--> To see all the PTS errors, type 'ok': "
ok = raw_input(msg)
if ok.find("ok") != -1:
subprocess.call("grep FAIL /home/pts/ubuntu/ttlbl/log/*.log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("grep ERROR /home/pts/ubuntu/ttlbl/log/*.inf", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("grep WARNING /home/pts/ubuntu/ttlbl/log/*.inf", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("grep FAIL log/*.log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("grep ERROR log/*.inf", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("grep WARNING log/*.inf", shell=True, stdout=sys.stdout, stderr=sys.stderr)
print ""
print "--> You may now unplug the CONV-TTL-BLO board %s-%s\n" % (sn1, sn2)
......
#===============================================================================
# CERN (BE-CO-HT)
# PTS definitions file
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
#
# date of creation: 2013-10-31
#
# version: 1.0
#
# description:
# This module contains register address definitions that are used across the
# various tests. Importing this module inside a test script makes these
# definitions available for use within a bus.vv_write or bus.vv_read method
# (see vv_pts.py for these methods).
#
# dependencies:
# none.
#
# references:
# none.
#
#===============================================================================
# GNU LESSER GENERAL PUBLIC LICENSE
#===============================================================================
# This source file is free software; you can redistribute it and/or modify it
# under the terms of the GNU Lesser General Public License as published by the
# Free Software Foundation; either version 2.1 of the License, or (at your
# option) any later version. This source is distributed in the hope that it
# will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
# See the GNU Lesser General Public License for more details. You should have
# received a copy of the GNU Lesser General Public License along with this
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
# 2014-10-31 Theodor Stana t.stana@cern.ch File created
#===============================================================================
# TODO: -
#===============================================================================
# ELMA crate definitions
ELMAIP = ""
ELMAPWD = ""
ELMASLOT = 4
# Board ID register
BIDR = 0x000
BIDR_ARR = [ "TBLO", "T485" ]
# Control and Status Register
CSR = 0x004
CSR_FRONT_LED_EN_OFS = 0
CSR_REAR_LED_EN_OFS = 1
CSR_STAT_LED_EN_OFS = 2
CSR_TTL_EN_OFS = 0
CSR_BLO_EN_OFS = 1
CSR_BLO_LED_OFS = 2
CSR_RST_UNLOCK_OFS = 14
CSR_RST_OFS = 15
# 1-Wire base address, used in therm_id.py
TEMP_1WIRE_BASE = 0x010
# Pulse counter base address, used in ttl_pulse.py
PULSE_CNT_BASE = 0xC00
# DAC and clock info registers and offsets, used in dac_vcxo_pll.py
PLL_DAC_BASE = 0X020
VCXO_DAC_BASE = 0x080
PLL_CLKINFO_BASE = 0x100
VCXO_CLKINFO_BASE = 0x120
CLKINFO_RST_OFS = 0x014
CLKINFO_ENABLE_OFS = 0x018
CLKINFO_VALUE_OFS = 0x010
# SFP I2C master base address, used in sfp_eeprom.py
SFP_EEPROM_BASE = 0x140
# SFP endpoint, miniNIC and buffer RAM base addresses and offsets,
# used in sfp_test.py
SFP_BASE = 0x200
SFP_ENDPOINT_OFS = 0x000
SFP_MINIC_OFS = 0x200
SFP_DPRAM_OFS = 0x600
class PtsException(Exception):
pass
class PtsCritical(PtsException):
"""critical error, abort the whole test suite"""
pass
class PtsUser(PtsException):
"""error, user intervention required"""
pass
class PtsWarning(PtsException):
"""warning, a cautionary message should be displayed"""
pass
class PtsInvalid(PtsException):
"""reserved: invalid parameters"""
class PtsNoBatch(PtsInvalid):
"""reserved: a suite was created without batch of tests to run"""
pass
class PtsBadTestNo(PtsInvalid):
"""reserved: a bad test number was given"""
pass
class PtsInfo(PtsException):
"""Information from the test, not an error"""
class PtsError(PtsException):
"""error, continue remaining tests in test suite"""
pass
class PTS_ERROR_LOGGER:
"""Log errors and continue testing without raising an exception"""
def __init__(self, inf, log):
self.inf = inf
self.log = log
self.er_count = 0
def set(self, msg):
self.inf.write(msg + "\n")
self.log.write(msg + "\n")
self.er_count = self.er_count + 1
def get(self):
return self.er_count
if __name__ == '__main__':
pass
#! /usr/bin/python
# coding: utf8
# Copyright CERN, 2014
# Author: Julian Lewis <julian.lewis@cern.ch>
# Theodor Stana <t.stana@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
import sys
import time
from ctypes import *
import os, errno, re, sys, struct
import os.path
from ptsexcept import *
import socket
from socket import SHUT_RDWR
import binascii
from ptsdefine import *
class BusException(Exception):
pass
class BusWarning(Exception):
pass
class VME(object):
def __init__(self,lun):
""" The vmeio driver lun (logical unit).
At driver install time, insmod maps lun on to
VME (csr, application window, interrupts).
Lun is set when creating a VME object
"""
self.lib = CDLL('./libvv_pts.so')
int = 0
if type(lun) == type(int):
self.lun = lun
else:
self.lun = int
raise BusWarning("Warning: VME __init__: Bad lun, default to 0")
def vv_init(self):
""" Initialize the library
loads the libvv_pts.so dynamic library
opens vmeio driver for lun 0
prepares the svec bootloader
"""
self.handle = cast(self.lib.vv_init(self.lun), c_void_p)
if self.handle == 0:
raise BusException("Failed vv_init: Can't initialize VME library")
return self.handle
def vv_close(self):
""" Close the driver and free up resources
"""
cc = self.lib.vv_close(self.handle)
self.handle = 0
if cc != 0:
raise BusException("Failed vv_close: Can't close VME library")
return cc
def vv_load(self, bit_stream, id):
""" Load the FPGA
reads the FPGA bitstream image file
initializes the svec bootloader
loads the FPGA image
initializes the loaded VME core for lun 0
"""
cc = self.lib.vv_load(self.handle, bit_stream, id)
if cc == -1:
raise BusException("Failed vv_load: Can't load bit_stream: %s" % (bit_stream))
return cc
def vv_write(self, byte_offset, value):
""" Write to the application FPGA wishbone bus
The byte offset will be aligned to D32
The value is a 32 bit integer
"""
x = c_int(value)
cc = self.lib.vv_write(self.handle, byte_offset, byref(x), 4)
if cc != 0:
raise BusException("Failed vv_write: offset:0x%X value:%d" % (byte_offset, value))
return cc
def vv_write_array(self, byte_offset, buf, size):
""" Write an array of data from the string array buf
size is the number of bytes to write aligned D32
"""
cc = self.lib.vv_write(self.handle, byte_offset, id(buf), size)
if cc != 0:
raise BusException("Failed vv_write_array: offset:0x%X size:%d" % (byte_offset, size))
return cc
def vv_read(self, byte_offset):
""" Read from the application FPGA wishbone bus
The byte offset will be aligned to D32
The value will contain the 32 bit integer read
"""
x = c_int(0)
cc = self.lib.vv_read(self.handle, byte_offset, byref(x), 4)
value = x.value
if cc != 0:
raise BusException("Failed vv_read: offset:0x%X" % (byte_offset))
return value & 0xFFFFFFFF
def vv_read_array(self, byte_offset, buf, size):
""" Read size bytes into the string array buf
The byte_offset and size will be D32 aligned
"""
cc = self.lib.vv_read(self.handle, byte_offset, id(buf), size)
if cc != 0:
raise BusException("Failed vv_read_array: offset:0x%X size:%d" % (byte_offset, size))
return cc
def vv_irqwait(self):
""" Wait for an interrupt
An ISR is installed and reads the interrupt source register from the FPGA application
If no interrupt occurs after one second the return is -1 and errno is ETIME
"""
x = c_int(0)
cc = self.lib.vv_irqwait(self.handle, byref(x))
irq_src = x.value
if cc != 0:
raise BusException("Failed vv_irqwait: No interrupt")
return irq_src
class PCI(object):
def __init__(self,lun):
""" The pciio driver lun (logical unit).
"""
self.lib = CDLL('./libvv_pts.so')
int = 0
if type(lun) == type(int):
self.lun = lun
else:
self.lun = int
raise BusWarning("Warning: PCI __init__: Bad lun, default to 0")
class SKT(object):
def __init__(self,lun):
""" Telnet access over a socket to ELMA I2C bus
"""
int = ELMASLOT
if type(lun) == type(int):
self.lun = lun
else:
self.lun = int
raise BusWarning("Warning: SKT __init__: Bad lun=(slot), default to %s" % int)
self.base = 0;
s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
s.connect((ELMAIP, 23))
s.recv(1000)
s.send("admin\r\n")
s.recv(1000)
s.send(ELMAPWD + "\r\n")
s.recv(1000)
self.handle = s
# get crate firmware version, to apply proper address in readreg/writereg
self.handle.send("version\r\n")
ver = self.handle.recv(1000)
pos = ver.find("Software version")
if (pos == -1):
print("Unexpected response from \"version\" command, exiting...")
self.close()
sys.exit(2)
ver = float(ver[pos+17:pos+21])
self.ver = ver
def vv_write(self, byte_offset, value):
""" Write to the application FPGA via ELMA telnet
The byte offset will be aligned to D32
The value is a 32 bit integer
"""
try:
cm = "writereg %d %x %x\r\n" % (self.lun, byte_offset, value)
if (self.ver < 2.27):
rn = byte_offset/4 + 1
cm = "writereg %d %d %x\r\n" % (self.lun,rn,value)
#print "vv_write:Debug:cm:%s\n" % (cm)
self.handle.send(cm)
orig = self.handle.recv(1000)
except Exception as e:
msg = "vv_write: No reply from register at address 0x%03x " % (byte_offset)
print msg+orig
raise BusException(msg)
return self.handle.recv(1000).find("Done")
def vv_read(self, byte_offset):
""" Read from the application FPGA via ELMA telnet
The byte offset will be aligned to D32
The value will contain the 32 bit integer read
"""
try:
cm = "readreg %d %x\r\n" % (self.lun, byte_offset)
if (self.ver < 2.27):
rn = byte_offset/4 + 1
cm = "readreg %d %d\r\n" % (self.lun,rn)
#print "vv_read:Debug:cm:%s\n" % (cm)
self.handle.send(cm)
orig = self.handle.recv(1000)
rp = orig
rp = rp.split(" ")[3]
rp = rp.split("\n")[0]
rp = int(rp,16)
except Exception as e:
msg = "vv_read: No reply from register at address 0x%03x " % (byte_offset)
print msg+orig
raise BusException(msg)
return rp
def vv_load(self):
""" Load the FPGA, its sort of a NO-OP in SKT class
"""
bid = self.vv_read(BIDR)
bid = binascii.unhexlify("%s" % "{0:x}".format(bid))
if bid in BIDR_ARR:
return 1
else:
raise BusException("Failed vv_load: FPGA: Bad board ID: %s" % bid)
return 0
def vv_init(self):
""" Init the library, its a NO-OP in SKT class
"""
return self.handle
def vv_close(self):
""" Close the socket
"""
self.handle.shutdown(SHUT_RDWR)
self.handle.close()
self.handle = 0
return 0
#!/bin/bash
xc3sprog -c xpc pts.bit
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