hdl: Fixed small naming error in the pulse counter regs component

3513bd9d · Theodor-Adrian Stana · c80e204a · 3513bd9d · 3513bd9d
Commit 3513bd9d authored Nov 03, 2014 by Theodor-Adrian Stana
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Showing with 11 additions and 11 deletions

pulse_cnt_wb.vhd hdl/modules/pulse_cnt_wb.vhd +10 -10

pulse_cnt_wb.wb hdl/modules/pulse_cnt_wb.wb +1 -1

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--- a/hdl/modules/pulse_cnt_wb.vhd
+++ b/hdl/modules/pulse_cnt_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : pulse_cnt_wb.vhd
 -- Author         : auto-generated by wbgen2 from pulse_cnt_wb.wb
-- Created        : Fri Oct 31 14:58:53 2014
+-- Created        : Mon Nov  3 09:56:02 2014
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_wb.wb
@@ -152,9 +152,9 @@ entity pulse_cnt_wb is
    pulse_cnt_rearch6o_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch6o_load_o                : out    std_logic;
 -- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6ICR'
-    pulse_cnt_rearch16_o                     : out    std_logic_vector(31 downto 0);
-    pulse_cnt_rearch16_i                     : in     std_logic_vector(31 downto 0);
-    pulse_cnt_rearch16_load_o                : out    std_logic
+    pulse_cnt_rearch6i_o                     : out    std_logic_vector(31 downto 0);
+    pulse_cnt_rearch6i_i                     : in     std_logic_vector(31 downto 0);
+    pulse_cnt_rearch6i_load_o                : out    std_logic
  );
 end pulse_cnt_wb;

@@ -218,7 +218,7 @@ begin
      pulse_cnt_rearch5o_load_o <= '0';
      pulse_cnt_rearch5i_load_o <= '0';
      pulse_cnt_rearch6o_load_o <= '0';
-      pulse_cnt_rearch16_load_o <= '0';
+      pulse_cnt_rearch6i_load_o <= '0';
    elsif rising_edge(clk_sys_i) then
 -- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
@@ -256,7 +256,7 @@ begin
          pulse_cnt_rearch5o_load_o <= '0';
          pulse_cnt_rearch5i_load_o <= '0';
          pulse_cnt_rearch6o_load_o <= '0';
-          pulse_cnt_rearch16_load_o <= '0';
+          pulse_cnt_rearch6i_load_o <= '0';
          ack_in_progress <= '0';
        else
          pulse_cnt_ttlch1o_load_o <= '0';
@@ -290,7 +290,7 @@ begin
          pulse_cnt_rearch5o_load_o <= '0';
          pulse_cnt_rearch5i_load_o <= '0';
          pulse_cnt_rearch6o_load_o <= '0';
-          pulse_cnt_rearch16_load_o <= '0';
+          pulse_cnt_rearch6i_load_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
@@ -514,9 +514,9 @@ begin
            ack_in_progress <= '1';
          when "11111" => 
            if (wb_we_i = '1') then
-              pulse_cnt_rearch16_load_o <= '1';
+              pulse_cnt_rearch6i_load_o <= '1';
            end if;
-            rddata_reg(31 downto 0) <= pulse_cnt_rearch16_i;
+            rddata_reg(31 downto 0) <= pulse_cnt_rearch6i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
@@ -595,7 +595,7 @@ begin
 -- Pulse counter value
  pulse_cnt_rearch6o_o <= wrdata_reg(31 downto 0);
 -- Pulse counter value
-  pulse_cnt_rearch16_o <= wrdata_reg(31 downto 0);
+  pulse_cnt_rearch6i_o <= wrdata_reg(31 downto 0);
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
 -- ACK signal generation. Just pass the LSB of ACK counter.

--- a/hdl/modules/pulse_cnt_wb.wb
+++ b/hdl/modules/pulse_cnt_wb.wb
@@ -440,7 +440,7 @@ peripheral {

  reg {
    name = "REARCH6ICR";
-    prefix = "rearch16";
+    prefix = "rearch6i";
    description = "Rear CH6 input counter register";
    field {
      name = "Pulse counter value";