Commit 30f02bf6 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

hdl: Additions to rear test logic

The additions are:
- checking the fail-safe lines before passing the input pulse to the pulse
  counters
- adding a delay to the pulse generators, to account for hardware delay
  appearing on enable
parent e9a6591f
......@@ -742,6 +742,7 @@ architecture arch of pts is
signal rear_trigs_a : std_logic_vector(5 downto 0);
signal rear_trigs : std_logic_vector(5 downto 0);
signal rear_trigs_redge_p : std_logic_vector(5 downto 0);
signal rs485_fs : std_logic_vector(5 downto 0);
-- Pulse counter register signals
signal ipcr_ld : std_logic_vector(15 downto 0);
......@@ -921,7 +922,7 @@ begin
line_front <= not (ttl_n_i);
line_inv <= not (inv_n_i);
line_rear <= not (rs485_n_i);
line_rear_fs <= rs485_n_i nor rs485_fs_n_i;
line_rear_fs <= rs485_fs;
-- Regs to test I2C operation
cmp_pts_regs : pts_regs
......@@ -1640,12 +1641,14 @@ end generate gen_other_front_pulse_logic;
-- Compose the tester control lines out of the PTS reg bits
tester_ctrl <= tester_s1 & tester_s0 & tester_mux_en & tester_vcc;
-- Assign rear panel inputs to local signals
rear_trigs_a <= not rs485_n_i;
-- And now generate the logic for six pulse rep channels
-- Generate the logic for six pulse rep channels
gen_rear_test_logic : for i in 0 to 5 generate
-- Assign rear panel inputs to local signals
rs485_fs(i) <= rs485_n_i(i) nor rs485_fs_n_i(i);
rear_trigs_a(i) <= (not rs485_n_i(i)) when (rs485_fs(i) = '0') else
'0';
-- Synchronize the inputs to the 20-MHz clock domain
cmp_rear_sync_chain : gc_sync_ffs
port map
......@@ -1669,7 +1672,7 @@ gen_rear_test_logic : for i in 0 to 5 generate
en_i => rear_pulse_en,
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i => x"00000000",
delay_i => x"0000003c",
pwidth_i => x"00000014",
freq_i => x"00989680",
......
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