Commit 0cd02d01 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Finished HDL guide

parent 76b7c305
FILE=hdlg-pts-conv-ttl-rs485
all:
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
$(MAKE) -C fig clean
\begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{ \LARGE \textbf{CONV-TTL-RS485 PTS HDL Guide}}
\noindent \rule{\textwidth}{.1cm}
\hfill January 19, 2015
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
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@misc{onewire,
author = {Iztok Jeras},
title = {{sockit\_owm, 1-wire (onewire) master}},
year = 2011,
note = {\url{http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf}}
}
@misc{spi,
author = {Simon Srot},
title = {{SPI Master Core Specification}},
year = 2004,
note = {\url{http://opencores.org/websvn,filedetails?repname=spi&path=%2Fspi%2Ftrunk%2Fdoc%2Fspi.pdf}}
}
@misc{i2c-master,
author = {Richard Herveille},
title = {{I$2$C Master Core Specification}},
year = 2003,
note = {\url{http://opencores.org/websvn,filedetails?repname=i2c&path=%2Fi2c%2Ftrunk%2Fdoc%2Fi2c_specs.pdf}}
}
@misc{coding-guidelines,
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
note = {\url{http://www.ohwr.org/documents/24}}
}
@misc{ug,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-RS485 User Guide}},
howpublished = {\url{http://www.ohwr.org/documents/351}}
}
@misc{hdlg,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-RS485 HDL Guide}},
howpublished = {\url{http://www.ohwr.org/documents/389}}
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
howpublished = {\url{www.ohwr.org/attachments/download/2324/ELMA_SNMP_specification.pdf}}
}
@misc{pts-repo,
title = {{CONV-TTL-RS485 testing project repository}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-rs485-tst/repository}}
}
@misc{pts-userguide,
author = "{Theodor Adrian Stana}",
title = {{CONV-TTL-RS485 PTS User Guide}},
howpublished = {\url{http://www.ohwr.org/documents/390}}
}
@misc{pts-hwguide,
author = "{Theodor Adrian Stana}",
title = {{CONV-TTL-RS485 PTS Hardware Guide}},
howpublished = {\url{http://www.ohwr.org/documents/390}}
}
@misc{conv-common-gw-ohwr,
title = {{Converter board common gateware project page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-common-gw}}
}
@misc{wr-cores,
title = {{White Rabbit core collection on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/wr-cores/wiki/wrpc_core}}
}
%==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
\usepackage[
colorlinks = true,
linkcolor = black,
citecolor = black,
urlcolor = blue,
]{hyperref}
\usepackage{graphicx}
\usepackage{multirow}
\usepackage{longtable}
\usepackage{color}
\usepackage[toc,page]{appendix}
% Color package
\usepackage[usenames,dvipsnames,table]{xcolor}
% Header and footer customization
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Licensing info
%------------------------------------------------------------------------------
\pagebreak
\thispagestyle{empty}
\addcontentsline{toc}{section}{Licensing information}
\section*{Licensing information}
\noindent
This document is licensed under a Creative Commons Attribution-ShareAlike 4.0
International License. If you have not received a copy of the license along with this
work, see \\
\url{http://creativecommons.org/licenses/by-sa/4.0/}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\section*{Revision history}
\addcontentsline{toc}{section}{Revision history}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
19-01-2015 & 0.1 & First draft \\
\hline
\end{tabular}
}
%------------------------------------------------------------------------------
% Table of contents, list of figs, tables
%------------------------------------------------------------------------------
\pagebreak
\pdfbookmark[1]{\contentsname}{toc}
\tableofcontents
\pagebreak
\listoffigures
\listoftables
%------------------------------------------------------------------------------
% List of abbreviations
%------------------------------------------------------------------------------
\pagebreak
\section*{List of abbreviations}
\begin{tabular}{l l}
FPGA & Field-Programmable Gate Array \\
I$^2$C & Inter-Integrated Circuit \\
PTS & Production Test Suite \\
SFP & Small Form-factor Pluggable (transceiver) \\
VME & VERSAmodule Eurocard \\
\end{tabular}
\addcontentsline{toc}{section}{List of abbreviations}
%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
Production Test Suite (PTS) is the environment designed for running functionality tests
on boards at the manufacturing site, right after production. It assures that boards comply
with a minimum set of quality rules in terms of soldering, mounting and PCB fabrication
process.
This document presents a high-level view of the firmware implemented on the FPGA for the
PTS project for the CONV-TTL-RS485 board. More details can be found by consulting
the PTS gateware, which can be obtained by cloning the git repository for the PTS project~\cite{pts-repo}.
%------------------------------------------------------------------------------
% SUBSEC: Additional docs
%------------------------------------------------------------------------------
\subsection{Additional documentation}
\begin{itemize}
\item CONV-TTL-RS485 User Guide \cite{ug}
\item CONV-TTL-RS485 HDL Guide \cite{hdlg}
\item CONV-TTL-RS485 PTS User Guide \cite{pts-userguide}
\item CONV-TTL-RS485 PTS Hardware Guide \cite{pts-hwguide}
\end{itemize}
%======================================================================================
% SEC: PTS system
%======================================================================================
\section{PTS system}
\label{sec:pts-sys}
The PTS system (Figure~\ref{fig:pts-sys}) is contained within a rack containing an ELMA
crate, the laptop with the PTS software installed on it and all other accessories necessary
for running tests. More information about the PTS system can be found in the PTS user
guide~\cite{pts-userguide}.
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/pts-sys}}
\caption{PTS System}
\label{fig:pts-sys}
\end{figure}
The ELMA crate within the PTS contains a system monitor (SysMon) board that monitors
voltage levels, temperatures and controls fan speeds for the crate fans. The SysMon
can be accessed via Telnet to send commands to the VME boards inside the crate.
Using such commands, the CONV-TTL-RS485 board can be accessed through the serial
(I$^2$C) interface on the VME P1 connector. The PTS software on the PTS laptop connects
to the crate through Telnet and sends \textit{readreg} and \textit{writereg}
commands to the crate; the commands are translated by the SysMon to I$^2$C transfers
to the CONV-TTL-RS485. More information about this can be found in \cite{ug} and
\cite{sysmon-i2c}.
%======================================================================================
% SEC: Gateware Overview
%======================================================================================
\section{Gateware overview}
\label{sec:overview}
A block diagram of the PTS gateware is shown in Figure~\ref{fig:hdl-bd}. The PTS software running
on a computer writes and reads registers implemented in the PTS gateware running on the CONV-TTL-RS485
on-board FPGA. As described in the following sections, writing and reading to specific registers
in the gateware result in the running of the steps necessary to test a CONV-TTL-RS485 device under test.
For a complete reference of the registers accessible in the PTS gateware, see the complete memory map
for the gateware in Appendix~\ref{app:memmap}.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/hdl-bd}}
\caption{\label{fig:hdl-bd} Gateware block diagram}
\end{figure}
%======================================================================================
% SEC: Test logic
%======================================================================================
\section{Test logic}
\label{sec:test-logic}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 01
%--------------------------------------------------------------------------------------
\subsection{Test 01 -- DAC and clocks test}
The logic for this test is shown in Figure~\ref{fig:dac-test} and can be summarized as follows:
\begin{itemize}
\item the PTS software controls (via OpenCores SPI master modules~\cite{spi}) the two DACs on the
CONV-TTL-RS485
\item the DACs control the tuning inputs of the on-board oscillators, which are input to
the FPGA
\item two counters are driven by these clocks; the values of these counters (Appendix~\ref{app:clk-info})
can be read by the PTS software
\item the change in frequency of the oscillators can be observed on the rate of change
of the two counters
\item this rate of change is monitored by the PTS software
\end{itemize}
\begin{figure}[h]
\centerline{\includegraphics[width=0.9\textwidth]{fig/dac-test}}
\caption{\label{fig:dac-test} DAC and clocks test logic}
\end{figure}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 02
%--------------------------------------------------------------------------------------
\subsection{Test 02 -- Front panel LEDs test}
The PTS software sets the CHLEDT and STLEDT bits in the PTS control and status register
(CSR -- see Appendix~\ref{app:pts-regs-csr}), which starts a sequence counter inside the
gateware. Each pulse or status LED is turned on based on the value of this counter.
%--------------------------------------------------------------------------------------
% SUBSEC: Test 03
%--------------------------------------------------------------------------------------
\subsection{Test 03 -- TTL pulse and switches test}
The logic for this test is shown in Figure~\ref{fig:ttl-test} and can be summarized as follows:
\begin{itemize}
\item the PTS software sets the TTLPT bit in the PTS control and status register (CSR -- see Appendix~\ref{app:pts-regs-csr})
\item this enables a general-purpose pulse generator component on TTL CH1 to generate
1~$\mu$s pulses with a period of 500~ms
\item the pulses are replicated through the channel daisy-chain~\cite{pts-userguide} from
CH1 to INV-TTL CH D
\item CH2 through INV-TTL CH D (CH10 in VHDL) have pulse generator components~\cite{conv-common-gw-ohwr}
which generate 1~$\mu$s pulses when there is a pulse on the input
\item each channel has one input and output pulse counter; each counter gets incremented when
there is a rising edge on the input or output
\item the current values of these counters can be read by the PTS software from the pulse counter
registers (see Appendix~\ref{app:pulse-cnt})
\end{itemize}
For the switch test:
\begin{itemize}
\item the user sets the switches as indicated in the CONV-TTL-RS485 PTS User Guide~\cite{pts-userguide}
\item the PTS software reads the CSR.SWITCH field (see Appendix~\ref{app:pts-regs-csr}) to
confirm proper switch setting
\end{itemize}
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/ttl-test}}
\caption{\label{fig:ttl-test} TTL pulse test logic}
\end{figure}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 04
%--------------------------------------------------------------------------------------
\pagebreak
\subsection{Test 04 -- RS-485 pulse and RTM detection lines test}
The RS-485 pulse test logic is the same for each of the six channels. It is shown in Figure~\ref{fig:rs485-test}
for one channel and can be summarized as follows:
\begin{itemize}
\item the PTS software checks that the RTM detection lines are as expected on the CONV-TTL-RTM-RS485
\item the PTS software sets the tester card bits in the CSR (see Appendix~\ref{app:pts-regs-csr})
to control the tester card
\item the values of these bits are reflected on the INV-TTL outputs on the front panel of
the CONV-TTL-RS485
\item the user connects Lemo 00 cables from the INV-TTL outputs to the RS485 testers
\item the PTS software sets the CSR.REARPT bit (see Appendix~\ref{app:pts-regs-csr})
\item this enables six \textit{pulse\_gen\_gp} components which generate pulses that are fed
back to the input on each channel via the RS485 tester card~\cite{pts-hwguide}; the CSR.TSTCS0 and
CSR.TSTCS1 bits control which output is looped back to the input (see Table~\ref{tbl:loopback})
\item each channel has one input and output pulse counter; each counter gets incremented when
there is a rising edge on the input or output
\item the PTS software clears the CSR.REARPT bit after some time
\item the PTS software reads the pulse counter registers (Section~\ref{app:pulse-cnt}) to check
that the number of pulses sent out of a channel is the same as that received at the input of the
channel
\item for the failsafe~\cite{ug} test, the PTS software reads the state of the rear failsafe bits in the
LSR (LSR.REARFS -- see Appendix~\ref{app:pts-regs-lsr})
\end{itemize}
This sequence is performed once without and once with terminations enabled (terminations are enabled
via the termination enable register -- TER, see Appendix~\ref{app:pts-regs-ter}).
\begin{figure}[hbtp]
\centerline{\includegraphics[width=.8\textwidth]{fig/rs485-test}}
\caption{\label{fig:rs485-test} RS-485 pulse test logic for one channel}
\end{figure}
\begin{table}[h]
\rowcolors{2}{white}{gray!25}
\caption{\label{tbl:loopback} Loopback connections via the RS485 tester on each channel}
\centerline{
\begin{tabular}{c c l}
\hline
\multicolumn{1}{c}{\textbf{TSTCS1}} & \multicolumn{1}{c}{\textbf{TSTCS0}} & \multicolumn{1}{c}{\textbf{Connection}} \\
\hline
0 & 0 & Failsafe -- both P and N lines logic high \\
0 & 1 & Output 3 to input \\
1 & 0 & Output 2 to input \\
1 & 1 & Output 1 to input \\
\hline
\end{tabular}
}
\end{table}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 05
%--------------------------------------------------------------------------------------
\subsection{Test 05 -- Thermometer chip test}
The PTS software interacts with the OpenCores one-wire master core~\cite{onewire}
to access the DS18B20U+ temperature chip for retrieving the unique board ID and the
temperature at the time the test is run.
%--------------------------------------------------------------------------------------
% SUBSEC: Test 06
%--------------------------------------------------------------------------------------
\subsection{Test 06 -- SFP EEPROM test}
An OpenCores I$^2$C master component~\cite{i2c-master} communicates to the SFP connector and retrieves
its internal identifier. The PTS software drives this communication by interacting with the
I$^2$C master and checks the SFP identifier for correct value.
%--------------------------------------------------------------------------------------
% SUBSEC: Test 07
%--------------------------------------------------------------------------------------
\subsection{Test 07 -- SPF link test}
The PTS software communicates with MiniNIC and endpoint components~\cite{wr-cores} to
initialize them and check whether the link goes up through the SFP loopback connector.
%======================================================================================
% SEC: Folder structure
%======================================================================================
\pagebreak
\section{Folder structure}
\label{sec:fold-struct}
The folder structure is shown in Table~\ref{tbl:fold-struct}.
\begin{table}[h]
\rowcolors{2}{white}{gray!25}
\caption{\label{tbl:fold-struct} Folder structure for the PTS gateware}
\centerline{
\begin{tabular}{l p{.7\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Folder}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
ip\_cores/ & IP cores used as sub-modules within the git repository \\
modules/ & PTS-specific modules instantiated in the top-level file \\
syn/ & Contains the ISE project file and synthesis output files \\
top/ & Contains the top-level VHDL file and the UCF definitions file for the project \\
\hline
\end{tabular}
}
\end{table}
%======================================================================================
% SEC: Getting around the code
%======================================================================================
\section{Getting around the code}
\label{sec:get-around}
The most important part of the CONV-TTL-RS485 PTS gateware is concentrated in the top-level file (\textit{pts.vhd}),
where submodules are instantiated and connected as needed by the tests. The code in the top-level file
is organized into code sections as shown in Figure~\ref{fig:hdl-arch}.
\begin{figure}[h]
\centerline{\includegraphics[scale=.7]{fig/hdl-arch}}
\caption{Body of VHDL architecture}
\label{fig:hdl-arch}
\end{figure}
%======================================================================================
% APP: Memory map
%======================================================================================
\pagebreak
\begin{appendices}
\section{Memory map}
\label{app:memmap}
The full memory map of the PTS gateware is shown in Table~\ref{tbl:memmap}. Details about each of
the modules in the table are given in the subsections below.
\begin{table}[h]
\caption{CONV-TTL-RS485 PTS memory map}
\label{tbl:memmap}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.5\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Peripheral}} & \multicolumn{2}{c}{\textbf{Address range}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
PTS registers & 0x000 & 0x00f & PTS definition and control and status registers \\
OneWire master & 0x010 & 0x01f & OpenCores OneWire master core~\cite{onewire} \\
125-MHz DAC & 0x020 & 0x07f & OpenCores SPI master core~\cite{spi} for the 125-MHz DAC\\
20-MHz DAC & 0x080 & 0x0ff & OpenCores SPI master core~\cite{spi} for the 20-MHz DAC\\
125-MHz counter & 0x100 & 0x11f & Clock counters for the 125-MHz clock \\
20-MHz counter & 0x120 & 0x13f & Clock counters for the 20-MHz clock \\
I$^2$C master & 0x140 & 0x15f & OpenCores I$^2$C master core~\cite{i2c-master} for the SFP EEPROM \\
Endpoint & 0x200 & 0x3ff & Endpoint~\cite{wr-cores} for communicating via the SFP \\
MiniNIC & 0x400 & 0x7ff & MiniNIC~\cite{wr-cores} for communicating via the SFP \\
DPRAM & 0x800 & 0xbff & Dual-port RAM for the endpoint and MiniNIC components \\
Pulse counters & 0xc00 & 0xc7f & Pulse counters for pulse repetition tests \\
\hline
\end{tabular}
}
\end{table}
\include{pts_regs}
\include{clk_info}
\include{pulse_cnt_wb}
\end{appendices}
%======================================================================================
% Bibliography
%======================================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{hdlg-pts-conv-ttl-rs485}
\addcontentsline{toc}{section}{References}
\end{document}
\subsection{PTS control and status registers}
\label{subsec:wbgen:pts}
\label{app:pts-regs}
Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
Base address: 0x000
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
......@@ -15,15 +15,23 @@ Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
\endhead
\hline
\endfoot
0x0 & g\_board\_id & BIDR & Board ID Register\\
0x4 & 0xf{}f{}f{}f{}f{}f{}f{}f & CSR & Control and Status Register\\
0x8 & 0xf{}f{}f{}f{}f{}f{}f{}f & LSR & Line Status Register\\
0xc & 0xf{}f{}f{}f{}f{}f{}f{}f & TER & Termination Enable Register\\
0x0 & 0x54343835 & BIDR & Board ID Register\\
0x4 & (1) & CSR & Control and Status Register\\
0x8 & (2) & LSR & Line Status Register\\
0xc & 0x00000000 & TER & Termination Enable Register\\
\end{longtable}
}
\noindent Note (1): The reset value of the status bits in the CSR cannot be specified, since it is based on the
the state of the on-board switches and whether an RTM is plugged in or not. Control bits in the CSR default to 0.
\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
is plugged into the channel or not.
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
\label{app:pts-regs-bidr}
\vspace{11pt}
\noindent
......@@ -54,7 +62,7 @@ Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: g\_board\_id
Reset value: 0x54343835
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
......@@ -62,6 +70,7 @@ Reset value: g\_board\_id
\end{itemize}
\vspace{11pt}
\subsubsection{CSR -- Control and Status Register}
\label{app:pts-regs-csr}
\vspace{11pt}
\noindent
......@@ -178,6 +187,7 @@ RTM
\\
1 - line active \\ 0 - line inactive
\end{small}
\pagebreak
\item \begin{small}
{\bf
I2C\_ERR
......@@ -198,6 +208,7 @@ I2C\_WDTO
\end{itemize}
\vspace{11pt}
\subsubsection{LSR -- Line Status Register}
\label{app:pts-regs-lsr}
\vspace{11pt}
\noindent
......@@ -205,11 +216,11 @@ I2C\_WDTO
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[3:2]}\\
\multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]} & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONTFS[5:0]}\\
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
......@@ -246,20 +257,6 @@ Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\
\end{small}
\item \begin{small}
{\bf
FRONTFS
} [\emph{read-only}]: Front panel input failsafe state
\\
High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTINVFS
} [\emph{read-only}]: Front panel inverter input failsafe state
\\
High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REARFS
} [\emph{read-only}]: Rear panel input failsafe state
\\
......@@ -271,6 +268,7 @@ High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- cha
\end{itemize}
\vspace{11pt}
\subsubsection{TER -- Termination Enable Register}
\label{app:pts-regs-ter}
\vspace{11pt}
\noindent
......
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