hdl: Changed rear pulse gen startup delay to 3 us

05661a03 · Theodor-Adrian Stana · f134aea0 · 05661a03
Commit 05661a03 authored Dec 01, 2014 by Theodor-Adrian Stana
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pts.vhd hdl/top/pts.vhd +1 -1

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--- a/hdl/top/pts.vhd
+++ b/hdl/top/pts.vhd
@@ -1672,7 +1672,7 @@ gen_rear_test_logic : for i in 0 to 5 generate
      en_i     => rear_pulse_en,

      -- Delay, pulse width and frequency inputs, in number of clk_i cycles
-      delay_i  => x"0000003c",
+      delay_i  => x"00000050",
      pwidth_i => x"00000014",
      freq_i   => x"00989680",