pts_regs

PTS control and status registers

1. Memory map summary

H/W Address	Type	Name	VHDL/Verilog prefix	C prefix
0x0	REG	BIDR	pts_bidr	BIDR
0x1	REG	CSR	pts_csr	CSR
0x2	REG	LSR	pts_lsr	LSR
0x3	REG	TER	pts_ter	TER
0x4	REG	HWVERS	pts_hwvr	HWVR

2. HDL symbol

→	rst_n_i	BIDR:
→	clk_sys_i	pts_bidr_i[31:0]	⇐
⇒	wb_adr_i[2:0]
⇒	wb_dat_i[31:0]	CSR:
⇐	wb_dat_o[31:0]	pts_csr_chledt_o	→
→	wb_cyc_i	pts_csr_stledt_o	→
⇒	wb_sel_i[3:0]	pts_csr_rledt_o	→
→	wb_stb_i	pts_csr_ttlpt_o	→
→	wb_we_i	pts_csr_rearpt_o	→
←	wb_ack_o	pts_csr_tstcvcc_o	→
←	wb_stall_o	pts_csr_tstcmuxen_o	→
		pts_csr_tstcs0_o	→
		pts_csr_tstcs1_o	→
		pts_csr_rst_unlock_o	→
		pts_csr_rst_unlock_i	←
		pts_csr_rst_unlock_load_o	→
		pts_csr_rst_o	→
		pts_csr_rst_i	←
		pts_csr_rst_load_o	→
		pts_csr_switch_i[7:0]	⇐
		pts_csr_rtm_i[5:0]	⇐
		pts_csr_i2c_err_o	→
		pts_csr_i2c_err_i	←
		pts_csr_i2c_err_load_o	→
		pts_csr_i2c_wdto_o	→
		pts_csr_i2c_wdto_i	←
		pts_csr_i2c_wdto_load_o	→

		LSR:
		pts_lsr_front_i[5:0]	⇐
		pts_lsr_frontinv_i[3:0]	⇐
		pts_lsr_rear_i[5:0]	⇐
		pts_lsr_frontfs_i[5:0]	⇐
		pts_lsr_frontinvfs_i[3:0]	⇐
		pts_lsr_rearfs_i[5:0]	⇐

		TER:
		pts_ter_iterm_o[5:0]	⇒
		pts_ter_oterm_o[5:0]	⇒

		HWVERS:
		pts_hwvr_hwvers_i[5:0]	⇐

3. Register description

3.1. BIDR

HW prefix:	pts_bidr
HW address:	0x0
C prefix:	BIDR
C offset:	0x0

Board ID Register

31	30	29	28	27	26	25	24
BIDR[31:24]

23	22	21	20	19	18	17	16
BIDR[23:16]

15	14	13	12	11	10	9	8
BIDR[15:8]

7	6	5	4	3	2	1	0
BIDR[7:0]

BIDR [read-only]: ID register bits

3.2. CSR

HW prefix:	pts_csr
HW address:	0x1
C prefix:	CSR
C offset:	0x4

Control and Status Register

31	30	29	28	27	26	25	24
I2C_WDTO	I2C_ERR	RTM[5:0]

23	22	21	20	19	18	17	16
SWITCH[7:0]

15	14	13	12	11	10	9	8
RST	RST_UNLOCK	-	-	-	-	-	TSTCS1

7	6	5	4	3	2	1	0
TSTCS0	TSTCMUXEN	TSTCVCC	REARPT	TTLPT	RLEDT	STLEDT	CHLEDT

CHLEDT [read/write]: Channel pulse LED enable
1 -- Enable channel LED sequencing
0 -- No effect
STLEDT [read/write]: Status LED enable
1 -- Enable front panel bicolor LED sequencing
0 -- No effect
RLEDT [read/write]: Rear pulse LED line
1 -- Set LED lines high
0 -- No effect
TTLPT [read/write]: TTL test enable
1 -- Enable pulse generation from CH1
0 -- No effect
REARPT [read/write]: Rear pulse enable
1 -- Enable rear panel pulse generation
0 -- No effect
TSTCVCC [read/write]: RS485 tester card VCC
1 -- Power on the RS485 tester
0 -- No effect
TSTCMUXEN [read/write]: RS485 tester card MUX enable
1 -- Enable multiplexers on RS485 tester
0 -- No effect
TSTCS0 [read/write]: RS485 tester card MUX S0 line
RS485 tester S0 line on multiplexers
TSTCS1 [read/write]: RS485 tester card MUX S1 line
RS485 tester S1 line on multiplexers
RST_UNLOCK [read/write]: Reset unlock bit
1 -- Reset bit unlocked
0 -- Reset bit locked
RST [read/write]: Reset bit -- active only if RST_UNLOCK is 1
1 -- initiate logic reset
0 -- no reset
SWITCH [read-only]: switches
1 - switch is ON
0 - switch is OFF
RTM [read-only]: RTM detection lines
1 - line active
0 - line inactive
I2C_ERR [read/write]: I2C communication error
1 -- attempted to address non-existing address
0 -- idle
This bit can be cleared by writing a '1' to it
I2C_WDTO [read/write]: I2C communication watchdog timeout error
1 -- timeout occured
0 -- no timeout
This bit can be cleared by writing a '1' to it

3.3. LSR

HW prefix:	pts_lsr
HW address:	0x2
C prefix:	LSR
C offset:	0x8

Line Status Register

31	30	29	28	27	26	25	24
REARFS[5:0]						FRONTINVFS[3:2]

23	22	21	20	19	18	17	16
FRONTINVFS[1:0]		FRONTFS[5:0]

15	14	13	12	11	10	9	8
REAR[5:0]						FRONTINV[3:2]

7	6	5	4	3	2	1	0
FRONTINV[1:0]		FRONT[5:0]

FRONT [read-only]: Front panel channel input state
Line state at board input
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
FRONTINV [read-only]: Front panel INV-TTL input state
Line state at board input
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
REAR [read-only]: Rear panel input state
Line state at board input
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
FRONTFS [read-only]: Front panel input failsafe state
High if line is in failsafe mode (e.g., no cable plugged in)
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
FRONTINVFS [read-only]: Front panel inverter input failsafe state
High if line is in failsafe mode (e.g., no cable plugged in)
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
REARFS [read-only]: Rear panel input failsafe state
High if line is in failsafe mode (e.g., no cable plugged in)
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.

3.4. TER

HW prefix:	pts_ter
HW address:	0x3
C prefix:	TER
C offset:	0xc

Termination Enable Register

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	OTERM[5:2]

7	6	5	4	3	2	1	0
OTERM[1:0]		ITERM[5:0]

ITERM [read/write]: Input termination enable
Set high to enable the channel input termination
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
OTERM [read/write]: Output termination enable
Set high to enable the channel output terminations
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.

3.5. HWVERS

HW prefix:	pts_hwvr
HW address:	0x4
C prefix:	HWVR
C offset:	0x10

Hardware version register

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	HWVERS[5:0]

HWVERS [read-only]: PCB version number
6 bits representing HW/PCB version number
4 MSB represent HW version number
2 LSB represent number of execution
Eg: value 010010 represents PCB version 4.2

pts_regs

PTS control and status registers

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