pax_global_header 0000666 0000000 0000000 00000000064 12432353720 0014513 g ustar 00root root 0000000 0000000 52 comment=3fdf92d96718a8ae0b0a2a328a2d29dda11e103f
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/ 0000775 0000000 0000000 00000000000 12432353720 0022074 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/.gitmodules 0000664 0000000 0000000 00000000366 12432353720 0024256 0 ustar 00root root 0000000 0000000 [submodule "hdl/ip_cores/conv-common-gw"]
path = hdl/ip_cores/conv-common-gw
url = git@ohwr.org:level-conversion/conv-common-gw.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git@ohwr.org:hdl-core-lib/wr-cores.git
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/README 0000664 0000000 0000000 00000000166 12432353720 0022757 0 ustar 00root root 0000000 0000000 This repository contains gateware and test scripts for functional and production
testing of CONV-TTL-BLO-RS485 cards.
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/ 0000775 0000000 0000000 00000000000 12432353720 0022643 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/ip_cores/ 0000775 0000000 0000000 00000000000 12432353720 0024446 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/ip_cores/conv-common-gw/ 0000775 0000000 0000000 00000000000 12432353720 0027314 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/ip_cores/wr-cores/ 0000775 0000000 0000000 00000000000 12432353720 0026207 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/modules/ 0000775 0000000 0000000 00000000000 12432353720 0024313 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/modules/Manifest.py 0000664 0000000 0000000 00000000222 12432353720 0026427 0 ustar 00root root 0000000 0000000 files = [
"pts_regs.vhd",
"pulse_cnt_wb.vhd",
"incr_counter.vhd",
"clk_info_wb_slave.vhd",
"pulse_gen_gp.vhd"
]
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/modules/clk_info_wb_slave.vhd 0000664 0000000 0000000 00000027001 12432353720 0030464 0 ustar 00root root 0000000 0000000 --_________________________________________________________________________________________________
-- |
-- |SVEC PTS| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- clk_info_wb_slave |
-- |
---------------------------------------------------------------------------------------------------
-- File clk_info_wb_slave.vhd |
-- |
-- Description Wishbone slave that receives and transmits information for a clock counter. |
-- It is Used at test svec_pts_04_05_06 for the evaluation of si570 VCXO and |
-- at svec_pts_08 for the evaluation of the VCXO and PLLREF clocks |
-- Five 32 bits long registers are used: |
-- Register in address x0 (reg 0) can only be read by the VME interface: |
-- reg 0 bit 0 indicates that a clock counter is full |
-- Register in address x1 (reg 1) can only be read by the VME interface: |
-- reg 1 bit 0 indicates a clock error:clock output disabled & clock counter full|
-- Register in address x2 (reg 2) can be written and read by the VME interface: |
-- reg 2 bit 0 enables the output of a clcok (oe_clk) |
-- Register in address x3 (reg 3) can be written and read by the VME interface: |
-- reg 3 bits 32..0 indicate the amount of cycles to be counted by the clock |
-- Register in address x4 (reg 4) can only be read by the VME interface: |
-- reg 4 bits 32..0 indicate the amount of cycles counted so far |
-- Register in address x5 (reg 5) can be written and read by the VME interface: |
-- reg 5 bit 0 resets the counter |
-- Register in address x6 (reg 6) can be written and read by the VME interface: |
-- reg 6 bit 0 enables the counting |
-- |
-- Authors Samuel Iglesias Gonsalvez |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2012 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2012 v1 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--=================================================================================================
-- Entity declaration for clk_info_wb_slave
--=================================================================================================
entity clk_info_wb_slave is
port
-- WISHBONE slave signals
(wb_clk_i : in std_logic;
rst_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_addr_i : in std_logic_vector( 2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_we_i : in std_logic;
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
-- Clock info signals
counter_is_full_i : in std_logic;
counter_now_i : in std_logic_vector (31 downto 0);
counter_top_o : out std_logic_vector (31 downto 0);
counter_rst_o : out std_logic;
counter_en_o : out std_logic;
oe_clk_o : out std_logic);
end clk_info_wb_slave;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture behavioral of clk_info_wb_slave is
signal clk_ok_synch, clk_err_synch : std_logic_vector(1 downto 0);
signal reg2, reg5, reg6 : std_logic_vector(31 downto 0);
signal reg3 : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- initial value
signal clk_err, oe_clk : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- INPUTS SYNCHRONIZATION --
---------------------------------------------------------------------------------------------------
clk_err_clk_ok_synchronizer: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if rst_i = '1' then
clk_ok_synch <= (others => '0');
clk_err_synch <= (others => '0');
else
clk_ok_synch <= clk_ok_synch(0) & (counter_is_full_i);
clk_err_synch <= clk_err_synch(0) & (clk_err);
end if;
end if;
end process;
clk_err <= '1' when counter_is_full_i = '1' and oe_clk = '0';
---------------------------------------------------------------------------------------------------
-- DATA IN/ OUT --
---------------------------------------------------------------------------------------------------
data_out: process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if rst_i = '1' then
wb_data_o <= (others => '0');
reg2 <= (others => '0');
reg3 <= x"FFFFFFFF";
reg5 <= (others => '0');
reg6 <= (others => '0');
else
if (wb_cyc_i = '1') and (wb_stb_i = '1') and (wb_we_i = '0') then -- WISHBONE reads
if (wb_addr_i = "000") then -- reg 0 read only, clk ok
wb_data_o(0) <= clk_ok_synch(1);
elsif (wb_addr_i = "001") then -- reg 1 read only, clk error
wb_data_o(0) <= clk_err_synch(1);
elsif (wb_addr_i = "010") then -- reg 2 read write, oe_clk
wb_data_o <= reg2;
elsif (wb_addr_i = "011") then -- reg 3 read write, counter top
wb_data_o <= reg3;
elsif (wb_addr_i = "100") then -- reg 4 read only, counter current value
wb_data_o <= counter_now_i;
elsif (wb_addr_i = "101") then -- reg 5 read write, counter reset
wb_data_o <= reg5;
elsif (wb_addr_i = "110") then -- reg 6 read write, counter enable
wb_data_o <= reg6;
elsif (wb_addr_i = "111") then -- dummy
wb_data_o <= x"C000FFEE";
else
wb_data_o <= x"00000000";
end if;
elsif (wb_cyc_i = '1') and (wb_stb_i = '1') and (wb_we_i = '1') then-- WISHBONE writes
if (wb_addr_i = "010") then -- reg 1 read write, oe_clk
reg2 <= wb_data_i;
elsif (wb_addr_i = "011") then -- reg 3 read write, counter top
reg3 <= wb_data_i;
elsif (wb_addr_i = "101") then -- reg 5 read write, counter reset
reg5 <= wb_data_i;
elsif (wb_addr_i = "110") then -- reg 6 read write, counter enable
reg6 <= wb_data_i;
end if;
end if;
end if;
end if;
end process;
oe_clk <= reg2(0);
oe_clk_o <= reg2(0);
counter_top_o <= reg3;
counter_rst_o <= reg5(0);
counter_en_o <= reg6(0);
---------------------------------------------------------------------------------------------------
-- ACK generation --
---------------------------------------------------------------------------------------------------
ack_generator: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if rst_i = '1' then
wb_ack_o <= '0';
else
wb_ack_o <= wb_stb_i and wb_cyc_i;
end if;
end if;
end process;
end behavioral;
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/modules/incr_counter.vhd 0000664 0000000 0000000 00000016766 12432353720 0027530 0 ustar 00root root 0000000 0000000 --_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- incr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File incr_counter.vhd |
-- |
-- Description Stop counter. Configurable counter_top_i and width. |
-- Current count value and done signal available. |
-- Done signal asserted simultaneous to value = counter_top_i. |
-- Needs a rst_i to restart. |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Entity declaration for incr_counter
--=================================================================================================
entity incr_counter is
generic
(width : integer := 32); -- default size
port
-- INPUTS
-- Signals from the clk_rst_manager
(clk_i : in std_logic;
rst_i : in std_logic;
-- Signals from any unit
counter_top_i : in std_logic_vector(width-1 downto 0); -- max value to be counted; when reached
-- counter stays at it, until a reset
counter_incr_en_i : in std_logic; -- enables counting
-- OUTPUTS
-- Signals to any unit
counter_o : out std_logic_vector(width-1 downto 0);
counter_is_full_o : out std_logic); -- counter reahed counter_top_i value
end incr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of incr_counter is
constant zeroes : unsigned(width-1 downto 0) := (others=>'0');
signal counter : unsigned(width-1 downto 0) := (others=>'0'); -- init to avoid sim warnings
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
incr_counting: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
counter_is_full_o <= '0';
counter <= zeroes;
elsif counter = unsigned (counter_top_i) then
counter_is_full_o <= '1';
counter <= unsigned (counter_top_i);
elsif counter_incr_en_i ='1' then
if counter = unsigned(counter_top_i) - "1" then
counter_is_full_o <= '1';
counter <= counter + "1";
else
counter_is_full_o <= '0';
counter <= counter + "1";
end if;
end if;
end if;
end process;
counter_o <= std_logic_vector(counter);
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/modules/pts_regs.vhd 0000664 0000000 0000000 00000033534 12432353720 0026654 0 ustar 00root root 0000000 0000000 ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for PTS control and status registers
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Wed Nov 12 10:26:43 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pts_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
pts_bidr_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'Front pulse LED enable' in reg: 'CSR'
pts_csr_fledt_o : out std_logic;
-- Port for BIT field: 'Rear pulse LED enable' in reg: 'CSR'
pts_csr_rledt_o : out std_logic;
-- Port for BIT field: 'Status LED enable' in reg: 'CSR'
pts_csr_stledt_o : out std_logic;
-- Port for BIT field: 'TTL test enable' in reg: 'CSR'
pts_csr_ttlpt_o : out std_logic;
-- Port for BIT field: 'RS485 pulse enable' in reg: 'CSR'
pts_csr_rs485pt_o : out std_logic;
-- Port for BIT field: 'RS485 tester card VCC' in reg: 'CSR'
pts_csr_tstcvcc_o : out std_logic;
-- Port for BIT field: 'RS485 tester card MUX enable' in reg: 'CSR'
pts_csr_tstcmuxen_o : out std_logic;
-- Port for BIT field: 'RS485 tester card MUX S0 line' in reg: 'CSR'
pts_csr_tstcs0_o : out std_logic;
-- Port for BIT field: 'RS485 tester card MUX S1 line' in reg: 'CSR'
pts_csr_tstcs1_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
pts_csr_rst_unlock_o : out std_logic;
pts_csr_rst_unlock_i : in std_logic;
pts_csr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CSR'
pts_csr_rst_o : out std_logic;
pts_csr_rst_i : in std_logic;
pts_csr_rst_load_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'CSR'
pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication error' in reg: 'CSR'
pts_csr_i2c_err_o : out std_logic;
pts_csr_i2c_err_i : in std_logic;
pts_csr_i2c_err_load_o : out std_logic;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'CSR'
pts_csr_i2c_wdto_o : out std_logic;
pts_csr_i2c_wdto_i : in std_logic;
pts_csr_i2c_wdto_load_o : out std_logic;
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
pts_lsr_front_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
pts_lsr_frontinv_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
pts_lsr_rear_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
pts_lsr_frontfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
pts_lsr_frontinvfs_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
pts_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Input termination enable' in reg: 'TER'
pts_ter_iterm_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Output termination enable' in reg: 'TER'
pts_ter_oterm_o : out std_logic_vector(5 downto 0)
);
end pts_regs;
architecture syn of pts_regs is
signal pts_csr_fledt_int : std_logic ;
signal pts_csr_rledt_int : std_logic ;
signal pts_csr_stledt_int : std_logic ;
signal pts_csr_ttlpt_int : std_logic ;
signal pts_csr_rs485pt_int : std_logic ;
signal pts_csr_tstcvcc_int : std_logic ;
signal pts_csr_tstcmuxen_int : std_logic ;
signal pts_csr_tstcs0_int : std_logic ;
signal pts_csr_tstcs1_int : std_logic ;
signal pts_ter_iterm_int : std_logic_vector(5 downto 0);
signal pts_ter_oterm_int : std_logic_vector(5 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pts_csr_fledt_int <= '0';
pts_csr_rledt_int <= '0';
pts_csr_stledt_int <= '0';
pts_csr_ttlpt_int <= '0';
pts_csr_rs485pt_int <= '0';
pts_csr_tstcvcc_int <= '0';
pts_csr_tstcmuxen_int <= '0';
pts_csr_tstcs0_int <= '0';
pts_csr_tstcs1_int <= '0';
pts_csr_rst_unlock_load_o <= '0';
pts_csr_rst_load_o <= '0';
pts_csr_i2c_err_load_o <= '0';
pts_csr_i2c_wdto_load_o <= '0';
pts_ter_iterm_int <= "000000";
pts_ter_oterm_int <= "000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
pts_csr_rst_unlock_load_o <= '0';
pts_csr_rst_load_o <= '0';
pts_csr_i2c_err_load_o <= '0';
pts_csr_i2c_wdto_load_o <= '0';
ack_in_progress <= '0';
else
pts_csr_rst_unlock_load_o <= '0';
pts_csr_rst_load_o <= '0';
pts_csr_i2c_err_load_o <= '0';
pts_csr_i2c_wdto_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pts_bidr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
pts_csr_fledt_int <= wrdata_reg(0);
pts_csr_rledt_int <= wrdata_reg(1);
pts_csr_stledt_int <= wrdata_reg(2);
pts_csr_ttlpt_int <= wrdata_reg(3);
pts_csr_rs485pt_int <= wrdata_reg(4);
pts_csr_tstcvcc_int <= wrdata_reg(5);
pts_csr_tstcmuxen_int <= wrdata_reg(6);
pts_csr_tstcs0_int <= wrdata_reg(7);
pts_csr_tstcs1_int <= wrdata_reg(8);
pts_csr_rst_unlock_load_o <= '1';
pts_csr_rst_load_o <= '1';
pts_csr_i2c_err_load_o <= '1';
pts_csr_i2c_wdto_load_o <= '1';
end if;
rddata_reg(0) <= pts_csr_fledt_int;
rddata_reg(1) <= pts_csr_rledt_int;
rddata_reg(2) <= pts_csr_stledt_int;
rddata_reg(3) <= pts_csr_ttlpt_int;
rddata_reg(4) <= pts_csr_rs485pt_int;
rddata_reg(5) <= pts_csr_tstcvcc_int;
rddata_reg(6) <= pts_csr_tstcmuxen_int;
rddata_reg(7) <= pts_csr_tstcs0_int;
rddata_reg(8) <= pts_csr_tstcs1_int;
rddata_reg(14) <= pts_csr_rst_unlock_i;
rddata_reg(15) <= pts_csr_rst_i;
rddata_reg(23 downto 16) <= pts_csr_switch_i;
rddata_reg(29 downto 24) <= pts_csr_rtm_i;
rddata_reg(30) <= pts_csr_i2c_err_i;
rddata_reg(31) <= pts_csr_i2c_wdto_i;
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
end if;
rddata_reg(5 downto 0) <= pts_lsr_front_i;
rddata_reg(9 downto 6) <= pts_lsr_frontinv_i;
rddata_reg(15 downto 10) <= pts_lsr_rear_i;
rddata_reg(21 downto 16) <= pts_lsr_frontfs_i;
rddata_reg(25 downto 22) <= pts_lsr_frontinvfs_i;
rddata_reg(31 downto 26) <= pts_lsr_rearfs_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
pts_ter_iterm_int <= wrdata_reg(5 downto 0);
pts_ter_oterm_int <= wrdata_reg(11 downto 6);
end if;
rddata_reg(5 downto 0) <= pts_ter_iterm_int;
rddata_reg(11 downto 6) <= pts_ter_oterm_int;
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- ID register bits
-- Front pulse LED enable
pts_csr_fledt_o <= pts_csr_fledt_int;
-- Rear pulse LED enable
pts_csr_rledt_o <= pts_csr_rledt_int;
-- Status LED enable
pts_csr_stledt_o <= pts_csr_stledt_int;
-- TTL test enable
pts_csr_ttlpt_o <= pts_csr_ttlpt_int;
-- RS485 pulse enable
pts_csr_rs485pt_o <= pts_csr_rs485pt_int;
-- RS485 tester card VCC
pts_csr_tstcvcc_o <= pts_csr_tstcvcc_int;
-- RS485 tester card MUX enable
pts_csr_tstcmuxen_o <= pts_csr_tstcmuxen_int;
-- RS485 tester card MUX S0 line
pts_csr_tstcs0_o <= pts_csr_tstcs0_int;
-- RS485 tester card MUX S1 line
pts_csr_tstcs1_o <= pts_csr_tstcs1_int;
-- Reset unlock bit
pts_csr_rst_unlock_o <= wrdata_reg(14);
-- Reset bit
pts_csr_rst_o <= wrdata_reg(15);
-- switches
-- RTM
-- I2C communication error
pts_csr_i2c_err_o <= wrdata_reg(30);
-- I2C communication watchdog timeout error
pts_csr_i2c_wdto_o <= wrdata_reg(31);
-- Front panel channel input state
-- Front panel INV-TTL input state
-- Rear panel input state
-- Front panel input failsafe state
-- Front panel inverter input failsafe state
-- Rear panel input failsafe state
-- Input termination enable
pts_ter_iterm_o <= pts_ter_iterm_int;
-- Output termination enable
pts_ter_oterm_o <= pts_ter_oterm_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/modules/pts_regs.wb 0000664 0000000 0000000 00000021227 12432353720 0026477 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- CONV-TTL-RS485 PTS registers wbgen2 description file
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description:
-- This file contains the register description for the converter board
-- registers and is to be used as input to the wbgen2 tool for generating
-- an appropriate VHDL file.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 11-11-2014 Theodor Stana Added GPL header
--==============================================================================
-- TODO: -
--==============================================================================
peripheral {
name = "PTS control and status registers";
description = "Registers of the PTS firmware";
hdl_entity = "pts_regs";
prefix = "pts";
-- Board ID register
reg {
name = "BIDR";
description = "Board ID Register";
prefix = "bidr";
reset_value = "g_board_id";
field {
name = "ID register bits";
reset_value = "g_board_id";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
-- Control & Status Register
reg {
name = "CSR";
description = "Control and Status Register";
prefix = "csr";
field {
name = "Front pulse LED enable";
prefix = "fledt";
description = "1 -- Enable front panel LED sequencing \ 0 -- No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rear pulse LED enable";
prefix = "rledt";
description = "1 -- Enable rear panel LED sequencing \ 0 -- No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Status LED enable";
prefix = "stledt";
description = "1 -- Enable front panel bicolor LED sequencing \ 0 -- No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "TTL test enable";
prefix = "ttlpt";
description = "1 -- Enable pulse generation from CH1 \ 0 -- No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "RS485 pulse enable";
prefix = "rs485pt";
description = "1 -- Enable RS485 pulse generation \ 0 -- No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "RS485 tester card VCC";
prefix = "tstcvcc";
description = "1 -- Power on the RS485 tester \ 0 -- No effect";
type = BIT;
access_bud = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "RS485 tester card MUX enable";
prefix = "tstcmuxen";
description = "1 -- Enable multiplexers on RS485 tester \ 0 -- No effect";
type = BIT;
access_bud = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "RS485 tester card MUX S0 line";
prefix = "tstcs0";
description = "RS485 tester S0 line on multiplexers";
type = BIT;
access_bud = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "RS485 tester card MUX S1 line";
prefix = "tstcs1";
description = "RS485 tester S1 line on multiplexers";
type = BIT;
access_bud = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reset unlock bit";
description = "1 -- Reset bit unlocked \ 0 -- Reset bit locked";
prefix = "rst_unlock";
type = BIT;
align = 14;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Reset bit";
description = "1 -- initiate logic reset \ 0 -- no reset";
prefix = "rst";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "switches";
prefix = "switch";
type = SLV;
align = 16;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RTM";
prefix = "rtm";
type = SLV;
align = 24;
size = 6;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "I2C communication error";
description = "1 -- attempted to address non-existing address \
0 -- idle \
This bit can be cleared by writing a '1' to it";
prefix = "i2c_err";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "I2C communication watchdog timeout error";
description = "1 -- timeout occured \
0 -- no timeout \
This bit can be cleared by writing a '1' to it";
prefix = "i2c_wdto";
type = BIT;
size = 1;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "LSR";
description = "Line Status Register";
prefix = "lsr";
field {
name = "Front panel channel input state";
description = "Line state at board input\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "front";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Front panel INV-TTL input state";
description = "Line state at board input\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "frontinv";
type = SLV;
size = 4;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Rear panel input state";
description = "Line state at board input\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "rear";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Front panel input failsafe state";
description = "High if line is in failsafe mode (e.g., no cable plugged in)\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "frontfs";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Front panel inverter input failsafe state";
description = "High if line is in failsafe mode (e.g., no cable plugged in)\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "frontinvfs";
type = SLV;
size = 4;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Rear panel input failsafe state";
description = "High if line is in failsafe mode (e.g., no cable plugged in)\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "rearfs";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TER";
description = "Termination Enable Register";
prefix = "ter";
field {
name = "Input termination enable";
description = "Set high to enable the channel input termination\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "iterm";
type = SLV;
size = 6;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Output termination enable";
description = "Set high to enable the channel output terminations\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "oterm";
type = SLV;
size = 6;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
};
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/modules/pulse_cnt_wb.vhd 0000664 0000000 0000000 00000070067 12432353720 0027514 0 ustar 00root root 0000000 0000000 ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse counter registers
---------------------------------------------------------------------------------------
-- File : pulse_cnt_wb.vhd
-- Author : auto-generated by wbgen2 from pulse_cnt_wb.wb
-- Created : Mon Nov 3 09:56:02 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_cnt_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH1OCR'
pulse_cnt_ttlch1o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch1o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch1o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH1ICR'
pulse_cnt_ttlch1i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch1i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch1i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH2OCR'
pulse_cnt_ttlch2o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch2o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch2o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH2ICR'
pulse_cnt_ttlch2i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch2i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch2i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH3OCR'
pulse_cnt_ttlch3o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch3o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch3o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH3ICR'
pulse_cnt_ttlch3i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch3i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch3i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH4OCR'
pulse_cnt_ttlch4o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch4o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch4o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH4ICR'
pulse_cnt_ttlch4i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch4i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch4i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH5OCR'
pulse_cnt_ttlch5o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch5o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch5o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH5ICR'
pulse_cnt_ttlch5i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch5i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch5i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH6OCR'
pulse_cnt_ttlch6o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch6o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch6o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH6ICR'
pulse_cnt_ttlch6i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch6i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch6i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHAOCR'
pulse_cnt_invttlchao_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchao_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchao_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHAICR'
pulse_cnt_invttlchai_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchai_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchai_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHBOCR'
pulse_cnt_invttlchbo_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchbo_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchbo_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHBICR'
pulse_cnt_invttlchbi_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchbi_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchbi_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHCOCR'
pulse_cnt_invttlchco_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchco_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchco_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHCICR'
pulse_cnt_invttlchci_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchci_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchci_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHDOCR'
pulse_cnt_invttlchdo_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchdo_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchdo_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHDICR'
pulse_cnt_invttlchdi_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchdi_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchdi_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH1OCR'
pulse_cnt_rearch1o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch1o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch1o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH1ICR'
pulse_cnt_rearch1i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch1i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch1i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH2OCR'
pulse_cnt_rearch2o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch2o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch2o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH2ICR'
pulse_cnt_rearch2i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch2i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch2i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH3OCR'
pulse_cnt_rearch3o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch3o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch3o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH3ICR'
pulse_cnt_rearch3i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch3i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch3i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH4OCR'
pulse_cnt_rearch4o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch4o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch4o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH4ICR'
pulse_cnt_rearch4i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch4i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch4i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH5OCR'
pulse_cnt_rearch5o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch5o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch5o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH5ICR'
pulse_cnt_rearch5i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch5i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch5i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6OCR'
pulse_cnt_rearch6o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch6o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch6o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6ICR'
pulse_cnt_rearch6i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch6i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch6i_load_o : out std_logic
);
end pulse_cnt_wb;
architecture syn of pulse_cnt_wb is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pulse_cnt_ttlch1o_load_o <= '0';
pulse_cnt_ttlch1i_load_o <= '0';
pulse_cnt_ttlch2o_load_o <= '0';
pulse_cnt_ttlch2i_load_o <= '0';
pulse_cnt_ttlch3o_load_o <= '0';
pulse_cnt_ttlch3i_load_o <= '0';
pulse_cnt_ttlch4o_load_o <= '0';
pulse_cnt_ttlch4i_load_o <= '0';
pulse_cnt_ttlch5o_load_o <= '0';
pulse_cnt_ttlch5i_load_o <= '0';
pulse_cnt_ttlch6o_load_o <= '0';
pulse_cnt_ttlch6i_load_o <= '0';
pulse_cnt_invttlchao_load_o <= '0';
pulse_cnt_invttlchai_load_o <= '0';
pulse_cnt_invttlchbo_load_o <= '0';
pulse_cnt_invttlchbi_load_o <= '0';
pulse_cnt_invttlchco_load_o <= '0';
pulse_cnt_invttlchci_load_o <= '0';
pulse_cnt_invttlchdo_load_o <= '0';
pulse_cnt_invttlchdi_load_o <= '0';
pulse_cnt_rearch1o_load_o <= '0';
pulse_cnt_rearch1i_load_o <= '0';
pulse_cnt_rearch2o_load_o <= '0';
pulse_cnt_rearch2i_load_o <= '0';
pulse_cnt_rearch3o_load_o <= '0';
pulse_cnt_rearch3i_load_o <= '0';
pulse_cnt_rearch4o_load_o <= '0';
pulse_cnt_rearch4i_load_o <= '0';
pulse_cnt_rearch5o_load_o <= '0';
pulse_cnt_rearch5i_load_o <= '0';
pulse_cnt_rearch6o_load_o <= '0';
pulse_cnt_rearch6i_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
pulse_cnt_ttlch1o_load_o <= '0';
pulse_cnt_ttlch1i_load_o <= '0';
pulse_cnt_ttlch2o_load_o <= '0';
pulse_cnt_ttlch2i_load_o <= '0';
pulse_cnt_ttlch3o_load_o <= '0';
pulse_cnt_ttlch3i_load_o <= '0';
pulse_cnt_ttlch4o_load_o <= '0';
pulse_cnt_ttlch4i_load_o <= '0';
pulse_cnt_ttlch5o_load_o <= '0';
pulse_cnt_ttlch5i_load_o <= '0';
pulse_cnt_ttlch6o_load_o <= '0';
pulse_cnt_ttlch6i_load_o <= '0';
pulse_cnt_invttlchao_load_o <= '0';
pulse_cnt_invttlchai_load_o <= '0';
pulse_cnt_invttlchbo_load_o <= '0';
pulse_cnt_invttlchbi_load_o <= '0';
pulse_cnt_invttlchco_load_o <= '0';
pulse_cnt_invttlchci_load_o <= '0';
pulse_cnt_invttlchdo_load_o <= '0';
pulse_cnt_invttlchdi_load_o <= '0';
pulse_cnt_rearch1o_load_o <= '0';
pulse_cnt_rearch1i_load_o <= '0';
pulse_cnt_rearch2o_load_o <= '0';
pulse_cnt_rearch2i_load_o <= '0';
pulse_cnt_rearch3o_load_o <= '0';
pulse_cnt_rearch3i_load_o <= '0';
pulse_cnt_rearch4o_load_o <= '0';
pulse_cnt_rearch4i_load_o <= '0';
pulse_cnt_rearch5o_load_o <= '0';
pulse_cnt_rearch5i_load_o <= '0';
pulse_cnt_rearch6o_load_o <= '0';
pulse_cnt_rearch6i_load_o <= '0';
ack_in_progress <= '0';
else
pulse_cnt_ttlch1o_load_o <= '0';
pulse_cnt_ttlch1i_load_o <= '0';
pulse_cnt_ttlch2o_load_o <= '0';
pulse_cnt_ttlch2i_load_o <= '0';
pulse_cnt_ttlch3o_load_o <= '0';
pulse_cnt_ttlch3i_load_o <= '0';
pulse_cnt_ttlch4o_load_o <= '0';
pulse_cnt_ttlch4i_load_o <= '0';
pulse_cnt_ttlch5o_load_o <= '0';
pulse_cnt_ttlch5i_load_o <= '0';
pulse_cnt_ttlch6o_load_o <= '0';
pulse_cnt_ttlch6i_load_o <= '0';
pulse_cnt_invttlchao_load_o <= '0';
pulse_cnt_invttlchai_load_o <= '0';
pulse_cnt_invttlchbo_load_o <= '0';
pulse_cnt_invttlchbi_load_o <= '0';
pulse_cnt_invttlchco_load_o <= '0';
pulse_cnt_invttlchci_load_o <= '0';
pulse_cnt_invttlchdo_load_o <= '0';
pulse_cnt_invttlchdi_load_o <= '0';
pulse_cnt_rearch1o_load_o <= '0';
pulse_cnt_rearch1i_load_o <= '0';
pulse_cnt_rearch2o_load_o <= '0';
pulse_cnt_rearch2i_load_o <= '0';
pulse_cnt_rearch3o_load_o <= '0';
pulse_cnt_rearch3i_load_o <= '0';
pulse_cnt_rearch4o_load_o <= '0';
pulse_cnt_rearch4i_load_o <= '0';
pulse_cnt_rearch5o_load_o <= '0';
pulse_cnt_rearch5i_load_o <= '0';
pulse_cnt_rearch6o_load_o <= '0';
pulse_cnt_rearch6i_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch1o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch1o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch1i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch1i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch2o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch2o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch2i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch2i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch3o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch3o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch3i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch3i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch4o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch4o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch4i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch4i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch5o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch5o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch5i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch5i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch6o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch6o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
pulse_cnt_ttlch6i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ttlch6i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
pulse_cnt_invttlchao_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_invttlchao_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
pulse_cnt_invttlchai_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_invttlchai_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
pulse_cnt_invttlchbo_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_invttlchbo_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
pulse_cnt_invttlchbi_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_invttlchbi_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
pulse_cnt_invttlchco_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_invttlchco_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
pulse_cnt_invttlchci_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_invttlchci_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
pulse_cnt_invttlchdo_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_invttlchdo_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
if (wb_we_i = '1') then
pulse_cnt_invttlchdi_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_invttlchdi_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100" =>
if (wb_we_i = '1') then
pulse_cnt_rearch1o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch1o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10101" =>
if (wb_we_i = '1') then
pulse_cnt_rearch1i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch1i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
pulse_cnt_rearch2o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch2o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
if (wb_we_i = '1') then
pulse_cnt_rearch2i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch2i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11000" =>
if (wb_we_i = '1') then
pulse_cnt_rearch3o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch3o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11001" =>
if (wb_we_i = '1') then
pulse_cnt_rearch3i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch3i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11010" =>
if (wb_we_i = '1') then
pulse_cnt_rearch4o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch4o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11011" =>
if (wb_we_i = '1') then
pulse_cnt_rearch4i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch4i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11100" =>
if (wb_we_i = '1') then
pulse_cnt_rearch5o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch5o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11101" =>
if (wb_we_i = '1') then
pulse_cnt_rearch5i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch5i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11110" =>
if (wb_we_i = '1') then
pulse_cnt_rearch6o_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch6o_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11111" =>
if (wb_we_i = '1') then
pulse_cnt_rearch6i_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= pulse_cnt_rearch6i_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Pulse counter value
pulse_cnt_ttlch1o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch1i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch2o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch2i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch3o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch3i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch4o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch4i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch5o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch5i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch6o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_ttlch6i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_invttlchao_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_invttlchai_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_invttlchbo_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_invttlchbi_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_invttlchco_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_invttlchci_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_invttlchdo_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_invttlchdi_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch1o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch1i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch2o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch2i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch3o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch3i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch4o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch4i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch5o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch5i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch6o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
pulse_cnt_rearch6i_o <= wrdata_reg(31 downto 0);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/modules/pulse_cnt_wb.wb 0000664 0000000 0000000 00000022540 12432353720 0027334 0 ustar 00root root 0000000 0000000 peripheral {
name = "Pulse counter registers";
description = "Registers containing the values for input and output generated pulses";
hdl_entity = "pulse_cnt_wb";
prefix = "pulse_cnt";
reg {
name = "TTLCH1OCR";
prefix = "ttlch1o";
description = "TTL CH1 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH1ICR";
prefix = "ttlch1i";
description = "TTL CH1 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH2OCR";
prefix = "ttlch2o";
description = "TTL CH2 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH2ICR";
prefix = "ttlch2i";
description = "TTL CH2 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH3OCR";
prefix = "ttlch3o";
description = "TTL CH3 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH3ICR";
prefix = "ttlch3i";
description = "TTL CH3 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH4OCR";
prefix = "ttlch4o";
description = "TTL CH4 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH4ICR";
prefix = "ttlch4i";
description = "TTL CH4 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH5OCR";
prefix = "ttlch5o";
description = "TTL CH5 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH5ICR";
prefix = "ttlch5i";
description = "TTL CH5 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH6OCR";
prefix = "ttlch6o";
description = "TTL CH6 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TTLCH6ICR";
prefix = "ttlch6i";
description = "TTL CH6 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "INVTTLCHAOCR";
prefix = "invttlchao";
description = "INV-TTL CHA output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "INVTTLCHAICR";
prefix = "invttlchai";
description = "INV-TTL CHA input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "INVTTLCHBOCR";
prefix = "invttlchbo";
description = "INV-TTL CHB output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "INVTTLCHBICR";
prefix = "invttlchbi";
description = "INV-TTL CHB input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "INVTTLCHCOCR";
prefix = "invttlchco";
description = "INV-TTL CHC output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "INVTTLCHCICR";
prefix = "invttlchci";
description = "INV-TTL CHC input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "INVTTLCHDOCR";
prefix = "invttlchdo";
description = "INV-TTL CHD output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "INVTTLCHDICR";
prefix = "invttlchdi";
description = "INV-TTL CHD input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH1OCR";
prefix = "rearch1o";
description = "Rear CH1 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH1ICR";
prefix = "rearch1i";
description = "Rear CH1 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH2OCR";
prefix = "rearch2o";
description = "Rear CH2 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH2ICR";
prefix = "rearch2i";
description = "Rear CH2 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH3OCR";
prefix = "rearch3o";
description = "Rear CH3 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH3ICR";
prefix = "rearch3i";
description = "Rear CH3 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH4OCR";
prefix = "rearch4o";
description = "Rear CH4 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH4ICR";
prefix = "rearch4i";
description = "Rear CH4 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH5OCR";
prefix = "rearch5o";
description = "Rear CH5 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH5ICR";
prefix = "rearch5i";
description = "Rear CH5 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH6OCR";
prefix = "rearch6o";
description = "Rear CH6 output counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "REARCH6ICR";
prefix = "rearch6i";
description = "Rear CH6 input counter register";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/modules/pulse_gen_gp.vhd 0000664 0000000 0000000 00000013601 12432353720 0027466 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- General-purpose pulse generator
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 2.0
--
-- description:
--
-- This module generates pulses with configurable frequency, width and delay.
--
-- In order to generate pulses, the module must be enabled via the en_i port.
-- Once en_i is high, pulses are generated at the frequency specified via
-- freq_i, with the width specified via pwidth_i.
--
-- An optional delay can be added before the start of the pulse, via the delay_i
-- port.
--
-- Note that this delay can be set only before the module is enabled.
--
-- freq_i, pwidth_i and delay_i are given in clk_i cycles.
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
-- 2013 08-15 Theodor Stana t.stana@cern.ch v2.0, delay, pwidth, freq
-- now controllable via
-- inputs (regs, etc.)
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen_gp is
port
(
-- Input clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active high enable signal
en_i : in std_logic;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
-- Output pulse signal
pulse_o : out std_logic
);
end entity pulse_gen_gp;
architecture behav of pulse_gen_gp is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal delay_int : unsigned(31 downto 0);
signal pwidth_int : unsigned(31 downto 0);
signal freq_int : unsigned(31 downto 0);
signal pulse_cnt : unsigned(31 downto 0);
signal delay_cnt : unsigned(31 downto 0);
signal delay_en : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Convert std_logic_vector inputs to unsigned
--============================================================================
delay_int <= unsigned(delay_i);
pwidth_int <= unsigned(pwidth_i);
freq_int <= unsigned(freq_i);
--============================================================================
-- Delay logic
--============================================================================
p_delay: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then
delay_en <= '1';
delay_cnt <= (others => '0');
else
if (delay_int = (delay_int'range => '0')) then
delay_en <= '0';
elsif (delay_en = '1') then
delay_cnt <= delay_cnt + 1;
if (delay_cnt = delay_int) then
delay_en <= '0';
delay_cnt <= (others => '0');
end if;
end if;
end if;
end if;
end process p_delay;
--============================================================================
-- Pulse generation logic
--============================================================================
p_gen_pulse: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then
pulse_cnt <= (others => '0');
pulse_o <= '0';
elsif (delay_en = '0') then
pulse_cnt <= pulse_cnt + 1;
pulse_o <= '0';
if (pulse_cnt < pwidth_int) then
pulse_o <= '1';
elsif (pulse_cnt = freq_int-1) then
pulse_cnt <= (others => '0');
end if;
end if;
end if;
end process p_gen_pulse;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/syn/ 0000775 0000000 0000000 00000000000 12432353720 0023454 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/syn/Makefile 0000664 0000000 0000000 00000002047 12432353720 0025117 0 ustar 00root root 0000000 0000000 ########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := pts.xise
ISE_CRAP := *.b pts_summary.html *.tcl pts.bld pts.cmd_log *.drc pts.lso *.ncd pts.ngc pts.ngd pts.ngr pts.pad pts.par pts.pcf pts.prj pts.ptwx pts.stx pts.syr pts.twr pts.twx pts.gise pts.unroutes pts.ut pts.xpi pts.xst pts_bitgen.xwbt pts_envsettings.html pts_guide.ncd pts_map.map pts_map.mrp pts_map.ncd pts_map.ngm pts_map.xrpt pts_ngdbuild.xrpt pts_pad.csv pts_pad.txt pts_par.xrpt pts_summary.xml pts_usage.xml pts_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/syn/Manifest.py 0000664 0000000 0000000 00000000322 12432353720 0025571 0 ustar 00root root 0000000 0000000 target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "pts"
syn_project = "pts.xise"
modules = {
"local" : [
"../top"
]
}
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/syn/pts.xise 0000664 0000000 0000000 00000241631 12432353720 0025163 0 ustar 00root root 0000000 0000000
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/top/ 0000775 0000000 0000000 00000000000 12432353720 0023445 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/top/Manifest.py 0000664 0000000 0000000 00000000247 12432353720 0025570 0 ustar 00root root 0000000 0000000 files = [
"pts.ucf",
"pts.vhd"
]
modules = {
"local" : [
"../modules",
"../ip_cores/conv-common-gw",
"../ip_cores/wr-cores"
],
}
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/top/pts.ucf 0000664 0000000 0000000 00000037321 12432353720 0024760 0 ustar 00root root 0000000 0000000 #==============================================================================
# CERN (BE-CO-HT)
# UCF defintions file for CONV-TTL-RS485 PTS gateware
#==============================================================================
#
# author: Theodor Stana (t.stana@cern.ch)
#
# date of creation: 2014-10-30
#
# version: 1.0
#
# description:
# This file contains the pin definitions for the CONV-TTL-RS485 FPGA.
#
# references:
# [1] CONV-TTL-RS485 schematics from latest version of project at:
# https://edms.cern.ch/nav/EDA-02541
#
#==============================================================================
# GNU LESSER GENERAL PUBLIC LICENSE
#==============================================================================
# This source file is free software; you can redistribute it and/or modify it
# under the terms of the GNU Lesser General Public License as published by the
# Free Software Foundation; either version 2.1 of the License, or (at your
# option) any later version. This source is distributed in the hope that it
# will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
# See the GNU Lesser General Public License for more details. You should have
# received a copy of the GNU Lesser General Public License along with this
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#==============================================================================
# last changes:
# 2014-07-24 Theodor Stana t.stana@cern.ch File created
#==============================================================================
# TODO: -
#==============================================================================
#=============================================================================
# CLOCKS
#=============================================================================
NET "clk_20_i" LOC = E16;
NET "clk_20_i" TNM_NET = "clk_20";
TIMESPEC TSCLK20 = PERIOD "clk_20" 20 MHz HIGH 50 %;
NET "clk_125_p_i" LOC = H12;
NET "clk_125_n_i" LOC = G11;
NET "clk_125_p_i" TNM_NET = "clk_125";
TIMESPEC TSCLK125 = PERIOD "clk_125" 125 MHz HIGH 50 %;
#==============================================================================
# FRONT PANEL
#==============================================================================
#-----------------------------------------------------------------------------
# TTL I/O
#-----------------------------------------------------------------------------
NET "ttl_n_i[0]" LOC = T3;
NET "ttl_n_i[0]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[1]" LOC = U4;
NET "ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[2]" LOC = W3;
NET "ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[3]" LOC = W4;
NET "ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[4]" LOC = V3;
NET "ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[5]" LOC = U3;
NET "ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "ttl_o[0]" LOC = D1;
NET "ttl_o[0]" IOSTANDARD = LVCMOS33;
NET "ttl_o[1]" LOC = E1;
NET "ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "ttl_o[2]" LOC = F2;
NET "ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "ttl_o[3]" LOC = F1;
NET "ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "ttl_o[4]" LOC = G1;
NET "ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "ttl_o[5]" LOC = H2;
NET "ttl_o[5]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# INV-TTL I/O
#-----------------------------------------------------------------------------
NET "inv_n_i[0]" LOC = Y1;
NET "inv_n_i[0]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[1]" LOC = Y2;
NET "inv_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[2]" LOC = AA1;
NET "inv_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[3]" LOC = AA2;
NET "inv_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_o[0]" LOC = H1;
NET "inv_o[0]" IOSTANDARD = LVCMOS33;
NET "inv_o[1]" LOC = J1;
NET "inv_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_o[2]" LOC = K2;
NET "inv_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_o[3]" LOC = K1;
NET "inv_o[3]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Channel LEDs
#------------------------------------------------------------------------------
NET "led_front_o[0]" LOC = H3;
NET "led_front_o[0]" IOSTANDARD = LVCMOS33;
NET "led_front_o[1]" LOC = J4;
NET "led_front_o[1]" IOSTANDARD = LVCMOS33;
NET "led_front_o[2]" LOC = J3;
NET "led_front_o[2]" IOSTANDARD = LVCMOS33;
NET "led_front_o[3]" LOC = K3;
NET "led_front_o[3]" IOSTANDARD = LVCMOS33;
NET "led_front_o[4]" LOC = L4;
NET "led_front_o[4]" IOSTANDARD = LVCMOS33;
NET "led_front_o[5]" LOC = L3;
NET "led_front_o[5]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[0]" LOC = AA4;
NET "led_inv_o[0]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[1]" LOC = AB4;
NET "led_inv_o[1]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[2]" LOC = AB5;
NET "led_inv_o[2]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[3]" LOC = Y5;
NET "led_inv_o[3]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Status LEDs
#------------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M5;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = M4;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = K6;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = K5;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_gp_2_4_o" LOC = F9;
NET "led_gp_2_4_o" IOSTANDARD = LVCMOS33;
NET "led_gp_1_3_o" LOC = F10;
NET "led_gp_1_3_o" IOSTANDARD = LVCMOS33;
NET "led_oterm_wr_o" LOC = E5;
NET "led_oterm_wr_o" IOSTANDARD = LVCMOS33;
NET "led_iterm_syserror_o" LOC = F7;
NET "led_iterm_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_gf_syspw_o" LOC = F8;
NET "led_gf_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_ttl_i2c_o" LOC = E6;
NET "led_ttl_i2c_o" IOSTANDARD = LVCMOS33;
#=============================================================================
# Rear panel signals
#=============================================================================
#-----------------------------------------------------------------------------
# RS-485 I/O (fs = failsafe)
#-----------------------------------------------------------------------------
NET "rs485_n_i[0]" LOC = Y12;
NET "rs485_n_i[0]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[1]" LOC = AB12;
NET "rs485_n_i[1]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[2]" LOC = AB11;
NET "rs485_n_i[2]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[3]" LOC = AB10;
NET "rs485_n_i[3]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[4]" LOC = AB9;
NET "rs485_n_i[4]" IOSTANDARD = LVCMOS33;
NET "rs485_n_i[5]" LOC = AA8;
NET "rs485_n_i[5]" IOSTANDARD = LVCMOS33;
NET "rs485_o[0]" LOC = W18;
NET "rs485_o[0]" IOSTANDARD = LVCMOS33;
NET "rs485_o[1]" LOC = Y18;
NET "rs485_o[1]" IOSTANDARD = LVCMOS33;
NET "rs485_o[2]" LOC = W17;
NET "rs485_o[2]" IOSTANDARD = LVCMOS33;
NET "rs485_o[3]" LOC = Y17;
NET "rs485_o[3]" IOSTANDARD = LVCMOS33;
NET "rs485_o[4]" LOC = Y16;
NET "rs485_o[4]" IOSTANDARD = LVCMOS33;
NET "rs485_o[5]" LOC = Y15;
NET "rs485_o[5]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[0]" LOC = AA12;
NET "rs485_fs_n_i[0]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[1]" LOC = Y11;
NET "rs485_fs_n_i[1]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[2]" LOC = Y10;
NET "rs485_fs_n_i[2]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[3]" LOC = AA10;
NET "rs485_fs_n_i[3]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[4]" LOC = AB8;
NET "rs485_fs_n_i[4]" IOSTANDARD = LVCMOS33;
NET "rs485_fs_n_i[5]" LOC = AB7;
NET "rs485_fs_n_i[5]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Input and output termination enable lines
#------------------------------------------------------------------------------
NET "iterm_en_o[0]" LOC = W14;
NET "iterm_en_o[0]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[1]" LOC = W13;
NET "iterm_en_o[1]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[2]" LOC = W12;
NET "iterm_en_o[2]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[3]" LOC = W11;
NET "iterm_en_o[3]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[4]" LOC = W10;
NET "iterm_en_o[4]" IOSTANDARD = LVCMOS33;
NET "iterm_en_o[5]" LOC = W9;
NET "iterm_en_o[5]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[0]" LOC = T22;
NET "oterm_en_o[0]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[1]" LOC = T21;
NET "oterm_en_o[1]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[2]" LOC = T20;
NET "oterm_en_o[2]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[3]" LOC = U20;
NET "oterm_en_o[3]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[4]" LOC = V20;
NET "oterm_en_o[4]" IOSTANDARD = LVCMOS33;
NET "oterm_en_o[5]" LOC = W20;
NET "oterm_en_o[5]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Channel LEDs
#------------------------------------------------------------------------------
NET "led_rear_n_o[0]" LOC = AB17;
NET "led_rear_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[1]" LOC = AB19;
NET "led_rear_n_o[1]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[2]" LOC = AA16;
NET "led_rear_n_o[2]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[3]" LOC = AA18;
NET "led_rear_n_o[3]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[4]" LOC = AB16;
NET "led_rear_n_o[4]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[5]" LOC = AB18;
NET "led_rear_n_o[5]" IOSTANDARD = LVCMOS33;
#=============================================================================
# Channel enable signals
#=============================================================================
NET "global_oen_o" LOC = N3;
NET "global_oen_o" IOSTANDARD = LVCMOS33;
NET "ttl_oen_o" LOC = M3;
NET "ttl_oen_o" IOSTANDARD = LVCMOS33;
NET "inv_oen_o" LOC = N4;
NET "inv_oen_o" IOSTANDARD = LVCMOS33;
NET "rs485_oen_o" LOC = AB6;
NET "rs485_oen_o" IOSTANDARD = LVCMOS33;
#=============================================================================
# VME CONNECTOR SIGNALS
#=============================================================================
#-----------------------------------------------------------------------------
# I2C lines
#-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_en_o" LOC = H18;
NET "scl_en_o" IOSTANDARD = LVCMOS33;
NET "scl_en_o" DRIVE = 4;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
NET "sda_en_o" LOC = J19;
NET "sda_en_o" IOSTANDARD = LVCMOS33;
NET "sda_en_o" SLEW = FAST;
NET "sda_en_o" DRIVE = 4;
#-----------------------------------------------------------------------------
# System reset line
#-----------------------------------------------------------------------------
NET "vme_sysreset_n_i" LOC = L20;
NET "vme_sysreset_n_i" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# Geographical addressing lines
#-----------------------------------------------------------------------------
NET "vme_gap_i" LOC = H19;
NET "vme_gap_i" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[0]" LOC = H20;
NET "vme_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[1]" LOC = J20;
NET "vme_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[2]" LOC = K19;
NET "vme_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[3]" LOC = K20;
NET "vme_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[4]" LOC = L19;
NET "vme_ga_i[4]" IOSTANDARD = LVCMOS33;
#=============================================================================
# WHITE RABBIT
#=============================================================================
#-----------------------------------------------------------------------------
# DAC control
#-----------------------------------------------------------------------------
NET "dac_20_din_o" LOC = AB13;
NET "dac_20_din_o" IOSTANDARD = LVCMOS33;
NET "dac_20_sclk_o" LOC = Y13;
NET "dac_20_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac_20_sync_n_o" LOC = AB14;
NET "dac_20_sync_n_o" IOSTANDARD = LVCMOS33;
NET "dac_125_din_o" LOC = Y14;
NET "dac_125_din_o" IOSTANDARD = LVCMOS33;
NET "dac_125_sclk_o" LOC = AA14;
NET "dac_125_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac_125_sync_n_o" LOC = AB15;
NET "dac_125_sync_n_o" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# SFP connection
#-----------------------------------------------------------------------------
NET "sfp_los_i" LOC = G3;
NET "sfp_los_i" IOSTANDARD = LVCMOS33;
NET "sfp_present_i" LOC = G4;
NET "sfp_present_i" IOSTANDARD = LVCMOS33;
NET "sfp_rate_select_o" LOC = C4;
NET "sfp_rate_select_o" IOSTANDARD = LVCMOS33;
NET "sfp_scl_b" LOC = F3;
NET "sfp_scl_b" IOSTANDARD = LVCMOS33;
NET "sfp_sda_b" LOC = E3;
NET "sfp_sda_b" IOSTANDARD = LVCMOS33;
NET "sfp_tx_disable_o" LOC = E4;
NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i" LOC = D2;
NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# FPGA MGT lines
#-----------------------------------------------------------------------------
NET "mgt_clk0_p_i" LOC = A10;
NET "mgt_clk0_n_i" LOC = B10;
NET "mgt_sfp_rx0_p_i" LOC = D7;
NET "mgt_sfp_rx0_n_i" LOC = C7;
NET "mgt_sfp_tx0_p_o" LOC = B6;
NET "mgt_sfp_tx0_n_o" LOC = A6;
#=============================================================================
# OTHER SIGNALS
#=============================================================================
#-----------------------------------------------------------------------------
# One-wire thermometer data signal
#-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# General-purpose switches
#-----------------------------------------------------------------------------
NET "sw_gp_n_i[0]" LOC = F22;
NET "sw_gp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[1]" LOC = G22;
NET "sw_gp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[2]" LOC = H21;
NET "sw_gp_n_i[2]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[3]" LOC = H22;
NET "sw_gp_n_i[3]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[4]" LOC = J22;
NET "sw_gp_n_i[4]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[5]" LOC = K21;
NET "sw_gp_n_i[5]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[6]" LOC = K22;
NET "sw_gp_n_i[6]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[7]" LOC = L22;
NET "sw_gp_n_i[7]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# Multicast switches
#-----------------------------------------------------------------------------
NET "sw_multicast_n_i[0]" LOC = D21;
NET "sw_multicast_n_i[0]" IOSTANDARD = LVCMOS33;
NET "sw_multicast_n_i[1]" LOC = C22;
NET "sw_multicast_n_i[1]" IOSTANDARD = LVCMOS33;
NET "sw_multicast_n_i[2]" LOC = B22;
NET "sw_multicast_n_i[2]" IOSTANDARD = LVCMOS33;
NET "sw_multicast_n_i[3]" LOC = B21;
NET "sw_multicast_n_i[3]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# RTM detection lines
#-----------------------------------------------------------------------------
NET "rtmm_i[0]" LOC = V21;
NET "rtmm_i[0]" IOSTANDARD = LVCMOS33;
NET "rtmm_i[1]" LOC = V22;
NET "rtmm_i[1]" IOSTANDARD = LVCMOS33;
NET "rtmm_i[2]" LOC = U22;
NET "rtmm_i[2]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[0]" LOC = W22;
NET "rtmp_i[0]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[1]" LOC = Y22;
NET "rtmp_i[1]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[2]" LOC = Y21;
NET "rtmp_i[2]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# Flash memory
#-----------------------------------------------------------------------------
NET "flash_sclk_o" LOC = Y20;
NET "flash_sclk_o" IOSTANDARD = LVCMOS33;
NET "flash_cs_n_o" LOC = AA3;
NET "flash_cs_n_o" IOSTANDARD = LVCMOS33;
NET "flash_miso_i" LOC = AA20;
NET "flash_miso_i" IOSTANDARD = LVCMOS33;
NET "flash_mosi_o" LOC = AB20;
NET "flash_mosi_o" IOSTANDARD = LVCMOS33;
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/hdl/top/pts.vhd 0000664 0000000 0000000 00000251207 12432353720 0024765 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- CONV-TTL-RS485 PTS top-level file
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-10-30
--
-- version: 1.0
--
-- Top-level file of the HDL for the CONV-TTL-RS485 front-module PTS. All the
-- modules used within the PTS are instantiated and connected here. The logic
-- implemented here will work together with the PTS (Python) software.
--
-- dependencies:
-- - converter board common gateware [1]
-- - general-cores repository [2]
-- - White Rabbit core collection [3]
--
-- references:
-- [1] Converter board common gateware on OHWR,
-- http://www.ohwr.org/projects/conv-common-gw/repository
-- [2] Platform-independent core collection on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [3] White Rabbit Core Collection on OHWR,
-- http://www.ohwr.org/projects/wr-cores/repository
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-10-30 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.conv_common_gw_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
use work.wrcore_pkg.all;
use work.endpoint_pkg.all;
entity pts is
port
(
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- VME interface
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- Channel enable
global_oen_o : out std_logic;
ttl_oen_o : out std_logic;
inv_oen_o : out std_logic;
rs485_oen_o : out std_logic;
-- Front panel channels
ttl_n_i : in std_logic_vector(5 downto 0);
ttl_o : out std_logic_vector(5 downto 0);
inv_n_i : in std_logic_vector(3 downto 0);
inv_o : out std_logic_vector(3 downto 0);
-- Rear panel channels
rs485_n_i : in std_logic_vector(5 downto 0);
rs485_fs_n_i : in std_logic_vector(5 downto 0);
rs485_o : out std_logic_vector(5 downto 0);
-- Rear input and output termination lines
iterm_en_o : out std_logic_vector(5 downto 0);
oterm_en_o : out std_logic_vector(5 downto 0);
-- Channel leds
led_front_o : out std_logic_vector(5 downto 0);
led_inv_o : out std_logic_vector(3 downto 0);
led_rear_n_o : out std_logic_vector(5 downto 0);
-- SPI interface to on-board flash chip
flash_cs_n_o : out std_logic;
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
-- PLL DACs
-- 20 MHz VCXO control
dac_20_din_o : out std_logic;
dac_20_sclk_o : out std_logic;
dac_20_sync_n_o : out std_logic;
-- 125 MHz clock generator control
dac_125_din_o : out std_logic;
dac_125_sclk_o : out std_logic;
dac_125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
sfp_present_i : in std_logic;
sfp_rate_select_o : out std_logic;
sfp_scl_b : inout std_logic;
sfp_sda_b : inout std_logic;
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- FPGA MGT lines
mgt_clk0_p_i : in std_logic;
mgt_clk0_n_i : in std_logic;
mgt_sfp_rx0_p_i : in std_logic;
mgt_sfp_rx0_n_i : in std_logic;
mgt_sfp_tx0_p_o : out std_logic;
mgt_sfp_tx0_n_o : out std_logic;
-- Thermometer data port
thermometer_b : inout std_logic;
-- Switches
sw_gp_n_i : in std_logic_vector(7 downto 0);
sw_multicast_n_i : in std_logic_vector(3 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
-- Front panel bicolor LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_gp_2_4_o : out std_logic;
led_gp_1_3_o : out std_logic;
led_oterm_wr_o : out std_logic;
led_iterm_syserror_o : out std_logic;
led_gf_syspw_o : out std_logic;
led_ttl_i2c_o : out std_logic
);
end entity pts;
architecture arch of pts is
--============================================================================
-- Type declarations
--============================================================================
-- Pulse counter register and load value types
type t_pcr is array (15 downto 0) of unsigned(31 downto 0);
type t_pcr_ldval is array (15 downto 0) of std_logic_vector(31 downto 0);
type t_pulse_led_cnt is array(9 downto 0) of unsigned(18 downto 0);
--============================================================================
-- Constant declarations
--============================================================================
-- Board ID constant
constant c_board_id : std_logic_vector(31 downto 0) := x"54343835";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 11;
-- slave order definitions
constant c_slv_pts_regs : natural := 0;
constant c_slv_onewire_mst : natural := 1;
constant c_slv_dac_spi_125 : natural := 2;
constant c_slv_dac_spi_20 : natural := 3;
constant c_slv_clk_info_125 : natural := 4;
constant c_slv_clk_info_20 : natural := 5;
constant c_slv_sfp_i2c : natural := 6;
constant c_slv_minic : natural := 7;
constant c_slv_endpoint : natural := 8;
constant c_slv_dpram : natural := 9;
constant c_slv_pulse_cntrs : natural := 10;
-- base address definitions
constant c_addr_pts_regs : t_wishbone_address := x"00000000";
constant c_addr_onewire_mst : t_wishbone_address := x"00000010";
constant c_addr_dac_spi_125 : t_wishbone_address := x"00000020";
constant c_addr_dac_spi_20 : t_wishbone_address := x"00000080";
constant c_addr_clk_info_125 : t_wishbone_address := x"00000100";
constant c_addr_clk_info_20 : t_wishbone_address := x"00000120";
constant c_addr_sfp_i2c : t_wishbone_address := x"00000140";
constant c_addr_endpoint : t_wishbone_address := x"00000200";
constant c_addr_minic : t_wishbone_address := x"00000400";
constant c_addr_dpram : t_wishbone_address := x"00000800";
constant c_addr_pulse_cntrs : t_wishbone_address := x"00000c00";
-- address mask definitions
constant c_mask_pts_regs : t_wishbone_address := x"00000ff0";
constant c_mask_onewire_mst : t_wishbone_address := x"00000ff0";
constant c_mask_dac_spi_125 : t_wishbone_address := x"00000fe0";
constant c_mask_dac_spi_20 : t_wishbone_address := x"00000fe0";
constant c_mask_clk_info_125 : t_wishbone_address := x"00000f60";
constant c_mask_clk_info_20 : t_wishbone_address := x"00000f60";
constant c_mask_sfp_i2c : t_wishbone_address := x"00000f60";
constant c_mask_endpoint : t_wishbone_address := x"00000e00";
constant c_mask_minic : t_wishbone_address := x"00000c00";
constant c_mask_dpram : t_wishbone_address := x"00000c00";
constant c_mask_pulse_cntrs : t_wishbone_address := x"00000c00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_pts_regs => c_addr_pts_regs,
c_slv_onewire_mst => c_addr_onewire_mst,
c_slv_dac_spi_125 => c_addr_dac_spi_125,
c_slv_clk_info_125 => c_addr_clk_info_125,
c_slv_dac_spi_20 => c_addr_dac_spi_20,
c_slv_clk_info_20 => c_addr_clk_info_20,
c_slv_sfp_i2c => c_addr_sfp_i2c,
c_slv_endpoint => c_addr_endpoint,
c_slv_minic => c_addr_minic,
c_slv_dpram => c_addr_dpram,
c_slv_pulse_cntrs => c_addr_pulse_cntrs
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_pts_regs => c_mask_pts_regs,
c_slv_onewire_mst => c_mask_onewire_mst,
c_slv_dac_spi_125 => c_mask_dac_spi_125,
c_slv_clk_info_125 => c_mask_clk_info_125,
c_slv_dac_spi_20 => c_mask_dac_spi_20,
c_slv_clk_info_20 => c_mask_clk_info_20,
c_slv_sfp_i2c => c_mask_sfp_i2c,
c_slv_endpoint => c_mask_endpoint,
c_slv_minic => c_mask_minic,
c_slv_dpram => c_mask_dpram,
c_slv_pulse_cntrs => c_mask_pulse_cntrs
);
-- MiniNIC log2 of memory size
constant c_minic_memsize_log2 : natural := 10;
--============================================================================
-- Component declarations
--============================================================================
-- Regs to test I2C operation
component pts_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
pts_bidr_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'Front pulse LED enable' in reg: 'CSR'
pts_csr_fledt_o : out std_logic;
-- Port for BIT field: 'Rear pulse LED enable' in reg: 'CSR'
pts_csr_rledt_o : out std_logic;
-- Port for BIT field: 'Status LED enable' in reg: 'CSR'
pts_csr_stledt_o : out std_logic;
-- Port for BIT field: 'TTL test enable' in reg: 'CSR'
pts_csr_ttlpt_o : out std_logic;
-- Port for BIT field: 'RS485 pulse enable' in reg: 'CSR'
pts_csr_rs485pt_o : out std_logic;
-- Port for BIT field: 'RS485 tester card VCC' in reg: 'CSR'
pts_csr_tstcvcc_o : out std_logic;
-- Port for BIT field: 'RS485 tester card MUX enable' in reg: 'CSR'
pts_csr_tstcmuxen_o : out std_logic;
-- Port for BIT field: 'RS485 tester card MUX S0 line' in reg: 'CSR'
pts_csr_tstcs0_o : out std_logic;
-- Port for BIT field: 'RS485 tester card MUX S1 line' in reg: 'CSR'
pts_csr_tstcs1_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
pts_csr_rst_unlock_o : out std_logic;
pts_csr_rst_unlock_i : in std_logic;
pts_csr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CSR'
pts_csr_rst_o : out std_logic;
pts_csr_rst_i : in std_logic;
pts_csr_rst_load_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'CSR'
pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication error' in reg: 'CSR'
pts_csr_i2c_err_o : out std_logic;
pts_csr_i2c_err_i : in std_logic;
pts_csr_i2c_err_load_o : out std_logic;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'CSR'
pts_csr_i2c_wdto_o : out std_logic;
pts_csr_i2c_wdto_i : in std_logic;
pts_csr_i2c_wdto_load_o : out std_logic;
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
pts_lsr_front_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
pts_lsr_frontinv_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
pts_lsr_rear_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
pts_lsr_frontfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
pts_lsr_frontinvfs_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
pts_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Input termination enable' in reg: 'TER'
pts_ter_iterm_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Output termination enable' in reg: 'TER'
pts_ter_oterm_o : out std_logic_vector(5 downto 0)
);
end component pts_regs;
-- General-purpose pulse generator
component pulse_gen_gp is
port
(
-- Input clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active high enable signal
en_i : in std_logic;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
-- Output pulse signal
pulse_o : out std_logic
);
end component pulse_gen_gp;
component pulse_cnt_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH1OCR'
pulse_cnt_ttlch1o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch1o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch1o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH1ICR'
pulse_cnt_ttlch1i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch1i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch1i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH2OCR'
pulse_cnt_ttlch2o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch2o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch2o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH2ICR'
pulse_cnt_ttlch2i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch2i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch2i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH3OCR'
pulse_cnt_ttlch3o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch3o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch3o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH3ICR'
pulse_cnt_ttlch3i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch3i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch3i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH4OCR'
pulse_cnt_ttlch4o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch4o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch4o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH4ICR'
pulse_cnt_ttlch4i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch4i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch4i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH5OCR'
pulse_cnt_ttlch5o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch5o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch5o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH5ICR'
pulse_cnt_ttlch5i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch5i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch5i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH6OCR'
pulse_cnt_ttlch6o_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch6o_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch6o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH6ICR'
pulse_cnt_ttlch6i_o : out std_logic_vector(31 downto 0);
pulse_cnt_ttlch6i_i : in std_logic_vector(31 downto 0);
pulse_cnt_ttlch6i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHAOCR'
pulse_cnt_invttlchao_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchao_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchao_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHAICR'
pulse_cnt_invttlchai_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchai_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchai_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHBOCR'
pulse_cnt_invttlchbo_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchbo_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchbo_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHBICR'
pulse_cnt_invttlchbi_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchbi_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchbi_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHCOCR'
pulse_cnt_invttlchco_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchco_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchco_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHCICR'
pulse_cnt_invttlchci_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchci_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchci_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHDOCR'
pulse_cnt_invttlchdo_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchdo_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchdo_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHDICR'
pulse_cnt_invttlchdi_o : out std_logic_vector(31 downto 0);
pulse_cnt_invttlchdi_i : in std_logic_vector(31 downto 0);
pulse_cnt_invttlchdi_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH1OCR'
pulse_cnt_rearch1o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch1o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch1o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH1ICR'
pulse_cnt_rearch1i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch1i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch1i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH2OCR'
pulse_cnt_rearch2o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch2o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch2o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH2ICR'
pulse_cnt_rearch2i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch2i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch2i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH3OCR'
pulse_cnt_rearch3o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch3o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch3o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH3ICR'
pulse_cnt_rearch3i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch3i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch3i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH4OCR'
pulse_cnt_rearch4o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch4o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch4o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH4ICR'
pulse_cnt_rearch4i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch4i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch4i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH5OCR'
pulse_cnt_rearch5o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch5o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch5o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH5ICR'
pulse_cnt_rearch5i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch5i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch5i_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6OCR'
pulse_cnt_rearch6o_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch6o_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch6o_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6ICR'
pulse_cnt_rearch6i_o : out std_logic_vector(31 downto 0);
pulse_cnt_rearch6i_i : in std_logic_vector(31 downto 0);
pulse_cnt_rearch6i_load_o : out std_logic
);
end component pulse_cnt_wb;
-- Incremental counter component
-- use: DAC, PLL & VCXO test
component incr_counter is
generic
(
width : integer := 32 -- default size
);
port
(
-- INPUTS
-- Signals from the clk_rst_manager
clk_i : in std_logic;
rst_i : in std_logic;
-- Signals from any unit
counter_top_i : in std_logic_vector(width-1 downto 0); -- max value to be counted; when reached
-- counter stays at it, until a reset
counter_incr_en_i : in std_logic; -- enables counting
-- OUTPUTS
-- Signals to any unit
counter_o : out std_logic_vector(width-1 downto 0);
counter_is_full_o : out std_logic
); -- counter reahed counter_top_i value
end component incr_counter;
-- Clock info component
-- use: DAC, PLL & VCXO test
component clk_info_wb_slave is
port
(
-- WISHBONE slave signals
wb_clk_i : in std_logic;
rst_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_addr_i : in std_logic_vector( 2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_we_i : in std_logic;
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
-- Clock info signals
counter_is_full_i : in std_logic;
counter_now_i : in std_logic_vector (31 downto 0);
counter_top_o : out std_logic_vector (31 downto 0);
counter_rst_o : out std_logic;
counter_en_o : out std_logic;
oe_clk_o : out std_logic
);
end component clk_info_wb_slave;
-- GTP component
component wr_gtp_phy_spartan6
generic (
g_simulation : integer;
g_force_disparity : integer;
g_enable_ch0 : integer;
g_enable_ch1 : integer);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic := '0';
ch0_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch0_tx_k_i : in std_logic := '0';
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic := '0';
ch0_loopen_i : in std_logic := '0';
ch1_ref_clk_i : in std_logic := '0';
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock signals
signal clk_125 : std_logic;
-- Reset signals
signal rst_20_n : std_logic;
signal rst_20 : std_logic;
signal rst_125_n : std_logic;
signal rst_ext : std_logic;
-- I2C bridge signals
signal i2c_addr : std_logic_vector(6 downto 0);
signal i2c_tip : std_logic;
signal i2c_err_p : std_logic;
signal i2c_wdto_p : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array(c_nr_masters-1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array(c_nr_masters-1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array(c_nr_slaves-1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves-1 downto 0);
-- LED signals
signal cnt_halfsec : unsigned(23 downto 0);
signal led_seq : unsigned(4 downto 0);
signal pulse_led_en : std_logic;
signal stat_led_en : std_logic;
signal pulse_led_en_d0 : std_logic;
signal stat_led_en_d0 : std_logic;
signal front_led_en_risedge_p : std_logic;
signal stat_led_en_risedge_p : std_logic;
signal front_led_seq : std_logic_vector( 5 downto 0);
signal inv_led : std_logic_vector( 3 downto 0);
signal inv_led_seq : std_logic_vector( 3 downto 0);
signal front_led : std_logic_vector( 9 downto 0);
signal front_led_cnt : t_pulse_led_cnt;
signal bicolor_led_state : std_logic_vector(23 downto 0);
signal rear_led : std_logic_vector( 5 downto 0);
signal rear_led_cnt : t_pulse_led_cnt;
-- Signals to/from PTS regs component
signal rst_unlock_ld : std_logic;
signal rst_unlock_ldval : std_logic;
signal rst_unlock : std_logic;
signal rst_bit_ld : std_logic;
signal rst_bit_ldval : std_logic;
signal rst_bit : std_logic;
signal i2c_wdto_bit : std_logic;
signal i2c_wdto_bit_rst : std_logic;
signal i2c_wdto_bit_rst_ld : std_logic;
signal i2c_err_bit : std_logic;
signal i2c_err_bit_rst : std_logic;
signal i2c_err_bit_rst_ld : std_logic;
signal rtm_lines : std_logic_vector(5 downto 0);
signal switches : std_logic_vector(7 downto 0);
signal line_front : std_logic_vector(5 downto 0);
signal line_inv : std_logic_vector(3 downto 0);
signal line_rear : std_logic_vector(5 downto 0);
signal line_rear_fs : std_logic_vector(5 downto 0);
-- PLL & DAC test signals
signal cnt_125 : std_logic_vector(31 downto 0);
signal cnt_125_top : std_logic_vector(31 downto 0);
signal cnt_125_en : std_logic;
signal cnt_125_rst : std_logic;
signal cnt_125_full : std_logic;
signal cnt_125_a : std_logic_vector(31 downto 0);
signal cnt_125_top_a : std_logic_vector(31 downto 0);
signal cnt_125_en_a : std_logic;
signal cnt_125_rst_a : std_logic;
signal cnt_125_full_a : std_logic;
signal cnt_125_actual_rst : std_logic;
signal dac_125_sync_n : std_logic_vector(7 downto 0);
signal cnt_20 : std_logic_vector(31 downto 0);
signal cnt_20_top : std_logic_vector(31 downto 0);
signal cnt_20_en : std_logic;
signal cnt_20_rst : std_logic;
signal cnt_20_full : std_logic;
signal cnt_20_actual_rst : std_logic;
signal dac_20_sync_n : std_logic_vector(7 downto 0);
-- SFP EEPROM signals
signal i2c_scl_fr_sfp : std_logic;
signal i2c_scl_to_sfp : std_logic;
signal i2c_sfp_scl_en : std_logic;
signal i2c_sda_fr_sfp : std_logic;
signal i2c_sda_to_sfp : std_logic;
signal i2c_sfp_sda_en : std_logic;
-- SFP signals
signal clk_gtp : std_logic;
signal minic_mem_data_out : std_logic_vector(31 downto 0);
signal minic_mem_addr_out : std_logic_vector(c_minic_memsize_log2-1 downto 0);
signal minic_mem_data_in : std_logic_vector(31 downto 0);
signal minic_mem_wr : std_logic;
signal minic_src_out : t_wrf_source_out;
signal minic_src_in : t_wrf_source_in;
signal minic_snk_out : t_wrf_sink_out;
signal minic_snk_in : t_wrf_sink_in;
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_tx_d : std_logic_vector(15 downto 0);
signal phy_tx_k : std_logic_vector( 1 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_error : std_logic;
signal phy_rx_d : std_logic_vector(15 downto 0);
signal phy_rx_clk : std_logic;
signal phy_rx_k : std_logic_vector( 1 downto 0);
signal phy_rx_error : std_logic;
signal phy_rx_bitslide : std_logic_vector( 4 downto 0);
signal dpram_we : std_logic;
signal dpram_ack : std_logic;
-- one-wire master signals
signal owr_pwren : std_logic_vector(0 downto 0);
signal owr_en : std_logic_vector(0 downto 0);
signal owr_in : std_logic_vector(0 downto 0);
-- TTL pulse test signals
signal front_pulse_en : std_logic;
signal front_trigs_a : std_logic_vector(9 downto 0);
signal front_trigs : std_logic_vector(9 downto 0);
signal front_trigs_redge_p : std_logic_vector(9 downto 0);
signal front_pulses : std_logic_vector(9 downto 0);
signal front_pulses_d0 : std_logic_vector(9 downto 0);
signal front_pulses_redge_p : std_logic_vector(9 downto 0);
-- Rear panel test signals
signal tester_vcc : std_logic;
signal tester_mux_en : std_logic;
signal tester_s0 : std_logic;
signal tester_s1 : std_logic;
signal tester_ctrl : std_logic_vector(3 downto 0);
signal rear_pulse_en : std_logic;
signal rear_pulses : std_logic_vector(5 downto 0);
signal rear_pulses_d0 : std_logic_vector(5 downto 0);
signal rear_pulses_redge_p : std_logic_vector(5 downto 0);
signal rear_trigs_a : std_logic_vector(5 downto 0);
signal rear_trigs : std_logic_vector(5 downto 0);
signal rear_trigs_redge_p : std_logic_vector(5 downto 0);
-- Pulse counter register signals
signal ipcr_ld : std_logic_vector(15 downto 0);
signal ipcr_ldval : t_pcr_ldval;
signal ipcr : t_pcr;
signal opcr_ld : std_logic_vector(15 downto 0);
signal opcr_ldval : t_pcr_ldval;
signal opcr : t_pcr;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Differential input buffer for 125 MHz clock
--============================================================================
cmp_clk_125_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting
-- for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map
(
O => clk_125,
I => clk_125_p_i,
IB => clk_125_n_i
);
--============================================================================
-- Internal reset generation
--============================================================================
-- External reset input to reset generator
rst_ext <= rst_bit or (not vme_sysreset_n_i);
-- Configure reset generator for 100ms reset
cmp_reset_gen : conv_reset_gen
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**6)
)
port map
(
clk_i => clk_20_i,
rst_i => rst_ext,
rst_n_o => rst_20_n
);
-- Create an active-high reset signal
rst_20 <= not rst_20_n;
-- Create a reset signal in the 125-MHz clock domain
cmp_rst_125_sync : gc_sync_ffs
port map
(
clk_i => clk_125,
rst_n_i => '1',
data_i => rst_20_n,
synced_o => rst_125_n
);
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [2]
i2c_addr <= "10" & vme_ga_i;
-- Instantiate I2C bridge component
--
-- FSM watchdog timeout timer:
-- * consider bit period of 30 us
-- * 10 bits / byte transfer => 300 us
-- * 40 bytes in one transfer => 12000 us
-- * clk_i period = 50 ns => g_fsm_wdt = 12000 us / 50 ns = 240000
-- * multiply by two for extra safety => g_fsm_wdt = 480000
-- * Time to watchdog timeout: 480000 * 50ns = 24 ms
cmp_i2c_bridge : wb_i2c_bridge
generic map
(
g_fsm_wdt => 480000
)
port map
(
-- Clock, reset
clk_i => clk_20_i,
rst_n_i => rst_20_n,
-- I2C lines
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_en_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_en_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
-- TIP and ERR outputs
tip_o => i2c_tip,
err_p_o => i2c_err_p,
wdto_p_o => i2c_wdto_p,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Register for the I2C_WDTO bit in the SR, cleared by writing a '1'
p_sr_wdto_bit : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
i2c_wdto_bit <= '0';
elsif (i2c_wdto_p = '1') then
i2c_wdto_bit <= '1';
elsif (i2c_wdto_bit_rst_ld = '1') and (i2c_wdto_bit_rst = '1') then
i2c_wdto_bit <= '0';
end if;
end if;
end process p_sr_wdto_bit;
-- Register for the I2C_ERR bit in the SR
p_i2c_err_led : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
i2c_err_bit <= '0';
elsif (i2c_err_p = '1') then
i2c_err_bit <= '1';
elsif (i2c_err_bit_rst_ld = '1') and (i2c_err_bit_rst = '1') then
i2c_err_bit <= '0';
end if;
end if;
end process p_i2c_err_led;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- PTS registers
--============================================================================
-- RTM lines combo
rtm_lines <= rtmp_i & rtmm_i;
switches <= not sw_gp_n_i;
-- LSR signals
line_front <= not (ttl_n_i);
line_inv <= not (inv_n_i);
line_rear <= not (rs485_n_i);
line_rear_fs <= rs485_n_i nor rs485_fs_n_i;
-- Regs to test I2C operation
cmp_pts_regs : pts_regs
port map
(
rst_n_i => rst_20_n,
clk_sys_i => clk_20_i,
wb_adr_i => xbar_master_out(c_slv_pts_regs).adr(3 downto 2),
wb_dat_i => xbar_master_out(c_slv_pts_regs).dat,
wb_dat_o => xbar_master_in(c_slv_pts_regs).dat,
wb_cyc_i => xbar_master_out(c_slv_pts_regs).cyc,
wb_sel_i => xbar_master_out(c_slv_pts_regs).sel,
wb_stb_i => xbar_master_out(c_slv_pts_regs).stb,
wb_we_i => xbar_master_out(c_slv_pts_regs).we,
wb_ack_o => xbar_master_in(c_slv_pts_regs).ack,
wb_stall_o => xbar_master_in(c_slv_pts_regs).stall,
-- Board ID register
pts_bidr_i => c_board_id,
-- PTS control register
pts_csr_fledt_o => pulse_led_en,
pts_csr_rledt_o => open,
pts_csr_stledt_o => stat_led_en,
pts_csr_ttlpt_o => front_pulse_en,
pts_csr_rs485pt_o => rear_pulse_en,
pts_csr_tstcvcc_o => tester_vcc,
pts_csr_tstcmuxen_o => tester_mux_en,
pts_csr_tstcs0_o => tester_s0,
pts_csr_tstcs1_o => tester_s1,
pts_csr_rst_unlock_o => rst_unlock_ldval,
pts_csr_rst_unlock_i => rst_unlock,
pts_csr_rst_unlock_load_o => rst_unlock_ld,
pts_csr_rst_o => rst_bit_ldval,
pts_csr_rst_i => rst_bit,
pts_csr_rst_load_o => rst_bit_ld,
pts_csr_switch_i => switches,
pts_csr_rtm_i => rtm_lines,
pts_csr_i2c_err_o => i2c_err_bit_rst,
pts_csr_i2c_err_i => i2c_err_bit,
pts_csr_i2c_err_load_o => i2c_err_bit_rst_ld,
pts_csr_i2c_wdto_o => i2c_wdto_bit_rst,
pts_csr_i2c_wdto_i => i2c_wdto_bit,
pts_csr_i2c_wdto_load_o => i2c_wdto_bit_rst_ld,
pts_lsr_front_i => line_front,
pts_lsr_frontinv_i => line_inv,
pts_lsr_rear_i => line_rear,
pts_lsr_frontfs_i => (others => '0'),
pts_lsr_frontinvfs_i => (others => '0'),
pts_lsr_rearfs_i => line_rear_fs,
pts_ter_iterm_o => iterm_en_o,
pts_ter_oterm_o => oterm_en_o
);
-- Implement the RST_UNLOCK bit
p_rst_unlock : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
rst_unlock <= '0';
elsif (rst_unlock_ld = '1') then
if (rst_unlock_ldval = '1') then
rst_unlock <= '1';
else
rst_unlock <= '0';
end if;
end if;
end if;
end process p_rst_unlock;
-- Implement the reset bit register
-- The register can only be set when the RST_UNLOCK bit is '1'.
p_rst_fr_reg : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
rst_bit <= '0';
elsif (rst_bit_ld = '1') and (rst_bit_ldval = '1') and (rst_unlock = '1') then
rst_bit <= '1';
else
rst_bit <= '0';
end if;
end if;
end process p_rst_fr_reg;
--============================================================================
-- PLL test logic
-- * test 20MHz VCXO
-- * test 125MHz PLL from TI
-- * test Analog Devices AD5662 DACs used to control operation of the two
-- oscillators
--============================================================================
-----------------------------------------------------------------------------
-- 20-MHz VCXO test
-----------------------------------------------------------------------------
-- First, create the reset signal for the 20-MHz clock counter
cnt_20_actual_rst <= cnt_20_rst or rst_20;
-- Instantiate clock info slave
cmp_clk_info_20 : clk_info_wb_slave
port map
(
wb_clk_i => clk_20_i,
rst_i => rst_20,
wb_cyc_i => xbar_master_out(c_slv_clk_info_20).cyc,
wb_stb_i => xbar_master_out(c_slv_clk_info_20).stb,
wb_addr_i => xbar_master_out(c_slv_clk_info_20).adr(4 downto 2),
wb_data_i => xbar_master_out(c_slv_clk_info_20).dat,
wb_we_i => xbar_master_out(c_slv_clk_info_20).we,
wb_data_o => xbar_master_in(c_slv_clk_info_20).dat,
wb_ack_o => xbar_master_in(c_slv_clk_info_20).ack,
counter_is_full_i => cnt_20_full,
counter_now_i => cnt_20,
counter_top_o => cnt_20_top,
counter_rst_o => cnt_20_rst,
counter_en_o => cnt_20_en,
oe_clk_o => open
);
-- Then, instantiate increment counter for 20-MHz clock
cmp_incr_counter_20 : incr_counter
generic map
(
width => 32
)
port map
(
clk_i => clk_20_i,
rst_i => cnt_20_actual_rst,
counter_top_i => cnt_20_top,
counter_incr_en_i => cnt_20_en,
counter_o => cnt_20,
counter_is_full_o => cnt_20_full
);
-- Instantate a Wishbone SPI module to control 20-MHz DAC operation
cmp_dac_20_spi : wb_spi
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
wb_adr_i => xbar_master_out(c_slv_dac_spi_20).adr(6 downto 2),
wb_dat_i => xbar_master_out(c_slv_dac_spi_20).dat,
wb_dat_o => xbar_master_in(c_slv_dac_spi_20).dat,
wb_sel_i => xbar_master_out(c_slv_dac_spi_20).sel,
wb_stb_i => xbar_master_out(c_slv_dac_spi_20).stb,
wb_cyc_i => xbar_master_out(c_slv_dac_spi_20).cyc,
wb_we_i => xbar_master_out(c_slv_dac_spi_20).we,
wb_ack_o => xbar_master_in(c_slv_dac_spi_20).ack,
wb_err_o => xbar_master_in(c_slv_dac_spi_20).err,
wb_int_o => xbar_master_in(c_slv_dac_spi_20).int,
wb_stall_o => xbar_master_in(c_slv_dac_spi_20).stall,
pad_cs_o => dac_20_sync_n,
pad_sclk_o => dac_20_sclk_o,
pad_mosi_o => dac_20_din_o,
pad_miso_i => '0'
);
-- Finally, assign the SYNC_N output to the DAC
dac_20_sync_n_o <= dac_20_sync_n(0);
-----------------------------------------------------------------------------
-- 125-MHz PLL test
-----------------------------------------------------------------------------
-- Instantiate clock info slave
cmp_clk_info_125 : clk_info_wb_slave
port map
(
wb_clk_i => clk_20_i,
rst_i => rst_20,
wb_cyc_i => xbar_master_out(c_slv_clk_info_125).cyc,
wb_stb_i => xbar_master_out(c_slv_clk_info_125).stb,
wb_addr_i => xbar_master_out(c_slv_clk_info_125).adr(4 downto 2),
wb_data_i => xbar_master_out(c_slv_clk_info_125).dat,
wb_we_i => xbar_master_out(c_slv_clk_info_125).we,
wb_data_o => xbar_master_in(c_slv_clk_info_125).dat,
wb_ack_o => xbar_master_in(c_slv_clk_info_125).ack,
counter_is_full_i => cnt_125_full,
counter_now_i => cnt_125_a,
counter_top_o => cnt_125_top_a,
counter_rst_o => cnt_125_rst_a,
counter_en_o => cnt_125_en_a,
oe_clk_o => open
);
-- Sync FIFO for counter top value
cmp_cnt_top_20_to_125 : generic_async_fifo
generic map
(
g_data_width => 32,
g_size => 4
)
port map
(
rst_n_i => rst_20_n,
clk_wr_i => clk_20_i,
d_i => cnt_125_top_a,
we_i => '1',
clk_rd_i => clk_125,
q_o => cnt_125_top,
rd_i => '1'
);
-- Sync FF chain for 125-MHz clock counter reset signal
cmp_cnt_125_rst_sync : gc_sync_ffs
port map
(
clk_i => clk_125,
rst_n_i => rst_125_n,
data_i => cnt_125_rst_a,
synced_o => cnt_125_rst
);
-- Sync FF chain for 125-MHz clock counter enable signal
cmp_cnt_125_en_sync : gc_sync_ffs
port map
(
clk_i => clk_125,
rst_n_i => rst_125_n,
data_i => cnt_125_en_a,
synced_o => cnt_125_en
);
-- Sync FIFO for current counter value
cmp_cnt_125_to_20 : generic_async_fifo
generic map
(
g_data_width => 32,
g_size => 8
)
port map
(
rst_n_i => rst_20_n,
clk_wr_i => clk_125,
d_i => cnt_125,
we_i => '1',
clk_rd_i => clk_20_i,
q_o => cnt_125_a,
rd_i => '1'
);
-- Create a reset signal for the 125-MHz clock counter
cnt_125_actual_rst <= cnt_125_rst or (not rst_125_n);
-- Instantiate increment counter for 125-MHz clock
cmp_incr_counter_125 : incr_counter
generic map
(
width => 32
)
port map
(
clk_i => clk_125,
rst_i => cnt_125_actual_rst,
counter_top_i => cnt_125_top,
counter_incr_en_i => cnt_125_en,
counter_o => cnt_125,
counter_is_full_o => cnt_125_full
);
-- Instantate a Wishbone SPI module to control 125-MHz DAC operation
cmp_dac_125_spi : wb_spi
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
wb_adr_i => xbar_master_out(c_slv_dac_spi_125).adr(6 downto 2),
wb_dat_i => xbar_master_out(c_slv_dac_spi_125).dat,
wb_dat_o => xbar_master_in(c_slv_dac_spi_125).dat,
wb_sel_i => xbar_master_out(c_slv_dac_spi_125).sel,
wb_stb_i => xbar_master_out(c_slv_dac_spi_125).stb,
wb_cyc_i => xbar_master_out(c_slv_dac_spi_125).cyc,
wb_we_i => xbar_master_out(c_slv_dac_spi_125).we,
wb_ack_o => xbar_master_in(c_slv_dac_spi_125).ack,
wb_err_o => xbar_master_in(c_slv_dac_spi_125).err,
wb_int_o => xbar_master_in(c_slv_dac_spi_125).int,
wb_stall_o => xbar_master_in(c_slv_dac_spi_125).stall,
pad_cs_o => dac_125_sync_n,
pad_sclk_o => dac_125_sclk_o,
pad_mosi_o => dac_125_din_o,
pad_miso_i => '0'
);
-- Finally, assign the SYNC_N output to the DAC
dac_125_sync_n_o <= dac_125_sync_n(0);
--============================================================================
-- SFP EEPROM test logic
-- * test SFP I2C EEPROM with an I2C master
--============================================================================
-- First, instantiate an I2C master to handle SFP communication
cmp_sfp_eeprom_i2c : wb_i2c_master
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
wb_adr_i => xbar_master_out(c_slv_sfp_i2c).adr(6 downto 2),
wb_dat_i => xbar_master_out(c_slv_sfp_i2c).dat,
wb_we_i => xbar_master_out(c_slv_sfp_i2c).we,
wb_stb_i => xbar_master_out(c_slv_sfp_i2c).stb,
wb_sel_i => xbar_master_out(c_slv_sfp_i2c).sel,
wb_cyc_i => xbar_master_out(c_slv_sfp_i2c).cyc,
wb_ack_o => xbar_master_in(c_slv_sfp_i2c).ack,
wb_int_o => xbar_master_in(c_slv_sfp_i2c).int,
wb_dat_o => xbar_master_in(c_slv_sfp_i2c).dat,
scl_pad_i => i2c_scl_fr_sfp,
scl_pad_o => i2c_scl_to_sfp,
scl_padoen_o => i2c_sfp_scl_en,
sda_pad_i => i2c_sda_fr_sfp,
sda_pad_o => i2c_sda_to_sfp,
sda_padoen_o => i2c_sfp_sda_en
);
-- and assign the ports and tri-state buffers
sfp_scl_b <= i2c_scl_to_sfp when (i2c_sfp_scl_en = '0') else 'Z';
i2c_scl_fr_sfp <= sfp_scl_b;
sfp_sda_b <= i2c_sda_to_sfp when (i2c_sfp_sda_en = '0') else 'Z';
i2c_sda_fr_sfp <= sfp_sda_b;
--============================================================================
-- SFP loopback test logic
-- * test J1 SFP connector using an SFP loopback module
--============================================================================
-- First, instantiate an IBUFGDS for MGT clock
cmp_mgt_clk_ibufds : IBUFDS
generic map
(
DIFF_TERM => true,
IBUF_LOW_PWR => false,
IOSTANDARD => "DEFAULT"
)
port map
(
I => mgt_clk0_p_i,
IB => mgt_clk0_n_i,
O => clk_gtp
);
-- Connect the MINIC module to the crossbar
cmp_sfp_minic : xwr_mini_nic
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_memsize_log2 => c_minic_memsize_log2,
g_buffer_little_endian => true
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
mem_data_o => minic_mem_data_out,
mem_addr_o => minic_mem_addr_out,
mem_data_i => minic_mem_data_in,
mem_wr_o => minic_mem_wr,
src_o => minic_src_out,
src_i => minic_src_in,
snk_o => minic_snk_out,
snk_i => minic_snk_in,
txtsu_port_id_i => "00000",
txtsu_frame_id_i => x"0000",
txtsu_tsval_i => x"00000000",
txtsu_tsincorrect_i => '0',
txtsu_stb_i => '0',
wb_i => xbar_master_out(c_slv_minic),
wb_o => xbar_master_in(c_slv_minic)
);
-- Connect the endpoint buffer RAM
cmp_sfp_dpram : generic_dpram
generic map
(
g_data_width => 32,
g_size => 2**c_minic_memsize_log2,
g_with_byte_enable => false,
g_dual_clock => false
)
port map
(
rst_n_i => rst_20_n,
clka_i => clk_20_i,
bwea_i => "0000",
wea_i => dpram_we,
aa_i => xbar_master_out(c_slv_dpram).adr(c_minic_memsize_log2+1 downto 2),
da_i => xbar_master_out(c_slv_dpram).dat,
qa_o => xbar_master_in(c_slv_dpram).dat,
clkb_i => clk_20_i,
bweb_i => "0000",
web_i => minic_mem_wr,
ab_i => minic_mem_addr_out,
db_i => minic_mem_data_out,
qb_o => minic_mem_data_in
);
-- associate WE to first port of the RAM to WB signals
dpram_we <= xbar_master_out(c_slv_dpram).cyc and xbar_master_out(c_slv_dpram).stb and
xbar_master_out(c_slv_dpram).we;
-- ACK logic for DPRAM
xbar_master_in(c_slv_dpram).ack <= dpram_ack;
xbar_master_in(c_slv_dpram).err <= '0';
p_ram_ack : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
dpram_ack <= '0';
else
dpram_ack <= '0';
if (xbar_master_out(c_slv_dpram).stb = '1') and
(xbar_master_out(c_slv_dpram).cyc = '1') then
dpram_ack <= '1';
end if;
end if;
end if;
end process p_ram_ack;
-- Connect the Endpoint module to the crossbar
cmp_sfp_endpoint : xwr_endpoint
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_simulation => false,
g_tx_force_gap_length => 0,
g_pcs_16bit => false,
g_rx_buffer_size => 1024,
g_with_rx_buffer => true,
g_with_flow_control => false,
g_with_timestamper => true,
g_with_dpi_classifier => false,
g_with_vlans => false,
g_with_rtu => false,
g_with_leds => false,
g_with_dmtd => false
)
port map
(
clk_ref_i => clk_125,
clk_sys_i => clk_20_i,
clk_dmtd_i => clk_125,
rst_n_i => rst_20_n,
pps_csync_p1_i => '0',
pps_valid_i => '0',
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_ref_clk_i => clk_125,
phy_tx_data_o => phy_tx_d,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_error,
phy_rx_data_i => phy_rx_d,
phy_rx_clk_i => phy_rx_clk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_error,
phy_rx_bitslide_i => phy_rx_bitslide,
src_o => minic_snk_in,
src_i => minic_snk_out,
snk_o => minic_src_in,
snk_i => minic_src_out,
wb_i => xbar_master_out(c_slv_endpoint),
wb_o => xbar_master_in(c_slv_endpoint)
);
-- Finally, connect the GTP transceiver to the endpoint signals
cmp_gtp_xceiver : wr_gtp_phy_spartan6
generic map
(
g_simulation => 0,
g_force_disparity => 1,
g_enable_ch0 => 1,
g_enable_ch1 => 0
)
port map
(
gtp_clk_i => clk_gtp,
ch0_ref_clk_i => clk_125,
ch0_tx_data_i => phy_tx_d(7 downto 0),
ch0_tx_k_i => phy_tx_k(0),
ch0_tx_disparity_o => phy_tx_disparity,
ch0_tx_enc_err_o => phy_tx_error,
ch0_rx_rbclk_o => phy_rx_clk,
ch0_rx_data_o => phy_rx_d(7 downto 0),
ch0_rx_k_o => phy_rx_k(0),
ch0_rx_enc_err_o => phy_rx_error,
ch0_rx_bitslide_o => phy_rx_bitslide(3 downto 0),
ch0_rst_i => phy_rst,
ch0_loopen_i => phy_loopen,
pad_txn0_o => mgt_sfp_tx0_n_o,
pad_txp0_o => mgt_sfp_tx0_p_o,
pad_rxn0_i => mgt_sfp_rx0_n_i,
pad_rxp0_i => mgt_sfp_rx0_p_i
);
--============================================================================
-- Thermometer test logic
--============================================================================
-- The one-wire master component is used to control the on-board DS18B20
-- thermometer
cmp_onewire_master : wb_onewire_master
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
wb_cyc_i => xbar_master_out(c_slv_onewire_mst).cyc,
wb_sel_i => xbar_master_out(c_slv_onewire_mst).sel,
wb_stb_i => xbar_master_out(c_slv_onewire_mst).stb,
wb_we_i => xbar_master_out(c_slv_onewire_mst).we,
wb_adr_i => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
wb_dat_i => xbar_master_out(c_slv_onewire_mst).dat,
wb_dat_o => xbar_master_in(c_slv_onewire_mst).dat,
wb_ack_o => xbar_master_in(c_slv_onewire_mst).ack,
wb_int_o => open,
wb_stall_o => xbar_master_in(c_slv_onewire_mst).stall,
owr_pwren_o => owr_pwren,
owr_en_o => owr_en,
owr_i => owr_in
);
-- Generate tri-state buffer for thermometer
thermometer_b <= '0' when (owr_en(0) = '1') else
'Z';
owr_in(0) <= thermometer_b;
--============================================================================
-- TTL pulse test logic
--============================================================================
-- Channel enable outputs
global_oen_o <= '1';
ttl_oen_o <= front_pulse_en;
inv_oen_o <= front_pulse_en or tester_vcc;
-- First, instantiate a general-purpose pulse generator to generate the output
-- pulse from CH1 to CH2
--
-- 1-us pulses are generated twice a second.
cmp_first_pulse_gen : pulse_gen_gp
port map (
-- Input clock and active-low reset
clk_i => clk_20_i,
rst_n_i => rst_20_n,
-- Active high enable signal
en_i => front_pulse_en,
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i => x"00000000",
pwidth_i => x"00000014",
freq_i => x"00989680",
-- Output pulse signal
pulse_o => front_pulses(0)
);
-- Assign the TTL, INV-TTL inputs to internal signals
front_trigs_a(5 downto 0) <= not ttl_n_i;
front_trigs_a(9 downto 6) <= not inv_n_i;
-- Synchronize these signals in the 20-MHz clock domain
gen_ttl_sync_chains : for i in 0 to 9 generate
cmp_ttl_sync_chain : gc_sync_ffs
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
data_i => front_trigs_a(i),
synced_o => front_trigs(i),
ppulse_o => front_trigs_redge_p(i)
);
end generate gen_ttl_sync_chains;
-- Now, generate nine pulse generator blocks connected to the TTL outputs
-- and with the TTL inputs as triggers.
--
-- External to the FPGA, the inputs of CH2 are expected to be connected to CH1,
-- which generates pulses for the daisy-chain, then CH2 outputs to CH3, CH3 to
-- CH4 and so on, until the last INV_TTL output, which is expected to
-- be connected back to the input of CH1.
--
-- The pulse generator is configured for fixed-width pulses of 1us.
gen_front_pulse_gens : for i in 1 to 9 generate
cmp_pulse_gens : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => true,
g_pwidth => 20,
g_duty_cycle_div => 5
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
gf_en_n_i => '1',
en_i => front_pulse_en,
trig_a_i => front_trigs(i),
pulse_err_p_o => open,
pulse_o => front_pulses(i)
);
end generate gen_front_pulse_gens;
-- Assign the FPGA outputs for the TTL channels
ttl_o <= front_pulses(5 downto 0);
inv_o <= front_pulses(9 downto 6) when (front_pulse_en = '1') else
tester_ctrl;
-- Implement the pulse counter registers for the TTL channels
gen_other_front_pulse_logic : for i in 0 to 9 generate
-- First, some rising-edge detectors for output pulses
p_front_pulse_redge : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
front_pulses_d0(i) <= '0';
front_pulses_redge_p(i) <= '0';
else
front_pulses_d0(i) <= front_pulses(i);
front_pulses_redge_p(i) <= front_pulses(i) and (not front_pulses_d0(i));
end if;
end if;
end process p_front_pulse_redge;
-- Now, the actual I/O pulse counters
p_front_pulse_cnt : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
opcr(i) <= (others => '0');
ipcr(i) <= (others => '0');
else
if (opcr_ld(i) = '1') then
opcr(i) <= unsigned(opcr_ldval(i));
elsif (front_pulses_redge_p(i) = '1') then
opcr(i) <= opcr(i) + 1;
end if;
if (ipcr_ld(i) = '1') then
ipcr(i) <= unsigned(ipcr_ldval(i));
elsif (front_trigs_redge_p(i) = '1') then
ipcr(i) <= ipcr(i) + 1;
end if;
end if;
end if;
end process p_front_pulse_cnt;
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_front_led : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
front_led_cnt(i) <= (others => '0');
front_led(i) <= '0';
else
case front_led(i) is
when '0' =>
if (front_pulses_redge_p(i) = '1') then
front_led(i) <= '1';
end if;
when '1' =>
front_led_cnt(i) <= front_led_cnt(i) + 1;
if (front_led_cnt(i) = (front_led_cnt(i)'range => '1')) then
front_led(i) <= '0';
end if;
when others =>
front_led(i) <= '0';
end case;
end if;
end if;
end process p_front_led;
end generate gen_other_front_pulse_logic;
--============================================================================
-- Rear panel pulse test logic
--============================================================================
-- Compose the tester control lines out of the PTS reg bits
tester_ctrl <= tester_s1 & tester_s0 & tester_mux_en & tester_vcc;
-- Assign rear panel inputs to local signals
rear_trigs_a <= not rs485_n_i;
-- And now generate the logic for six pulse rep channels
gen_rear_test_logic : for i in 0 to 5 generate
-- Synchronize the inputs to the 20-MHz clock domain
cmp_rear_sync_chain : gc_sync_ffs
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
data_i => rear_trigs_a(i),
synced_o => rear_trigs(i),
ppulse_o => rear_trigs_redge_p(i)
);
-- Instantiate general-purpose pulse generators to generate the output pulses
-- 1-us pulses are generated twice a second.
cmp_rear_pulse_gen : pulse_gen_gp
port map (
-- Input clock and active-low reset
clk_i => clk_20_i,
rst_n_i => rst_20_n,
-- Active high enable signal
en_i => rear_pulse_en,
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i => x"00000000",
pwidth_i => x"00000014",
freq_i => x"00989680",
-- Output pulse signal
pulse_o => rear_pulses(i)
);
-- Implement some rising-edge detectors for the output pulses
p_rear_pulse_redge : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
rear_pulses_d0(i) <= '0';
rear_pulses_redge_p(i) <= '0';
else
rear_pulses_d0(i) <= rear_pulses(i);
rear_pulses_redge_p(i) <= rear_pulses(i) and (not rear_pulses_d0(i));
end if;
end if;
end process p_rear_pulse_redge;
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_rear_led : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
rear_led_cnt(i) <= (others => '0');
rear_led(i) <= '0';
else
case rear_led(i) is
when '0' =>
if (rear_pulses_redge_p(i) = '1') then
rear_led(i) <= '1';
end if;
when '1' =>
rear_led_cnt(i) <= rear_led_cnt(i) + 1;
if (rear_led_cnt(i) = (rear_led_cnt(i)'range => '1')) then
rear_led(i) <= '0';
end if;
when others =>
rear_led(i) <= '0';
end case;
end if;
end if;
end process p_rear_led;
-- Implement the pulse counters for the rear panel channels
-- Note: pulse counters for rear panel channels are indexes 10..15 of signal
p_rear_pulse_cnt : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
opcr(i+10) <= (others => '0');
ipcr(i+10) <= (others => '0');
else
if (opcr_ld(i+10) = '1') then
opcr(i+10) <= unsigned(opcr_ldval(i+10));
elsif (rear_pulses_redge_p(i) = '1') then
opcr(i+10) <= opcr(i+10) + 1;
end if;
if (ipcr_ld(i+10) = '1') then
ipcr(i+10) <= unsigned(ipcr_ldval(i+10));
elsif (rear_trigs_redge_p(i) = '1') then
ipcr(i+10) <= ipcr(i+10) + 1;
end if;
end if;
end if;
end process p_rear_pulse_cnt;
end generate gen_rear_test_logic;
-- Finally, assign the outputs
rs485_oen_o <= rear_pulse_en;
rs485_o <= rear_pulses;
--============================================================================
-- Pulse counter registers, retaining values for pulse counters of both RS-485
-- and TTL pulse repetition tests.
--============================================================================
cmp_pulse_cnt_regs : pulse_cnt_wb
port map (
rst_n_i => rst_20_n,
clk_sys_i => clk_20_i,
wb_adr_i => xbar_master_out(c_slv_pulse_cntrs).adr(6 downto 2),
wb_dat_i => xbar_master_out(c_slv_pulse_cntrs).dat,
wb_dat_o => xbar_master_in(c_slv_pulse_cntrs).dat,
wb_cyc_i => xbar_master_out(c_slv_pulse_cntrs).cyc,
wb_sel_i => xbar_master_out(c_slv_pulse_cntrs).sel,
wb_stb_i => xbar_master_out(c_slv_pulse_cntrs).stb,
wb_we_i => xbar_master_out(c_slv_pulse_cntrs).we,
wb_ack_o => xbar_master_in(c_slv_pulse_cntrs).ack,
wb_stall_o => xbar_master_in(c_slv_pulse_cntrs).stall,
pulse_cnt_ttlch1o_o => opcr_ldval(0),
pulse_cnt_ttlch1o_i => std_logic_vector(opcr(0)),
pulse_cnt_ttlch1o_load_o => opcr_ld(0),
pulse_cnt_ttlch1i_o => ipcr_ldval(0),
pulse_cnt_ttlch1i_i => std_logic_vector(ipcr(0)),
pulse_cnt_ttlch1i_load_o => ipcr_ld(0),
pulse_cnt_ttlch2o_o => opcr_ldval(1),
pulse_cnt_ttlch2o_i => std_logic_vector(opcr(1)),
pulse_cnt_ttlch2o_load_o => opcr_ld(1),
pulse_cnt_ttlch2i_o => ipcr_ldval(1),
pulse_cnt_ttlch2i_i => std_logic_vector(ipcr(1)),
pulse_cnt_ttlch2i_load_o => ipcr_ld(1),
pulse_cnt_ttlch3o_o => opcr_ldval(2),
pulse_cnt_ttlch3o_i => std_logic_vector(opcr(2)),
pulse_cnt_ttlch3o_load_o => opcr_ld(2),
pulse_cnt_ttlch3i_o => ipcr_ldval(2),
pulse_cnt_ttlch3i_i => std_logic_vector(ipcr(2)),
pulse_cnt_ttlch3i_load_o => ipcr_ld(2),
pulse_cnt_ttlch4o_o => opcr_ldval(3),
pulse_cnt_ttlch4o_i => std_logic_vector(opcr(3)),
pulse_cnt_ttlch4o_load_o => opcr_ld(3),
pulse_cnt_ttlch4i_o => ipcr_ldval(3),
pulse_cnt_ttlch4i_i => std_logic_vector(ipcr(3)),
pulse_cnt_ttlch4i_load_o => ipcr_ld(3),
pulse_cnt_ttlch5o_o => opcr_ldval(4),
pulse_cnt_ttlch5o_i => std_logic_vector(opcr(4)),
pulse_cnt_ttlch5o_load_o => opcr_ld(4),
pulse_cnt_ttlch5i_o => ipcr_ldval(4),
pulse_cnt_ttlch5i_i => std_logic_vector(ipcr(4)),
pulse_cnt_ttlch5i_load_o => ipcr_ld(4),
pulse_cnt_ttlch6o_o => opcr_ldval(5),
pulse_cnt_ttlch6o_i => std_logic_vector(opcr(5)),
pulse_cnt_ttlch6o_load_o => opcr_ld(5),
pulse_cnt_ttlch6i_o => ipcr_ldval(5),
pulse_cnt_ttlch6i_i => std_logic_vector(ipcr(5)),
pulse_cnt_ttlch6i_load_o => ipcr_ld(5),
pulse_cnt_invttlchao_o => opcr_ldval(6),
pulse_cnt_invttlchao_i => std_logic_vector(opcr(6)),
pulse_cnt_invttlchao_load_o => opcr_ld(6),
pulse_cnt_invttlchai_o => ipcr_ldval(6),
pulse_cnt_invttlchai_i => std_logic_vector(ipcr(6)),
pulse_cnt_invttlchai_load_o => ipcr_ld(6),
pulse_cnt_invttlchbo_o => opcr_ldval(7),
pulse_cnt_invttlchbo_i => std_logic_vector(opcr(7)),
pulse_cnt_invttlchbo_load_o => opcr_ld(7),
pulse_cnt_invttlchbi_o => ipcr_ldval(7),
pulse_cnt_invttlchbi_i => std_logic_vector(ipcr(7)),
pulse_cnt_invttlchbi_load_o => ipcr_ld(7),
pulse_cnt_invttlchco_o => opcr_ldval(8),
pulse_cnt_invttlchco_i => std_logic_vector(opcr(8)),
pulse_cnt_invttlchco_load_o => opcr_ld(8),
pulse_cnt_invttlchci_o => ipcr_ldval(8),
pulse_cnt_invttlchci_i => std_logic_vector(ipcr(8)),
pulse_cnt_invttlchci_load_o => ipcr_ld(8),
pulse_cnt_invttlchdo_o => opcr_ldval(9),
pulse_cnt_invttlchdo_i => std_logic_vector(opcr(9)),
pulse_cnt_invttlchdo_load_o => opcr_ld(9),
pulse_cnt_invttlchdi_o => ipcr_ldval(9),
pulse_cnt_invttlchdi_i => std_logic_vector(ipcr(9)),
pulse_cnt_invttlchdi_load_o => ipcr_ld(9),
pulse_cnt_rearch1o_o => opcr_ldval(10),
pulse_cnt_rearch1o_i => std_logic_vector(opcr(10)),
pulse_cnt_rearch1o_load_o => opcr_ld(10),
pulse_cnt_rearch1i_o => ipcr_ldval(10),
pulse_cnt_rearch1i_i => std_logic_vector(ipcr(10)),
pulse_cnt_rearch1i_load_o => ipcr_ld(10),
pulse_cnt_rearch2o_o => opcr_ldval(11),
pulse_cnt_rearch2o_i => std_logic_vector(opcr(11)),
pulse_cnt_rearch2o_load_o => opcr_ld(11),
pulse_cnt_rearch2i_o => ipcr_ldval(11),
pulse_cnt_rearch2i_i => std_logic_vector(ipcr(11)),
pulse_cnt_rearch2i_load_o => ipcr_ld(11),
pulse_cnt_rearch3o_o => opcr_ldval(12),
pulse_cnt_rearch3o_i => std_logic_vector(opcr(12)),
pulse_cnt_rearch3o_load_o => opcr_ld(12),
pulse_cnt_rearch3i_o => ipcr_ldval(12),
pulse_cnt_rearch3i_i => std_logic_vector(ipcr(12)),
pulse_cnt_rearch3i_load_o => ipcr_ld(12),
pulse_cnt_rearch4o_o => opcr_ldval(13),
pulse_cnt_rearch4o_i => std_logic_vector(opcr(13)),
pulse_cnt_rearch4o_load_o => opcr_ld(13),
pulse_cnt_rearch4i_o => ipcr_ldval(13),
pulse_cnt_rearch4i_i => std_logic_vector(ipcr(13)),
pulse_cnt_rearch4i_load_o => ipcr_ld(13),
pulse_cnt_rearch5o_o => opcr_ldval(14),
pulse_cnt_rearch5o_i => std_logic_vector(opcr(14)),
pulse_cnt_rearch5o_load_o => opcr_ld(14),
pulse_cnt_rearch5i_o => ipcr_ldval(14),
pulse_cnt_rearch5i_i => std_logic_vector(ipcr(14)),
pulse_cnt_rearch5i_load_o => ipcr_ld(14),
pulse_cnt_rearch6o_o => opcr_ldval(15),
pulse_cnt_rearch6o_i => std_logic_vector(opcr(15)),
pulse_cnt_rearch6o_load_o => opcr_ld(15),
pulse_cnt_rearch6i_o => ipcr_ldval(15),
pulse_cnt_rearch6i_i => std_logic_vector(ipcr(15)),
pulse_cnt_rearch6i_load_o => ipcr_ld(15)
);
--============================================================================
-- LED test logic
-- * test bicolor LEDs and its driving circuit
-- * test front panel LED logic and driving circuit
--============================================================================
-- Rising edge detector for pulse LED enable signal
p_pulse_led_en_risedge : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_led_en_d0 <= '0';
front_led_en_risedge_p <= '0';
else
pulse_led_en_d0 <= pulse_led_en;
front_led_en_risedge_p <= '0';
if (pulse_led_en_d0 = '0') and (pulse_led_en = '1') then
front_led_en_risedge_p <= '1';
end if;
end if;
end if;
end process p_pulse_led_en_risedge;
-- Rising edge detector for status LED enable signal
p_stat_led_en_risedge : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
stat_led_en_d0 <= '0';
stat_led_en_risedge_p <= '0';
else
stat_led_en_d0 <= stat_led_en;
stat_led_en_risedge_p <= '0';
if (stat_led_en_d0 = '0') and (stat_led_en = '1') then
stat_led_en_risedge_p <= '1';
end if;
end if;
end if;
end process p_stat_led_en_risedge;
-- Process to control the LED sequence counter
p_led_seq : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') or (stat_led_en_risedge_p = '1')
or (front_led_en_risedge_p = '1') then
cnt_halfsec <= (others => '0');
led_seq <= (others => '0');
elsif (pulse_led_en = '1') or (stat_led_en = '1') then
cnt_halfsec <= cnt_halfsec + 1;
if (cnt_halfsec = 9999999) then
cnt_halfsec <= (others => '0');
led_seq <= led_seq + 1;
if (led_seq = 24) then
led_seq <= (others => '0');
end if;
end if;
end if;
end if;
end process p_led_seq;
-- Light each LED red and green in a sequence, based on the sequence counter.
--
-- The colors are set via the LED state vector (two bits per LED) as follows:
-- state(1..0) color
-- 00 OFF
-- 01 RED
-- 10 GREEN
bicolor_led_state <= "000000000001000000000000" when (stat_led_en = '1') and (led_seq = 1) else
"000000000100000000000000" when (stat_led_en = '1') and (led_seq = 2) else
"000000010000000000000000" when (stat_led_en = '1') and (led_seq = 3) else
"000001000000000000000000" when (stat_led_en = '1') and (led_seq = 4) else
"000000000000000001000000" when (stat_led_en = '1') and (led_seq = 5) else
"000000000000000000010000" when (stat_led_en = '1') and (led_seq = 6) else
"000000000000000000000100" when (stat_led_en = '1') and (led_seq = 7) else
"000000000000000000000001" when (stat_led_en = '1') and (led_seq = 8) else
"000000000000000100000000" when (stat_led_en = '1') and (led_seq = 9) else
"000000000000010000000000" when (stat_led_en = '1') and (led_seq = 10) else
"000100000000000000000000" when (stat_led_en = '1') and (led_seq = 11) else
"010000000000000000000000" when (stat_led_en = '1') and (led_seq = 12) else
"000000000010000000000000" when (stat_led_en = '1') and (led_seq = 13) else
"000000001000000000000000" when (stat_led_en = '1') and (led_seq = 14) else
"000000100000000000000000" when (stat_led_en = '1') and (led_seq = 15) else
"000010000000000000000000" when (stat_led_en = '1') and (led_seq = 16) else
"000000000000000010000000" when (stat_led_en = '1') and (led_seq = 17) else
"000000000000000000100000" when (stat_led_en = '1') and (led_seq = 18) else
"000000000000000000001000" when (stat_led_en = '1') and (led_seq = 19) else
"000000000000000000000010" when (stat_led_en = '1') and (led_seq = 20) else
"000000000000001000000000" when (stat_led_en = '1') and (led_seq = 21) else
"000000000000100000000000" when (stat_led_en = '1') and (led_seq = 22) else
"001000000000000000000000" when (stat_led_en = '1') and (led_seq = 23) else
"100000000000000000000000" when (stat_led_en = '1') and (led_seq = 24) else
"000000000000000000000000";
-- Sequence the front-panel LEDs based on the sequence counter
front_led_seq <= "000001" when (pulse_led_en = '1') and (led_seq = 1) else
"000010" when (pulse_led_en = '1') and (led_seq = 2) else
"000100" when (pulse_led_en = '1') and (led_seq = 3) else
"001000" when (pulse_led_en = '1') and (led_seq = 4) else
"010000" when (pulse_led_en = '1') and (led_seq = 5) else
"100000" when (pulse_led_en = '1') and (led_seq = 6) else
"000001" when (pulse_led_en = '1') and (led_seq = 11) else
"000010" when (pulse_led_en = '1') and (led_seq = 12) else
"000100" when (pulse_led_en = '1') and (led_seq = 13) else
"001000" when (pulse_led_en = '1') and (led_seq = 14) else
"010000" when (pulse_led_en = '1') and (led_seq = 15) else
"100000" when (pulse_led_en = '1') and (led_seq = 16) else
"000000";
-- Sequence the inverter LEDs
inv_led_seq <= "0001" when (pulse_led_en = '1') and (led_seq = 7) else
"0010" when (pulse_led_en = '1') and (led_seq = 8) else
"0100" when (pulse_led_en = '1') and (led_seq = 9) else
"1000" when (pulse_led_en = '1') and (led_seq = 10) else
"0001" when (pulse_led_en = '1') and (led_seq = 17) else
"0010" when (pulse_led_en = '1') and (led_seq = 18) else
"0100" when (pulse_led_en = '1') and (led_seq = 19) else
"1000" when (pulse_led_en = '1') and (led_seq = 20) else
"0000";
-- Then, we instantiate the LED controller and control it via the LED state
-- vector.
cmp_bicolor_led_ctrl : gc_bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 20000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_ttl_i2c_o,
column_o(1) => led_oterm_wr_o,
column_o(2) => led_iterm_syserror_o,
column_o(3) => led_gf_syspw_o,
column_o(4) => led_gp_2_4_o,
column_o(5) => led_gp_1_3_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
--============================================================================
-- Drive pulse LEDs
--============================================================================
led_front_o <= front_led_seq when (pulse_led_en = '1') else
front_led(5 downto 0);
led_inv_o <= inv_led_seq when (pulse_led_en = '1') else
tester_ctrl when (tester_vcc = '1') else
front_led(9 downto 6);
led_rear_n_o <= not front_led_seq when (pulse_led_en = '1') else
not rear_led(5 downto 0);
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
flash_cs_n_o <= '1';
flash_mosi_o <= '0';
flash_sclk_o <= '0';
-- SFP lines all open-drain, set to high-impedance
sfp_rate_select_o <= 'Z';
sfp_tx_disable_o <= 'Z';
end architecture arch;
--==============================================================================
-- architecture end
--==============================================================================
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/ 0000775 0000000 0000000 00000000000 12432353720 0022702 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/Makefile 0000664 0000000 0000000 00000002454 12432353720 0024347 0 ustar 00root root 0000000 0000000 ELMAIP =
ELMAPWD =
ELMASLOT =
all:
mkdir -p ubuntu/t485/log
touch ubuntu/t485/log/fan-speeds
cp -r shell/ ubuntu/t485/
mkdir -p ubuntu/t485/pyts/
cp python/* ubuntu/t485/pyts/
sed -i "s/ELMAIP = \"\"/ELMAIP = \"$(ELMAIP)\"/" ubuntu/t485/pyts/ptsdefine.py
sed -i "s/ELMAPWD = \"\"/ELMAPWD = \"$(ELMAPWD)\"/" ubuntu/t485/pyts/ptsdefine.py
sed -i "s/ELMASLOT =/ELMASLOT = $(ELMASLOT)/" ubuntu/t485/pyts/ptsdefine.py
cp ubuntu/t485/pyts/pts.py ubuntu/t485/pts
cp ubuntu/t485/pyts/jpts.py ubuntu/t485/jpts
ln -s pyts/dac_vcxo_pll.py ubuntu/t485/test01.py
ln -s pyts/leds.py ubuntu/t485/test02.py
ln -s pyts/ttl_pulse_switch.py ubuntu/t485/test03.py
ln -s pyts/rs485_pulse_rtm.py ubuntu/t485/test04.py
ln -s pyts/therm_id.py ubuntu/t485/test05.py
ln -s pyts/sfp_eeprom.py ubuntu/t485/test06.py
ln -s pyts/sfp_test.py ubuntu/t485/test07.py
ln -s pyts/flashtest.py ubuntu/t485/flashtest.py
mkdir -p ubuntu/t485/boot
mv ubuntu/t485/shell/program ubuntu/t485/boot
mv ubuntu/t485/shell/flash ubuntu/t485/boot
wget -P ubuntu/t485/boot http://www.ohwr.org/attachments/download/3680/pts.bit
wget -P ubuntu/t485/boot http://www.ohwr.org/attachments/download/3650/flash_load.bit
wget -P ubuntu/t485/boot http://www.ohwr.org/attachments/download/3657/golden-v0.0_release-v1.0.bin
clean:
rm -rf ubuntu/
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/ 0000775 0000000 0000000 00000000000 12432353720 0024223 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/dac_vcxo_pll.py 0000664 0000000 0000000 00000034225 12432353720 0027240 0 ustar 00root root 0000000 0000000 ##________________________________________________________________________________________________
##
## CONV-TTL-RS485 PTS
##
## CERN,BE/CO-HT
##________________________________________________________________________________________________
##
##------------------------------------------------------------------------------------------------
##
## CONV-TTL-RS485 DAC, VCXO, PLL test
##
##------------------------------------------------------------------------------------------------
##
## Description Testing of the VCXO, the 125-MHz PLL and the DAC chips that control operation of
## these two clocks. One DAC controls the operation of the 20MHz VCXO oscillator.
## This DAC shall be henceforth referred to as DAC_VCXO.
##
## Another DAC (DAC_PLL) controls a 25MHz VCXO, which in turn controls a TI PLL chip.
##
## The clocking scheme is shown below
## __________ ________
## ------| | | |
## SPI ------| DAC_VCXO |----->| VCXO |--------------------> 20MHz clk
## ------|__________| |________|
## __________ ________ ________
## ------| | | | | |
## SPI ------| DAC_PLL |----->| OSC |----->| PLL |----> PLL 125 MHz clk
## ------|__________| |________| |________|
##
## The gateware loaded to the FPGA implements the interface for the communication
## between the DACs and the I2C bus on the VME P1 connector. The DAC interface is an
## SPI Wishbone master, running at a system clock of 20MHz. The SPI Wishbone master
## for the DAC_VCXO can be accessed at base address 0x080. The SPI Wishbone master
## for the DAC_PLL can be accessed at base address 0x020.
##
## The FPGA receives the VCXO and PLL clock signals dedicated counters are used to
## count clock cycles, which can be controlled and checked via the Wishbone
## interface. The base address for the VCXO counter is 0x120. The base address for
## the PLL counter is 0x100.
##
## The following counter registers are used for controlling and evaluating the clks:
## base_addr + 0x10, bits 31..0: number of cycles counted so far
## base_addr + 0x14, bit 0: counter reset, active high
## base_addr + 0x18, bit 0: counter enable, active high
##
## The test starts by programming the DACs. The VCXO and the PLL counters are
## enabled and count clock cycles for ~2secs; the amount of counted cycles is an
## indication of the clock's frequency. The test continues with reprogramming the
## DACs and confirming that the amount of counted cycles by the counters changes
## accordingly; the higher the DAC value the faster the oscillators become and the
## larger the amount of cycles counted by the counters.
##
##
## Authors Julian Lewis (Julian.Lewis@cern.ch)
## Theodor Stana (t.stana@cern.ch)
## Website http://www.ohwr.org/projects/conv-ttl-rs485
## Date 31/10/2014
##------------------------------------------------------------------------------------------------
##
##------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
sys.path.append("pyts")
import time
import os
import math
# Import common modules
from ctypes import *
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## SPI class --
##-------------------------------------------------------------------------------------------------
class COpenCoresSPI:
R_RX = [0x00, 0x04, 0x08, 0x0C]
R_TX = [0x00, 0x04, 0x08, 0x0C]
R_CTRL = 0x10
R_DIV = 0x14
R_SS = 0x18
LGH_MASK = (0x7F)
CTRL_GO = (1<< 8)
CTRL_BSY = (1<< 8)
CTRL_RXNEG = (1<< 9)
CTRL_TXNEG = (1<<10)
CTRL_LSB = (1<<11)
CTRL_IE = (1<<12)
CTRL_ASS = (1<<13)
DIV_MASK = (0xFFFF)
SS_SEL = [0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40]
conf = 0x0
def wr_reg(self, addr, val):
self.bus.vv_write(self.base + addr,val)
def rd_reg(self,addr):
return self.bus.vv_read(self.base + addr)
def __init__(self, bus, base, divider):
self.bus = bus;
self.base = base;
self.wr_reg(self.R_DIV, (divider & self.DIV_MASK));
# default configuration
self.conf = self.CTRL_ASS # | self.CTRL_TXNEG
def wait_busy(self):
tmo = 1000
while(self.rd_reg(self.R_CTRL) & self.CTRL_BSY):
tmo = tmo -1
if tmo <= 0:
raise PtsError("Timeout waiting on busy flag")
def config(self, ass, rx_neg, tx_neg, lsb, ie):
self.conf = 0
if(ass):
self.conf |= self.CTRL_ASS
if(tx_neg):
self.conf |= self.CTRL_TXNEG
if(rx_neg):
self.conf |= self.CTRL_RXNEG
if(lsb):
self.conf |= self.CTRL_LSB
if(ie):
self.conf |= self.CTRL_IE
# slave = slave number (0 to 7)
# data = byte data array to send, in case if read fill with dummy data of the right size
# This transaction has been modified for this test!!
def transaction(self, slave, data):
self.wr_reg(self.R_SS, self.SS_SEL[slave])
txrx = [0x00000000, 0x00000000, 0x00000000, 0x00000000]
txrx[0] = 0x00FFFFFF & data
self.wr_reg(self.R_TX[0], txrx[0])
ctrl_reg = self.CTRL_ASS | self.CTRL_GO | 24
self.wr_reg(self.R_CTRL, 2018)
self.wr_reg(self.R_CTRL, 2118)
tmp = (self.rd_reg(self.R_CTRL) >> 8) & 0x00000001
tmo = 100
while(tmp == 1):
tmp = (self.rd_reg(self.R_CTRL) >> 8) & 0x00000001
tmo = tmo -1
if tmo <= 0:
msg = "ERROR: DAC IC52 or IC53: Not responding"
raise PtsError(msg)
return txrx
##-------------------------------------------------------------------------------------------------
## DAC AD5662 class --
##-------------------------------------------------------------------------------------------------
class DAC_AD5662:
PD0 = 16
PD1 = 17
OM_NORMAL = 0
OM_1K = 1
OM_100K = 2
OM_TRISTATE = 3
V_REF = 3.3
def __init__(self, spi):
self.dac_value = 0x0000
self.op = self.OM_NORMAL
self.spi = spi
def set_dac_voltage(self, voltage):
if (voltage >= self.V_REF):
"FAIL: please set a valid DAC_AD5662 voltage"
value = int(voltage / self.V_REF * 65536)
self.dac_value = value
def operation_mode(self, op):
self.op = op
def update_output(self):
data = (self.op << 16) + (self.dac_value)
self.spi.transaction(0, data)
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus,tname,inf,log):
"""
tests : DAC IC52, VCXO OSC3, DAC IC53, VCXO OSC1, PLL IC29
uses : pts.bit and dac_vcxo_pll.py
"""
VCXO_COUNTER_MARGIN = 2000000 # Expected value of a 20MHz counter after 100msec
VCXO_COUNTER_2SEC = 40000000 # Expected value of a 20MHz counter after 2sec
PLL_COUNTER_MARGIN = 12500000 # Expected value of a 125MHz counter after 100msec
PLL_COUNTER_2SEC = 250000000 # Expected value of a 125MHz counter after 2sec
pel = PTS_ERROR_LOGGER(inf,log)
dac_volts = [0.1, 0.8, 1.65, 2.4, 3.2]
vcxo = []
pll125 = []
for dac_volt in dac_volts:
# Setting DAC_VCXO
dac_vcxo_spi = COpenCoresSPI(bus, VCXO_DAC_BASE, 0x014) # divider=0x014: SCLK would be 5 MHz
dac = DAC_AD5662(dac_vcxo_spi)
dac.operation_mode(dac.OM_NORMAL)
dac.set_dac_voltage(dac_volt)
dac.update_output()
# Setting DAC_PLL
dac_pll_spi = COpenCoresSPI(bus, PLL_DAC_BASE, 0x014) # divider=0x014: SCLK woulb be 5 MHz
dac = DAC_AD5662(dac_pll_spi)
dac.operation_mode(dac.OM_NORMAL)
dac.set_dac_voltage(dac_volt)
dac.update_output()
# Resetting VCXO & PLL Counters
bus.vv_write(VCXO_CLKINFO_BASE + CLKINFO_RST_OFS, 1) # Reset VCXO counter
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_RST_OFS, 1) # Reset PLL IC29 counter
vcxo_count = bus.vv_read(VCXO_CLKINFO_BASE + CLKINFO_VALUE_OFS) # Read VCXO counter, counter is under reset
pll125_count = bus.vv_read(PLL_CLKINFO_BASE + CLKINFO_VALUE_OFS) # Read PLL IC29 counter, counter is under reset
# Enabling VCXO & PLL Counters
bus.vv_write(VCXO_CLKINFO_BASE + CLKINFO_ENABLE_OFS, 1) # Enable VCXO counter
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_ENABLE_OFS, 1) # Enable PLL IC29 counter
bus.vv_write(VCXO_CLKINFO_BASE + CLKINFO_RST_OFS, 0) # Release VCXO counter reset
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_RST_OFS, 0) # Release PLL IC29 counter reset
# VCXO & PLL Counters counting for 2 secs..
time.sleep(2)
bus.vv_write(VCXO_CLKINFO_BASE + CLKINFO_ENABLE_OFS, 0) # Disable VCXO counter
bus.vv_write(PLL_CLKINFO_BASE + CLKINFO_ENABLE_OFS, 0) # Disable PLL IC29 counter
# Reading VCXO & PLL Counters
vcxo_count = bus.vv_read(VCXO_CLKINFO_BASE + CLKINFO_VALUE_OFS) # Read VCXO counter
pll125_count = bus.vv_read(PLL_CLKINFO_BASE + CLKINFO_VALUE_OFS) # Read PLL IC29 counter
vcxo.append(vcxo_count)
pll125.append(pll125_count)
# Evaluating the VCXO and PLL clock frequencies at DAC middle value 1.65
if dac_volt == 1.65:
if (vcxo_count > (VCXO_COUNTER_2SEC-VCXO_COUNTER_MARGIN)) and (vcxo_count < (VCXO_COUNTER_2SEC+VCXO_COUNTER_MARGIN)):
msg = "VCXO OSC3: Frequency OK; Counter value after 2sec: %d is within range[%d .. %d]" % (vcxo_count, VCXO_COUNTER_2SEC-VCXO_COUNTER_MARGIN, VCXO_COUNTER_2SEC+VCXO_COUNTER_MARGIN)
inf.write("%s\n" % (msg))
else:
msg = "ERROR: VCXO OSC3: Wrong frequency; Counter value after 2sec: %d out of range[%d .. %d]" % (vcxo_count, VCXO_COUNTER_2SEC-VCXO_COUNTER_MARGIN, VCXO_COUNTER_2SEC+VCXO_COUNTER_MARGIN)
pel.set(msg)
if (pll125_count > (PLL_COUNTER_2SEC-PLL_COUNTER_MARGIN)) and (pll125_count < (PLL_COUNTER_2SEC+PLL_COUNTER_MARGIN)):
msg = "PLL IC29: Frequency OK; Counter value after 2sec: %d is within range[%d .. %d]" % (pll125_count, PLL_COUNTER_2SEC-PLL_COUNTER_MARGIN, PLL_COUNTER_2SEC+PLL_COUNTER_MARGIN)
inf.write("%s\n" % (msg))
else:
msg = "ERROR: PLL IC29: Wrong frequency; Counter value after 2sec: %d out of range[%d .. %d]" % (pll125_count, PLL_COUNTER_2SEC-PLL_COUNTER_MARGIN, PLL_COUNTER_2SEC+PLL_COUNTER_MARGIN)
pel.set(msg)
inf.write("\n")
# Evaluating the VCXO and PLL influence from DAC
for i in range(len(dac_volts)):
grad = vcxo[i] / dac_volts[i]
if i > 0:
diff = grad - ograd
if diff < 0:
inf.write("VCXO OSC3: Frequency responds to change in DAC IC52 OK. DAC=%3.2fV\n" % (dac_volts[i]))
else:
msg = "ERROR: VCXO OSC3: Frequency not responding to change in DAC IC52 control value"
pel.set(msg)
ograd = grad
inf.write("\n")
for i in range(len(dac_volts)):
grad = pll125[i] / dac_volts[i]
if i > 0:
diff = grad - ograd
if diff < 0:
inf.write("PLL IC29: Frequency responds to change in DAC IC53 OK. DAC=%3.2fV\n" % (dac_volts[i]))
else:
msg = "ERROR: PLL IC29: Frequency not responding to change in DAC IC53 control value"
pel.set(msg)
ograd = grad
inf.write("\n")
# Set DAC_VCXO to mid-oscillator range (1.65 V)
dac_vcxo_spi = COpenCoresSPI(bus, VCXO_DAC_BASE, 0x014) # divider=0x014: SCLK would be 5 MHz
dac = DAC_AD5662(dac_vcxo_spi)
dac.operation_mode(dac.OM_NORMAL)
dac.set_dac_voltage(1.65)
dac.update_output()
# Set DAC_PLL to mid-oscillator range (1.65 V)
dac_pll_spi = COpenCoresSPI(bus, PLL_DAC_BASE, 0x014) # divider=0x014: SCLK woulb be 5 MHz
dac = DAC_AD5662(dac_pll_spi)
dac.operation_mode(dac.OM_NORMAL)
dac.set_dac_voltage(1.65)
dac.update_output()
return pel.get()
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/flashtest.py 0000664 0000000 0000000 00000020534 12432353720 0026576 0 ustar 00root root 0000000 0000000 ##_______________________________________________________________________________________________
##
## CONV-TTL-RS485 PTS
##
## CERN,BE/CO-HT
##_______________________________________________________________________________________________
##
##-----------------------------------------------------------------------------------------------
##
## CONV-TTL-RS485 flash test
##
##-----------------------------------------------------------------------------------------------
##
## Description This test checks that the release and golden gatewares downloaded to the FPGA are
## the proper version. A gateware download is performed by pts.py prior to this
## script being run. This script is then run to check that the release gateware the
## FPGA boots up to is the correct version. MultiBoot is then performed via the FPGA
## gateware and the gateware version of the golden gateware is checked for
## correctness.
##
##
## Authors Julian Lewis (Julian.Lewis@cern.ch)
## Theodor-Adrian Stana (t.stana@cern.ch)
## Website http://www.ohwr.org/projects/pts
## Date 05/11/2014
##-----------------------------------------------------------------------------------------------
##
##------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
sys.path.append("log/")
import time
import os, errno, re, sys, struct
import os.path
import traceback
import glob
import binascii
# Import common modules
from ctypes import *
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus,tname,inf,log):
"""
tests : Flash chip IC62
uses : golden-v0.0_release-v1.0.bin and flashtest.py
"""
GWVERS_RELEASE = 1.0
GWVERS_GOLDEN = 0.0
# Set the precision of gateware versions based on the number of digits the
# fractional part thereof has; this is done to avoid exceptions in the
# printing to file below
#
# gwvers can be between 0.0 to 15.15 (four bits major, four bits minor)
r = GWVERS_RELEASE - int(GWVERS_RELEASE)
r *= 100
r = int(r)
pr = 1
if (r < 20) and (r >= 10):
pr = 2
g = GWVERS_GOLDEN - int(GWVERS_GOLDEN)
g *= 100
g = int(g)
pg = 1
if (g < 20) and (g >= 10):
pg = 2
pel = PTS_ERROR_LOGGER(inf,log)
try:
# Get board ID and convert it to string
bid = bus.vv_read(0x00)
bid = binascii.unhexlify("%s" % "{0:x}".format(bid))
# and now check if appropriate
if (bid == "T485"):
msg = "Board ID correct: %s\n" % bid
inf.write(msg)
else:
msg = "ERROR: Board ID (%s) incorrect, check IC62" % bid
pel.set(msg)
# Get gateware version and convert it to major-minor float number
gwvers = bus.vv_read(0x04) & 0xff
maj = float(gwvers >> 4)
min = float(gwvers & 0x0f)
if min < 10:
p = 1 # decimal precision for printing below
min /= 10
else:
p = 2 # decimal precision for printing below
min /= 100
gwvers = maj + min
# and now check if appropriate
if (gwvers == GWVERS_RELEASE):
msg = "Release gateware version correct: %2.*f\n" % (p, gwvers)
inf.write(msg)
else:
msg = "ERROR: Release gateware version (%2.*f) incorrect - expected %2.*f" % (p, gwvers, pr, GWVERS_RELEASE)
pel.set(msg)
# Fall-back to golden addres by performing IPROG from wrong address
print("Trying fallback to golden gateware...")
bus.vv_write(0x108, 0x44 | (0x0b << 24))
bus.vv_write(0x10c, 0x180000 | (0x0b << 24)) # release bitstream at 0x170000
bus.vv_write(0x100, 0x10000)
try:
# This write will issue IPROG and an NACK, so we avoid the exception here
bus.vv_write(0x100, 0x20000)
except:
pass
# Try to read out gateware version and time out after 60 seconds
t0 = time.time()
t1 = t0 + 60
while (1):
try:
if (time.time() >= t1):
msg = "ERROR: Timeout, fallback unsuccessful"
print msg
pel.set(msg)
break
# Get board ID and convert it to string
bid = bus.vv_read(0x00)
bid = binascii.unhexlify("%s" % "{0:x}".format(bid))
# and now check if appropriate
if (bid == "T485"):
msg = "Board ID correct: %s\n" % bid
inf.write(msg)
else:
msg = "ERROR: Board ID (%s) incorrect, check IC62" % bid
pel.set(msg)
# Read gateware version after fall-back
gwvers = bus.vv_read(0x04) & 0xff
maj = float(gwvers >> 4)
min = float(gwvers & 0x0f)
if min < 10:
p = 1 # decimal precision for printing below
min /= 10
else:
p = 2 # decimal precision for printing below
min /= 100
gwvers = maj + min
# and now check if appropriate
if (gwvers == GWVERS_GOLDEN):
msg = "Golden gateware version correct: %2.*f\n" % (p, gwvers)
inf.write(msg)
else:
msg = "ERROR: Golden gateware version (%2.*f) incorrect - expected %2.*f" % (p, gwvers, pg, GWVERS_GOLDEN)
pel.set(msg)
# FPGA up from booting, end the loop
break
except BusException:
continue
return pel.get()
except BusException, e:
raise PtsError("SKT Exception: %s" % (e))
except BusWarning, e:
raise PtsError("SKT Warning: %s" % (e))
if __name__ == '__main__':
bus = SKT(ELMASLOT)
os.chdir("log")
logname = glob.glob('*.log')
infname = glob.glob('*.inf')
log = open(logname[0],'a')
inf = open(infname[0],'a')
msg = "Run:1 Begin: test08"
print msg
log.write(msg + '\n')
inf.write(msg + '\n')
try:
print main.__doc__
ret = main(bus, 'test08', inf, log)
if (ret == 0):
msg = "PASS: test08"
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
else:
msg = "FAIL: test08->flashtest.py\n"
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
except Exception as e:
msg = "FAIL: test08->flashtest.py (%s)" % e
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
msg = "Run:1 End: test08"
print msg
log.write(msg + '\n')
inf.write(msg + '\n')
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/jpts.py 0000775 0000000 0000000 00000025267 12432353720 0025574 0 ustar 00root root 0000000 0000000 #! /usr/bin/python
# coding: utf8
##________________________________________________________________________________________________
##
## CONV-TTL-RS485 PTS
##
## CERN,BE/CO-HT
##________________________________________________________________________________________________
##
##------------------------------------------------------------------------------------------------
##
## CONV-TTL-RS485 test sequencer
##
##------------------------------------------------------------------------------------------------
##
## Description This module gets called by the main PTS module (pts.py) to run the tests defined
## via the make-links.bat script. The tests are listed within this script and symlinks
## are created to point to the actual Pyton programs running the tests.
##
## The task of this module is to run these Python programs in a sequence and print the
## test results to output files.
##
## Two types of output files exist for this purpose. The first is the log file (.log),
## which contains brief information, PASS/FAIL for each test. The second, the info
## file (.inf) contains more detailed information, listing the steps the test takes
## and the reasons for which the test failed (if it failed).
##
## Authors Julian Lewis (Julian.Lewis@cern.ch)
## Theodor Stana (t.stana@cern.ch)
## Website http://www.ohwr.org/projects/conv-ttl-rs485
## Date 30/10/2014
##-------------------------------------------------------------------------------------------------
##
##-------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-------------------------------------------------------------------------------------------------
##------------------------------------------------------------------------------------------------
## Import
##------------------------------------------------------------------------------------------------
import sys
sys.path.append('.')
sys.path.append("pyts")
import ptsexcept
import ptsdefine
import time
import traceback
import socket
from optparse import OptionParser
from vv_pts import *
from os import path, access, R_OK, readlink
##-------------------------------------------------------------------------------------------------
## Method to get the test program a symlink points to
##-------------------------------------------------------------------------------------------------
def lnk_ptr(tname):
lname = "./%s.py" % (tname)
if path.islink(lname):
return readlink(lname)
else:
return tname
##-------------------------------------------------------------------------------------------------
## Method to run the test
##-------------------------------------------------------------------------------------------------
def run_test(tname,bus,inf,log):
# Each test should have a main function in it running the necessary steps
# to run. Here we import the name of the test and run the main function,
# printing the docstring at the beginning of this function.
#
# The number of errors returned by the test's main function is returned
# by this function to the JPTS program.
try:
mod = __import__(tname)
msg = mod.main.__doc__
print msg
log.write("%s\n" % (msg))
inf.write("%s\n" % (msg))
time.sleep(1)
return mod.main(bus,tname,inf,log)
except PtsError, e:
msg = "%s %s->%s\n" % (e, tname, lnk_ptr(tname))
print "ABORT: %s" % (msg)
inf.write(msg)
log.write(msg)
return 1
##-------------------------------------------------------------------------------------------------
## Main "method" of JPTS
##-------------------------------------------------------------------------------------------------
if __name__ == '__main__':
# Print usage information
use = "Usage: %prog [--lun=0 --snum=1234 5678 --debug] test_num,run_count test_num,run_count..."
parser = OptionParser(usage=use, version="pts version 2.0")
parser.add_option("-l", "--lun", help="Logical Unit Number", type="int", default=ELMASLOT, dest="lun")
parser.add_option("-s", "--snum", help="Serial number(s)", dest="snum", action="store", nargs=2, default=("0","0"))
parser.add_option("-n", "--name", help="Board name", dest="board_name", default="ttlbl")
parser.add_option("-b", "--bus", help="Bus VME/PCI/SKT", dest="bus_type", default="SKT")
parser.add_option("-o", "--outdir", help="Path to log directory", dest="dir_name", default=".")
parser.add_option("-d", "--debug", help="Debug Option", dest="debug", default=False, action="store_true")
options, args = parser.parse_args()
# Print further information if in debug mode
if options.debug:
print "\n"
print "options (Logical Unit Number) lun :%d" % options.lun
print "options (Serial numbers pair) snum :%s %s" % options.snum
print "options (Board name ) name :%s" % options.board_name
print "options (Bus VME PCI or SKT ) bus :%s" % options.bus_type
print "options (Location of log dir) outdir:%s" % options.dir_name
print "options (Debug printing flag) debug :%d" % options.debug
print "arglist (List: Test,RunCount) :%s" % (args)
# Create test array from existing test links
tns = []
if len(args):
for a in args:
nstr = a.split(',')
tn = int(nstr[0])
if len(nstr) == 2:
tc = int(nstr[1])
else:
tc = 1
tns.append((tn,tc))
else:
for a in range(19):
tns.append((a,1))
# Get logical unit number, serial numbers, board name, log file dir from command line args
# and create path strings for log and info files
lun = options.lun
sno, xno = options.snum
bnm = options.board_name
dir = options.dir_name
now = time.asctime(time.localtime(time.time()))
now = now.replace(" ","-")
now = now.replace(":","-")
lgf = "%s/log/%s-%s-%s-%s-%1d.log" % (dir,bnm,sno,xno,now,lun)
inf = "%s/log/%s-%s-%s-%s-%1d.inf" % (dir,bnm,sno,xno,now,lun)
# Open the log and info files
try:
log = open(lgf, "w")
inf = open(inf, "w")
except Exception, e:
msg = "Exception: %s" % (e)
print "Fatal: %s" % (msg)
sys.exit(1)
# and print them to console if in debug mode
if options.debug:
print "\n"
print "Log file is: %s" % lgf
print "Inf file is: %s" % inf
print "\n"
# Open up a bus object, can be one of following (depending on tested device):
# * VME -- VME board (SVEC, etc.)
# * PCI -- PCI board (SPEC, etc.)
# * SKT -- board connecting through I2C lines on VME backplane (CONV-TTL-BLO, etc.)
try:
if options.bus_type == "VME":
bus = VME(lun)
elif options.bus_type == "PCI":
bus = PCI(lun)
else:
bus = SKT(lun)
bus.vv_init()
except BusException, e:
print "Fatal:BUS Exception: %s" % (e)
except BusWarning, e:
print "Warning:Bus Exception: %s" % (e)
# Start running the tests.
for t in tns:
tname = "test%02d" % t[0]
pyt = "%s/%s.py" % (dir, tname)
if path.exists(pyt) and path.isfile(pyt) and access(pyt, R_OK):
for n in range(t[1]):
if n == 10:
msg = "Printing suppresses after 10 runs"
print msg
log.write('\n' + msg + '\n')
inf.write('\n' + msg + '\n')
if n < 10:
msg = "Run:%d Begin:%s" % (n+1,tname)
print msg
log.write('\n' + msg + '\n')
inf.write('\n' + msg + '\n')
try:
# First load a firmware and read back a register to confirm correct load.
if bus.vv_load() == 0:
msg = "INFO: Found CONV-TTL-RS485 board in slot %d\n" % (lun)
inf.write(msg + '\n')
# Each test is passed the test name, the log and info files and the
# bus object. The test program is expected to return the number of
# errors that occured. If no errors occur, the test PASSes, otherwise
# it FAILs.
cc = run_test(tname,bus,inf,log)
if cc == 0:
msg = "PASS: %s" % (tname)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
else:
msg = "FAIL: %s->%s" % (tname, lnk_ptr(tname))
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
except Exception, e:
if options.debug:
print e
traceback.print_exc()
msg = "FAIL: %s->%s (%s)" % (tname, lnk_ptr(tname), e)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
if n < 10:
msg = "Run:%d End:%s\n" % (n+1,tname)
print msg
log.write(msg + '\n')
inf.write(msg + '\n')
# Close the bus and the files
bus.vv_close()
log.close()
inf.close()
# Print info file to console if in debug mode
if options.debug:
print "Debug: printing:%s" % (inf)
inf = open(inf, "r")
try:
for line in inf:
l = line.split("\n")
print "%s" % l[0]
finally:
inf.close()
sys.exit(0)
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/leds.py 0000664 0000000 0000000 00000012164 12432353720 0025530 0 ustar 00root root 0000000 0000000 ##_______________________________________________________________________________________________
##
## CONV-TTL-RS485 PTS
##
## CERN,BE/CO-HT
##_______________________________________________________________________________________________
##
##-----------------------------------------------------------------------------------------------
##
## CONV-TTL-RS485 LEDs test
##
##-----------------------------------------------------------------------------------------------
##
## Description Testing of the Front Panel status LEDs (IC1 and bi-color LEDs) and pulse
## LEDs (IC5 and channel LEDs) of the CONV-TTL-BLO board.
##
## For this test, the operator's intervention is needed; when prompted, the operator
## needs to visually check the LEDS.
##
## The FPGA gateware sequences through each of the front panel LEDs (pulse LEDs
## status LEDs) based on the value of the current test field in the PTS control
## register. In order to start and stop LED sequencing, the test sets and clears
## control bits in the PTS CSR.
##
## Authors Julian Lewis (Julian.Lewis@cern.ch)
## Theodor-Adrian Stana (t.stana@cern.ch)
## Website http://www.ohwr.org/projects/pts
## Date 30/10/2014
##-----------------------------------------------------------------------------------------------
##
##------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
import time
import os, errno, re, sys, struct
import os.path
import traceback
# Import common modules
from ctypes import *
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus,tname,inf,log):
"""
tests : Front Panel LEDs, bicolor LEDs with transceiver IC1
uses : pts.bit and leds.py
"""
pel = PTS_ERROR_LOGGER(inf,log)
try:
# First phase of LED test, enable pulse LED sequencing
val = bus.vv_read(CSR)
val |= (1 << CSR_FRONT_LED_EN_OFS)
bus.vv_write(CSR, val)
# The gateware should blink the LEDs, ask the operator for input
inp = raw_input("--> Are the channel LEDs blinking one by one? yes/no: ")
while True:
if inp.find("yes") != -1 or inp.find("YES") != -1:
break
if inp.find("no") != -1 or inp.find("NO") != -1:
msg = "ERROR: Front Panel LEDs"
pel.set(msg)
break
inp = raw_input('Please type "yes" or "no" to continue: ')
# Second phase of LED test, enable status LED sequencing
val &= ~(1 << CSR_FRONT_LED_EN_OFS)
val |= 1 << CSR_STAT_LED_EN_OFS
bus.vv_write(CSR, val)
# The gateware should blink the LEDs, ask the operator for input
inp = raw_input("--> Are the status LEDs blinking one by one? yes/no: ")
while True:
if inp.find("yes") != -1 or inp.find("YES") != -1:
break
if inp.find("no") != -1 or inp.find("NO") != -1:
msg = "ERROR: Status LEDs or transceiver IC1"
pel.set(msg)
break
inp = raw_input('Please type "yes" or "no" to continue: ')
return pel.get()
except BusException, e:
raise PtsError("SKT Exception: %s" % (e))
except BusWarning, e:
raise PtsError("SKT Warning: %s" % (e))
finally:
# Clean-up -- clear status and front LED test bits
val = bus.vv_read(CSR)
val &= ~((1 << CSR_FRONT_LED_EN_OFS) | (1 << CSR_STAT_LED_EN_OFS))
bus.vv_write(CSR, val)
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/pts.py 0000775 0000000 0000000 00000025230 12432353720 0025410 0 ustar 00root root 0000000 0000000 #! /usr/bin/python
# coding: utf8
##________________________________________________________________________________________________
##
## CONV-TTL-RS485 PTS
##
## CERN,BE/CO-HT
##________________________________________________________________________________________________
##
##------------------------------------------------------------------------------------------------
##
## CONV-TTL-RS485 PTS main program
##
##------------------------------------------------------------------------------------------------
##
## Description This is the main program of the PTS suite. It is the high-level program of the
## suite, running scripts to turn the test system on and off and downloading bitfiles
## to the DUT FPGA(s) before finally running the test programs. This latter part is
## handled by JPTS (jpts.py), a Python program that cycles through the various tests
## to be performed and writes results to log (.log) and info (.inf) files.
##
## Each board has a barcode associated to it, which can be either read via a barcode
## reader device, or manually input by the user from a keyboard. The barcode is used
## as part of the output file names to identify a DUT board.
##
## The program begins by asking for this barcode and downloading a bitstream to the
## FPGA once the board has been plugged in. Then, JPTS gets called in an external
## shell to run the tests defined for a board's PTS.
##
## After the tests have finished running, the log and info files get stored to a USB
## stick provided with the test system.
##
## Authors Julian Lewis (Julian.Lewis@cern.ch)
## Theodor Stana (t.stana@cern.ch)
## Website http://www.ohwr.org/projects/conv-ttl-rs485
## Date 30/10/2014
##-------------------------------------------------------------------------------------------------
##
##-------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import
##-------------------------------------------------------------------------------------------------
import sys
sys.path.append('.')
sys.path.append("pyts")
import time
import traceback
import os
import subprocess
import re
# Import ptsdefine module to avoid wrong `make's
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## Method to turn on the ELMA crate.
##-------------------------------------------------------------------------------------------------
## It calls the get-fan-speeds script to check if the crate is on.
##-------------------------------------------------------------------------------------------------
def men_is_on():
on = 0
subprocess.call("cd shell; ./get-fan-speeds", shell=True, stdout=fnull, stderr=fnull)
btxt = tuple(open("log/fan-speeds","r"))
for i in range(1,len(btxt)):
if btxt[i].find("INTEGER: 0") == -1:
on = on + 1
return on
##-------------------------------------------------------------------------------------------------
## Method to turn on the VME crate.
##-------------------------------------------------------------------------------------------------
## It calls the men-on script which sends the necessary SMTP commands to the ELMA crate to turn on
## power to the VME backplane.
##-------------------------------------------------------------------------------------------------
def men_on():
tmo = 1
while men_is_on() == 0:
print "Try:%d Switching ON the VME Crate" % (tmo)
subprocess.call("shell/men-on", shell=True, stdout=fnull, stderr=fnull)
tmo = tmo + 1
if tmo > 10:
print "FATAL ERROR: VME Crate: Unable to switch ON"
sys.exit(1)
time.sleep(1)
##-------------------------------------------------------------------------------------------------
## Method to turn off the VME crate.
##-------------------------------------------------------------------------------------------------
## It calls the men-off script which sends the necessary SMTP commands to the ELMA crate to turn off
## power to the VME backplane.
##-------------------------------------------------------------------------------------------------
def men_off():
tmo = 1
while men_is_on() != 0:
print "Try:%d Switching OFF the VME Crate" % (tmo)
subprocess.call("shell/men-off", shell=True, stdout=fnull, stderr=fnull)
tmo = tmo + 1
if tmo > 10:
print "FATAL ERROR: VME Crate: Unable to switch OFF"
sys.exit(1)
time.sleep(1)
##-------------------------------------------------------------------------------------------------
## Main "method" of PTS
##-------------------------------------------------------------------------------------------------
if __name__ == '__main__':
print "\nHello and Welcome to the CONV-TTL-RS485 PTS!\n"
# Open NULL File and turn the crate off
fnull = open(os.devnull, "w")
# Clear the log dir (if any) and (re-)create it to store log and info files
subprocess.call("rm -rf ./log; mkdir log; chmod 777 log", shell=True, stdout=fnull, stderr=fnull)
men_off()
# Scan the first barcode
while True:
sn1 = raw_input("--> Scan the 1st barcode: ")
m = re.search(r"[^a-z\-A-Z0-9_]+",sn1)
if m:
print "Bad character in barcode"
else:
break
# Scan the second barcode
while True:
sn2 = raw_input("--> Scan the 2nd barcode: ")
if len(sn2) > 2:
m = re.search(r"[^a-z\-A-Z0-9_]+",sn2)
if m:
print "Bad character in barcode"
else:
break
else:
sn2 = "0"
break
# Ask the user to plug in the board, turn on the crate and call the script to download bitstream
# to FPGA
msg = "\n--> Plug the CONV-TTL-RS485 board '%s-%s' into the VME crate.\n Then type 'ok': " % (sn1, sn2)
ok = raw_input(msg)
while True:
if ok.find("ok") != -1 or ok.find("OK") != -1:
break
else:
ok = raw_input("--> Please type 'ok' to continue: ")
print "\n"
men_on()
print "Loading FPGA bitstream..."
ret = subprocess.call("cd boot; ./program", shell=True, stdout=fnull, stderr=fnull)
time.sleep(1)
if (ret != 0):
print "ERROR: Bitstream download fail. Check JTAG connectivity."
else:
# Run JPTS in another shell script; JPTS will handle running each of the test scripts
cmd = "xterm -e ./jpts -s %s %s" % (sn1, sn2)
print "Running tests :%s\n" % (cmd)
subprocess.call(cmd, shell=True, stdout=fnull, stderr=fnull)
ret = subprocess.call("grep FAIL log/*.log", shell=True, stdout=fnull, stderr=fnull)
if (ret == 0):
print "Errors in tests, not downloading release bitstream"
print ""
else:
# After JPTS has finished, download release bitstream to EEPROM chip if none of the tests has failed
print "Loading CONV-TTL-RS485 golden and release bitstream...\n"
ret = subprocess.call("cd boot; ./flash", shell=True, stdout=fnull, stderr=fnull)
if (ret != 0):
print "ERROR: Bitstream download failed"
else:
time.sleep(1)
# ... power-cycle the crate
print "VME crate power-cycle..."
men_off()
time.sleep(5)
men_on()
time.sleep(5)
# .. and run the flash test
cmd = "xterm -e python ./flashtest.py"
subprocess.call(cmd, shell=True, stdout=fnull, stderr=fnull)
# After all testing has finished, grep the log files for PASS and FAIL messages and print the outcomes to the console
subprocess.call("grep PASS log/*.log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("grep FAIL log/*.log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
# Save results on USB key...
print "\nSaving test results on USB key"
try:
subprocess.call("mkdir -p /media/pts/log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("cp log/*.log /media/pts/log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("cp log/*.inf /media/pts/log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
except e:
print "ERROR: No access to USB key at /media/pts"
print e
# We're done, turn off the VME crate
print "\nTesting completed!"
men_off()
# Finally, print anything that went wrong throughout the test programs by grepping the log and info files and
# exit when the user desires.
msg = "\n--> To see all the PTS errors, type 'ok': "
ok = raw_input(msg)
if ok.find("ok") != -1:
subprocess.call("grep FAIL log/*.log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("grep ERROR log/*.inf", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("grep WARNING log/*.inf", shell=True, stdout=sys.stdout, stderr=sys.stderr)
print ""
print "--> You may now unplug the CONV-TTL-RS485 board %s-%s\n" % (sn1, sn2)
msg = "--> To exit PTS, type 'ok': "
ok = raw_input(msg)
while True:
if ok.find("ok") != -1 or ok.find("OK") != -1:
print "Exited PTS"
time.sleep(1)
sys.exit(1)
else:
ok = raw_input("--> To exit PTS, type 'ok': ")
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/ptsdefine.py 0000664 0000000 0000000 00000006433 12432353720 0026564 0 ustar 00root root 0000000 0000000 #===============================================================================
# CERN (BE-CO-HT)
# PTS definitions file
#===============================================================================
# author: Theodor Stana (t.stana@cern.ch)
#
# date of creation: 2013-10-31
#
# version: 1.0
#
# description:
# This module contains register address definitions that are used across the
# various tests. Importing this module inside a test script makes these
# definitions available for use within a bus.vv_write or bus.vv_read method
# (see vv_pts.py for these methods).
#
# dependencies:
# none.
#
# references:
# none.
#
#===============================================================================
# GNU LESSER GENERAL PUBLIC LICENSE
#===============================================================================
# This source file is free software; you can redistribute it and/or modify it
# under the terms of the GNU Lesser General Public License as published by the
# Free Software Foundation; either version 2.1 of the License, or (at your
# option) any later version. This source is distributed in the hope that it
# will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
# See the GNU Lesser General Public License for more details. You should have
# received a copy of the GNU Lesser General Public License along with this
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#===============================================================================
# last changes:
# 2014-10-31 Theodor Stana t.stana@cern.ch File created
#===============================================================================
# TODO: -
#===============================================================================
# ELMA crate definitions
ELMAIP = ""
ELMAPWD = ""
ELMASLOT =
# Board ID register
BIDR = 0x000
BIDR_ARR = [ "TBLO", "T485" ]
# Control and Status Register
CSR = 0x004
CSR_FRONT_LED_EN_OFS = 0
CSR_REAR_LED_EN_OFS = 1
CSR_STAT_LED_EN_OFS = 2
CSR_TTL_EN_OFS = 3
CSR_REAR_EN_OFS = 4
CSR_TESTER_VCC_OFS = 5
CSR_TESTER_MUX_EN_OFS = 6
CSR_TESTER_MUX_S0_OFS = 7
CSR_TESTER_MUX_S1_OFS = 8
CSR_RST_UNLOCK_OFS = 14
CSR_RST_OFS = 15
CSR_SWITCHES_OFS = 16
CSR_RTM_OFS = 24
CSR_I2C_ERR_OFS = 30
CSR_I2C_WDTO_OFS = 31
# Line Status Register
LSR = 0x008
LSR_FRONT_OFS = 0
LSR_FRONTINV_OFS = 6
LSR_REAR_OFS = 10
LSR_REARFS_OFS = 26
# Termination Enable Register
TER = 0x00c
TER_ITERM_OFS = 0
TER_OTERM_OFS = 6
# 1-Wire base address, used in therm_id.py
TEMP_1WIRE_BASE = 0x010
# DAC and clock info registers and offsets, used in dac_vcxo_pll.py
PLL_DAC_BASE = 0X020
VCXO_DAC_BASE = 0x080
PLL_CLKINFO_BASE = 0x100
VCXO_CLKINFO_BASE = 0x120
CLKINFO_RST_OFS = 0x014
CLKINFO_ENABLE_OFS = 0x018
CLKINFO_VALUE_OFS = 0x010
# SFP I2C master base address, used in sfp_eeprom.py
SFP_EEPROM_BASE = 0x140
# SFP endpoint, miniNIC and buffer RAM base addresses and offsets,
# used in sfp_test.py
SFP_BASE = 0x200
SFP_ENDPOINT_OFS = 0x000
SFP_MINIC_OFS = 0x200
SFP_DPRAM_OFS = 0x600
# Pulse counter base address
PULSE_CNT_BASE = 0xc00
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/ptsexcept.py 0000664 0000000 0000000 00000002255 12432353720 0026620 0 ustar 00root root 0000000 0000000 class PtsException(Exception):
pass
class PtsCritical(PtsException):
"""critical error, abort the whole test suite"""
pass
class PtsUser(PtsException):
"""error, user intervention required"""
pass
class PtsWarning(PtsException):
"""warning, a cautionary message should be displayed"""
pass
class PtsInvalid(PtsException):
"""reserved: invalid parameters"""
class PtsNoBatch(PtsInvalid):
"""reserved: a suite was created without batch of tests to run"""
pass
class PtsBadTestNo(PtsInvalid):
"""reserved: a bad test number was given"""
pass
class PtsInfo(PtsException):
"""Information from the test, not an error"""
class PtsError(PtsException):
"""error, continue remaining tests in test suite"""
pass
class PTS_ERROR_LOGGER:
"""Log errors and continue testing without raising an exception"""
def __init__(self, inf, log):
self.inf = inf
self.log = log
self.er_count = 0
def set(self, msg):
self.inf.write(msg + "\n")
self.log.write(msg + "\n")
self.er_count = self.er_count + 1
def get(self):
return self.er_count
if __name__ == '__main__':
pass
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/rs485_pulse_rtm.py 0000664 0000000 0000000 00000022504 12432353720 0027557 0 ustar 00root root 0000000 0000000 # Import system modules
import sys
import time
# Import common modules
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
class CPulseCounter:
def __init__(self, bus, base):
self.bus = bus
self.base = base
def wr_reg(self, addr, val):
self.bus.vv_write(self.base + addr,val)
def rd_reg(self, addr):
return self.bus.vv_read(self.base + addr)
def wr_out_cnt(self, chan, val):
return self.wr_reg((chan-1)*8, val)
def wr_in_cnt(self, chan, val):
return self.wr_reg((chan-1)*8 + 4, val)
def rd_out_cnt(self, chan):
return self.rd_reg((chan-1)*8)
def rd_in_cnt(self, chan):
return self.rd_reg((chan-1)*8 + 4)
def mux_sel(bus, sel):
val = bus.vv_read(CSR)
val &= ~(1 << CSR_TESTER_MUX_S0_OFS)
val &= ~(1 << CSR_TESTER_MUX_S1_OFS)
if (sel & 0x1):
val |= (1 << CSR_TESTER_MUX_S0_OFS)
if (sel & 0x2):
val |= (1 << CSR_TESTER_MUX_S1_OFS)
bus.vv_write(CSR, val)
def en_pulse_gen(bus):
val = bus.vv_read(CSR)
val |= (1 << CSR_REAR_EN_OFS)
bus.vv_write(CSR, val)
def dis_pulse_gen(bus):
val = bus.vv_read(CSR)
val &= ~(1 << CSR_REAR_EN_OFS)
bus.vv_write(CSR, val)
def clear_counters(pc):
# Clear pulse counters for the TTL channels
for i in range(11, 17):
pc.wr_out_cnt(i, 0)
pc.wr_in_cnt(i, 0)
def check_counters(pc, inf, pel):
ic_arr = []
oc_arr = []
for i in range(11, 17):
ic_arr.append(pc.rd_in_cnt(i))
oc_arr.append(pc.rd_out_cnt(i))
for i in range(len(ic_arr)):
if (ic_arr[i] == oc_arr[i]):
msg = "Ch%d input counter (%d) matches the output counter (%d) - good\n" % (i+1,
ic_arr[i], oc_arr[i])
inf.write(msg)
else:
msg = "ERROR: Ch%d input counter (%d) does not match output counter (%d)"% (i+1,
ic_arr[i], oc_arr[i])
pel.set(msg)
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus, tname, inf, log):
"""
tests : RS-485 pulse repetition, RS-485 transceivers IC31-IC56,
solid-state switches IC56-IC75, solid-state switches
IC23-IC28, RS-485 transceivers IC16-IC21, Schmitt trigger
inputs IC30, IC45, NAND gate IC8, IC69 Schmitt trigger for
the RTM detection lines
uses : pts.bit and rs485_pulse_rtm.py
"""
pel = PTS_ERROR_LOGGER(inf, log)
try:
# Read RTM lines
rtm = (bus.vv_read(CSR) >> CSR_RTM_OFS) & 0x3f
if (rtm == 0x09):
msg = "RTM detection lines read correctly: 0x%02X" % rtm
inf.write(msg+'\n')
else:
msg = "ERROR: RTM detection lines readout (0x%02X) incorrect - expected 0x09. Check RTM presence or IC69" % rtm
pel.set(msg)
return pel.get()
# Initialize a pulse counter object
pc = CPulseCounter(bus, PULSE_CNT_BASE)
clear_counters(pc)
# Ask the user to make the daisy-chain
print("Connect the LEMO cable as follows:")
print(" - BLU cable to INV-TTL CH A")
print(" - GRN cable to INV-TTL CH B")
print(" - RED cable to INV-TTL CH C")
print(" - YEL cable to INV-TTL CH D")
reply = raw_input("Have the connections been made? (yes/no) ")
while (1):
if "yes" in reply.lower():
break
if "no" in reply.lower():
msg = "ERROR: Control connections to RS485 tester not made"
pel.set(msg)
return pel.get()
else:
reply = raw_input('Please type "yes" or "no" to continue: ')
# Power on the tester card
val = bus.vv_read(CSR)
val |= (1 << CSR_TESTER_VCC_OFS)
bus.vv_write(CSR, val)
#---------------------------
# Test with terminations OFF
#---------------------------
# Read out fail-safe lines -- should now be high, since the MUXes are
# powered but not enabled
val = bus.vv_read(LSR)
val >>= LSR_REARFS_OFS
if (val == 0x3f):
msg = "RS-485 failsafe lines read as expected: 0x%02X\n" % val
inf.write(msg)
else:
msg = "ERROR: Failsafe lines readout (0x%02X) incorrect - expected 0x3F" % val
pel.set(msg)
# Enable multiplexer
print("Enabling multiplexers")
val = bus.vv_read(CSR)
val |= (1 << CSR_TESTER_MUX_EN_OFS)
bus.vv_write(CSR, val)
# Generate pulses from different outputs to inputs
msg = "Testing channel connections (term. OFF): O1 -> I"
print(msg)
mux_sel(bus, 0x0)
inf.write('\n')
inf.write(msg+'\n')
en_pulse_gen(bus)
time.sleep(2)
dis_pulse_gen(bus)
check_counters(pc, inf, pel)
clear_counters(pc)
msg = "Testing channel connections (term. OFF): O2 -> I"
print(msg)
mux_sel(bus, 0x1)
inf.write('\n')
inf.write(msg+'\n')
en_pulse_gen(bus)
time.sleep(2)
dis_pulse_gen(bus)
check_counters(pc, inf, pel)
clear_counters(pc)
msg = "Testing channel connections (term. OFF): O3 -> I"
print(msg)
mux_sel(bus, 0x2)
inf.write('\n')
inf.write(msg+'\n')
en_pulse_gen(bus)
time.sleep(2)
dis_pulse_gen(bus)
check_counters(pc, inf, pel)
clear_counters(pc)
msg = "Testing RS-485 fail-safe on short-circuit case (term. OFF)"
print(msg)
mux_sel(bus, 0x3)
inf.write('\n')
inf.write(msg+'\n')
en_pulse_gen(bus)
val = bus.vv_read(LSR)
val >>= LSR_REARFS_OFS
if (val == 0x3f):
msg = "RS-485 failsafe lines read as expected: 0x%02X\n" % val
inf.write(msg)
else:
msg = "ERROR: Failsafe lines readout (0x%02X) incorrect - expected 0x3F" % val
pel.set(msg)
dis_pulse_gen(bus)
# Disable multiplexer
print("Disabling multiplexers")
val = bus.vv_read(CSR)
val &= ~(1 << CSR_TESTER_MUX_EN_OFS)
bus.vv_write(CSR, val)
#--------------------------
# Test with terminations ON
#--------------------------
# Read out fail-safe lines -- should now be high, since the MUXes are
# powered but not enabled
val = bus.vv_read(LSR)
val >>= LSR_REARFS_OFS
if (val == 0x3f):
msg = "RS-485 failsafe lines read as expected: 0x%02X\n" % val
inf.write(msg)
else:
msg = "ERROR: Failsafe lines readout (0x%02X) incorrect - expected 0x3F" % val
pel.set(msg)
inf.write('\n')
msg = "Enabling input and output terminations"
print(msg)
inf.write(msg + '\n')
bus.vv_write(TER, (0x3f << TER_OTERM_OFS) | (0x3f << TER_ITERM_OFS))
time.sleep(2)
# Enable multiplexer
print("Enabling multiplexers")
val = bus.vv_read(CSR)
val |= (1 << CSR_TESTER_MUX_EN_OFS)
bus.vv_write(CSR, val)
# Generate pulses from different outputs to inputs
msg = "Testing channel connections (term. ON): O1 -> I"
print(msg)
mux_sel(bus, 0x0)
inf.write('\n')
inf.write(msg+'\n')
en_pulse_gen(bus)
time.sleep(2)
dis_pulse_gen(bus)
check_counters(pc, inf, pel)
clear_counters(pc)
msg = "Testing channel connections (term. ON): O2 -> I"
print(msg)
mux_sel(bus, 0x1)
inf.write('\n')
inf.write(msg+'\n')
en_pulse_gen(bus)
time.sleep(2)
dis_pulse_gen(bus)
check_counters(pc, inf, pel)
clear_counters(pc)
msg = "Testing channel connections (term. ON): O3 -> I"
print(msg)
mux_sel(bus, 0x2)
inf.write('\n')
inf.write(msg+'\n')
en_pulse_gen(bus)
time.sleep(2)
dis_pulse_gen(bus)
check_counters(pc, inf, pel)
clear_counters(pc)
msg = "Testing RS-485 fail-safe on short-circuit case (term. ON)"
print(msg)
mux_sel(bus, 0x3)
inf.write('\n')
inf.write(msg+'\n')
en_pulse_gen(bus)
val = bus.vv_read(LSR)
val >>= LSR_REARFS_OFS
if (val == 0x3f):
msg = "RS-485 failsafe lines read as expected: 0x%02X\n" % val
inf.write(msg)
else:
msg = "ERROR: Failsafe lines readout (0x%02X) incorrect - expected 0x3F" % val
pel.set(msg)
dis_pulse_gen(bus)
# Disable multiplexer
print("Disabling multiplexers")
val = bus.vv_read(CSR)
val &= ~(1 << CSR_TESTER_MUX_EN_OFS)
bus.vv_write(CSR, val)
return pel.get()
except BusException, e:
raise PtsError("SKT Exception: %s" % e)
except BusWarning, e:
raise PtsError("SKT Warning: %s" % e)
finally:
val = bus.vv_read(CSR)
val &= ~(1 << CSR_TESTER_VCC_OFS)
val &= ~(1 << CSR_TESTER_MUX_EN_OFS)
val &= ~(1 << CSR_TESTER_MUX_S0_OFS)
val &= ~(1 << CSR_TESTER_MUX_S1_OFS)
bus.vv_write(CSR, val)
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/sfp_eeprom.py 0000664 0000000 0000000 00000017656 12432353720 0026753 0 ustar 00root root 0000000 0000000 ##________________________________________________________________________________________________
##
## CONV-TTL-RS485 PTS
##
## CERN,BE/CO-HT
##________________________________________________________________________________________________
##
##------------------------------------------------------------------------------------------------
##
## CONV-TTL-RS485 SFP EEPROM test
##
##------------------------------------------------------------------------------------------------
##
## Description Testing of the SFP EEPROM chip on the CONV-TTL-RS485 board (SFP J1). The gateware
## loaded to the on-board FPGA implements the interface for the communication
## between the I2C bus on the P1 VME connector and the I2C of the SFP EEPROM; the
## interface is an I2C Wishbone master, running on a 20 MHz system clock.
##
## The I2C Wishbone master can be accessed at base address 0x140.
## The I2C address of the SFP EEPROM is 0x50, predefined in the part number.
##
## The test checks the presence of the SFP connector, reads the connector type and
## verifies the received value.
##
## FW to load pts.bit
## Authors Julian Lewis (Julian.Lewis@cern.ch)
## Theodor-Adrian Stana (t.stana@cern.ch)
## Website http://www.ohwr.org/projects/pts
## Date 15/04/2013
##------------------------------------------------------------------------------------------------
##
##------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
import time
import os
# Import common modules
from ctypes import *
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## I2C class --
##-------------------------------------------------------------------------------------------------
class COpenCoresI2C:
R_PREL = 0x0
R_PREH = 0x4
R_CTR = 0x8
R_TXR = 0xC
R_RXR = 0xC
R_CR = 0x10
R_SR = 0x10
CTR_EN = (1<<7)
CR_STA = (1<<7)
CR_STO = (1<<6)
CR_WR = (1<<4)
CR_RD = (1<<5)
CR_NACK = (1<<3)
SR_RXACK = (1<<7)
SR_TIP = (1<<1)
def scan_bus(self):
for i in range(0,128):
self.wr_reg(self.R_TXR, i<<1);
self.wr_reg(self.R_CR, self.CR_STA | self.CR_WR);
self.wait_busy()
self.wr_reg(self.R_CR, self.CR_STO);
self.wait_busy()
def wr_reg(self, addr, val):
self.bus.vv_write(self.base + addr,val)
def rd_reg(self,addr):
return self.bus.vv_read(self.base + addr)
def __init__(self, bus, base, prescaler):
self.bus = bus;
self.base = base;
self.wr_reg(self.R_CTR, 0);
self.wr_reg(self.R_PREL, (prescaler & 0xff))
self.wr_reg(self.R_PREH, (prescaler >> 8))
self.wr_reg(self.R_CTR, self.CTR_EN);
self.scan_bus()
def wait_busy(self):
tmo = 100
while(self.rd_reg(self.R_SR) & self.SR_TIP):
tmo = tmo -1
if tmo <= 0:
msg = "ERROR: SFP-EEPROM: Not responding"
raise PtsError(msg)
def start(self, addr, write_mode):
addr = addr << 1
if(write_mode == False):
addr = addr | 1;
self.wr_reg(self.R_TXR, addr);
self.wr_reg(self.R_CR, self.CR_STA | self.CR_WR);
self.wait_busy()
if(self.rd_reg(self.R_SR) & self.SR_RXACK):
pass
def write(self, data, last):
self.wr_reg(self.R_TXR, data);
cmd = self.CR_WR;
if(last):
cmd = cmd | self.CR_STO;
self.wr_reg(self.R_CR, cmd);
self.wait_busy();
if(self.rd_reg(self.R_SR) & self.SR_RXACK):
pass
def read(self, last):
cmd = self.CR_RD;
if(last):
cmd = cmd | self.CR_STO | self.CR_NACK;
self.wr_reg(self.R_CR, cmd);
self.wait_busy();
return self.rd_reg(self.R_RXR);
##-------------------------------------------------------------------------------------------------
## EEPROM SFP class --
##-------------------------------------------------------------------------------------------------
class EEPROM_SFP:
def __init__(self, i2c, addr):
self.i2c = i2c;
self.addr = addr;
def wr_reg16(self, addr, value):
self.i2c.start(self.addr, True);
self.i2c.write(addr, False);
tmp = (value >> 8) & 0xFF;
self.i2c.write(value, False);
tmp = value & 0xFF;
self.i2c.write(value, True)
def wr_reg8(self, addr, value):
self.i2c.start(self.addr, True);
self.i2c.write(addr, False);
self.i2c.write(value, True);
def rd_reg16(self, addr):
self.i2c.start(self.addr, True);
self.i2c.write(addr, False);
self.i2c.start(self.addr, False);
tmp_MSB = self.i2c.read(False);
tmp_LSB = self.i2c.read(True);
value = (tmp_MSB << 8) | tmp_LSB;
return value;
def rd_reg8(self, addr):
self.i2c.start(self.addr, True);
self.i2c.write(addr, False);
self.i2c.start(self.addr, False);
return self.i2c.read(True);
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus,tname,inf,log):
"""
tests : SFP J1 EEPROM
uses : pts.bit and sfp_eeprom.py
"""
SFP_EEPROM_I2C_ADDR = 0x50
pel = PTS_ERROR_LOGGER(inf,log)
try:
# Create bus and EEPROM objects
i2c = COpenCoresI2C(bus, SFP_EEPROM_BASE, 39);
eeprom = EEPROM_SFP(i2c, SFP_EEPROM_I2C_ADDR);
# Read SFP I2C identifier value, which should return 0x03 for an SFP or SFP+ connector type
# No other connectors are currently supported
# For more information, see INF-8074 (SFP) and SFF-8472 (SFP+)
type = eeprom.rd_reg8(0x0);
if (type == 0x03):
inf.write("SFP type is correct: 0x%02x\n" % type)
else:
msg = "ERROR: SFP-EEPROM: Wrong connector type (0x%02x) - expected 0x03." % type
pel.set(msg)
return pel.get()
except BusException, e:
raise PtsError("SKT Exception: %s" % (e))
except BusWarning, e:
raise PtsError("SKT Warning: %s" % (e))
#finally:
# return pel.get()
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/sfp_test.py 0000664 0000000 0000000 00000015455 12432353720 0026436 0 ustar 00root root 0000000 0000000 ##________________________________________________________________________________________________
##
## CONV-TTL-RS485 PTS
##
## CERN,BE/CO-HT
##________________________________________________________________________________________________
##
##------------------------------------------------------------------------------------------------
##
## CONV-TTL-RS485 SFP test
##
##------------------------------------------------------------------------------------------------
##
## Description This Python module performs the testing of the MGT module on the CONV-TTL-RS485 FPGA
## and the connections to the small form-factor pluggable (SFP) module.
## For this test the SFP Loopback Adapter Module meeds to be plugged into the SFP
## connector. The idea of the test is to loopback the transmitter and the receiver
## of the link and check if the link is established. Loopback takes place through the
## SFP loopback adapter.
##
## Gateware inside the FPGA implements an endpoint module together with a miniNIC
## module to implement the communication. There are also 16kB of packet RAM available
## to the two modules. The test program views these three components as one, with the
## base address of the unified component as the endpoint's base address.
##
## Thejendpoint module is located at address 0x200 (offset 0x000),
## The miniNIC module is located at address 0x400 (offset 0x200),
## The 16 kB RAM is located at address 0x800 (offset 0x600)
##
## GW to load pts.bit
## Authors Julian Lewis (Julian.Lewis@cern.ch)
## Theodor-Adrian Stana (t.stana@cern.ch)
## Website http://www.ohwr.org/projects/pts
## Date 03/11/2014
##-------------------------------------------------------------------------------------------------
##
##------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##------------------------------------------------------------------------------------------------
##------------------------------------------------------------------------------------------------
## Import
##------------------------------------------------------------------------------------------------
# Import system modules
import ctypes
import sys
import time
import os
import traceback
# Import common modules
from ctypes import *
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## Minic class --
##-------------------------------------------------------------------------------------------------
class CMinic:
EP_REG_ECR = 0x0
EP_REG_MACL = 0x28
EP_REG_MDIO_CR = 0x2c
EP_REG_MDIO_SR = 0x30
EP_REG_IDR = 0x34
EP_MDIO_SR_READY = 0x80000000
EP_ECR_TX_EN = 0x40
EP_ECR_RX_EN = 0x80
MDIO_MCR = 0
MDIO_MSR = 1
MDIO_MCR_PDOWN = (1<<11)
MDIO_MCR_RESET = (1<<15)
MDIO_MSR_LSTATUS = (1<<2)
def __init__(self, bus, base):
self.base = base;
self.bus = bus;
self.init_ep();
def wr_reg(self, addr, val):
self.bus.vv_write(self.base + addr,val)
def rd_reg(self,addr):
return self.bus.vv_read(self.base + addr)
def ep_readl(self, addr):
return self.rd_reg(SFP_ENDPOINT_OFS + addr)
def ep_writel(self, addr, val):
self.wr_reg(SFP_ENDPOINT_OFS + addr, val) # used to be self.PTS_SFP_ENDPO...
def pcs_readl(self, addr):
val = 0
self.ep_writel(self.EP_REG_MDIO_CR, addr << 16);
tmo = 10000
while (val & self.EP_MDIO_SR_READY) == 0:
val = self.ep_readl(self.EP_REG_MDIO_SR)
tmo = tmo -1
if tmo <= 0:
msg = "ERROR: MINIC: Not responding"
raise PtsError(msg)
return (val & 0xffff)
def pcs_writel(self, addr, val):
val = 0
self.ep_writel(self.EP_REG_MDIO_CR, (addr << 16) | (1 << 31) | val);
tmo = 10000
while (val & self.EP_MDIO_SR_READY) == 0:
val = self.ep_readl(self.EP_REG_MDIO_SR)
tmo = tmo -1
if tmo <= 0:
msg = "ERROR: MINIC: Not responding"
raise PtsError(msg)
def init_ep(self):
idr = self.ep_readl(self.EP_REG_IDR)
self.ep_writel(self.EP_REG_ECR, self.EP_ECR_TX_EN | self.EP_ECR_RX_EN)
def reset_phy(self):
self.pcs_writel(self.MDIO_MCR, self.MDIO_MCR_PDOWN);
self.pcs_writel(self.MDIO_MCR, self.MDIO_MCR_RESET);
self.pcs_writel(self.MDIO_MCR, 0);
def link_up(self):
return self.pcs_readl(self.MDIO_MSR) & self.MDIO_MSR_LSTATUS
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus,tname,inf,log):
"""
tests : SFP J1
uses : pts.bit and sfp_test.py
"""
pel = PTS_ERROR_LOGGER(inf,log)
try:
# SFP link test
msg = "Begin SFP link test"
print msg
inf.write("\n%s\n" % (msg))
minic = CMinic(bus, SFP_BASE);
minic.init_ep()
minic.reset_phy()
minic.link_up()
if minic.link_up():
msg = "SFP link up OK"
inf.write("%s\n" % (msg))
else:
msg = "ERROR: SFP high speed link down"
pel.set(msg)
return pel.get()
except BusException, e:
raise PtsError("SKT Exception: %s" % (e))
except BusWarning, e:
raise PtsError("SKT Warning: %s" % (e))
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/therm_id.py 0000664 0000000 0000000 00000024131 12432353720 0026371 0 ustar 00root root 0000000 0000000 ##_______________________________________________________________________________________________
##
## CONV-TTL-RS485 PTS
##
## CERN,BE/CO-HT
##_______________________________________________________________________________________________
##
##------------------------------------------------------------------------------------------------
##
## CONV-TTL-RS485 TEMPID test
##
##------------------------------------------------------------------------------------------------
##
## Description Testing of the DS18B20 thermometer chip (IC22) on the CONV-TTL-RS-485 . The
## gateware loaded to the FPGA implements the interface for the communication between
## the SKT bus and the one wire of the DS18B20; this interface a one wire Wishbone
## master, running on a 20 MHz system clock.
##
## The family code of the DS18B20 is 0x28, predefined in the part number.
##
## The test reads the unique ID and the temperature and checks if the received
## values are within reasonable limits.
##
## Authors Julian Lewis (Julian.Lewis@cern.ch)
## Theodor Stana (t.stana@cern.ch)
## Website http://www.ohwr.org/projects/conv-ttl-rs485
## Date 31/10/2014
##------------------------------------------------------------------------------------------------
##
##------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
import time
import os
# Import common modules
from ctypes import *
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## One Wire class --
##-------------------------------------------------------------------------------------------------
class COpenCoresOneWire:
R_CSR = 0x0
R_CDR = 0x4
CSR_DAT_MSK = (1<<0)
CSR_RST_MSK = (1<<1)
CSR_OVD_MSK = (1<<2)
CSR_CYC_MSK = (1<<3)
CSR_PWR_MSK = (1<<4)
CSR_IRQ_MSK = (1<<6)
CSR_IEN_MSK = (1<<7)
CSR_SEL_OFS = 8
CSR_SEL_MSK = (0xF<<8)
CSR_POWER_OFS = 16
CSR_POWER_MSK = (0xFFFF<<16)
CDR_NOR_MSK = (0xFFFF<<0)
CDR_OVD_OFS = 16
CDR_OVD_MSK = (0XFFFF<<16)
def wr_reg(self, addr, val):
self.bus.vv_write(self.base + addr,val)
def rd_reg(self,addr):
return self.bus.vv_read(self.base + addr)
def __init__(self, bus, base, clk_div_nor, clk_div_ovd):
self.bus = bus
self.base = base
data = ((clk_div_nor & self.CDR_NOR_MSK) | ((clk_div_ovd<>= 1
if (byte_old == data):
return 0
else:
return -1
def write_block(self, port, block):
if (160 < len(block)):
return -1
data = []
for i in range(len(block)):
data.append(self.write_byte(port, block[i]))
return data
def read_block(self, port, length):
if (160 < length):
return -1
data = []
for i in range(length):
data.append(self.read_byte(port))
return data
##-------------------------------------------------------------------------------------------------
## DS18B20 class --
##-------------------------------------------------------------------------------------------------
class CDS18B20:
ROM_SEARCH = 0xF0
ROM_READ = 0x33
ROM_MATCH = 0x55
ROM_SKIP = 0xCC
ROM_ALARM_SEARCH = 0xEC
CONVERT_TEMP = 0x44
WRITE_SCRATCHPAD = 0x4E
READ_SCRATCHPAD = 0xBE
COPY_SCRATCHPAD = 0x48
RECALL_EEPROM = 0xB8
READ_POWER_SUPPLY = 0xB4
def __init__(self, onewire, port):
self.onewire = onewire
self.port = port
def read_serial_number(self):
if (1 != self.onewire.reset(self.port)):
msg = "ERROR: TempID IC22: Not responding"
raise PtsError(msg)
else:
err = self.onewire.write_byte(self.port, self.ROM_READ)
if err != 0:
msg = "ERROR: TempID IC22: Write failed"
raise PtsError(msg)
serial_number = 0
for i in range(8):
serial_number |= self.onewire.read_byte(self.port) << (i*8)
if (self.crc(serial_number)):
msg = "ERROR: TempID IC22: Checksum calculation failed"
raise PtsError(msg)
return serial_number
def access(self, serial_number):
if (1 != self.onewire.reset(self.port)):
msg = "ERROR: TempID IC22: Not responding"
raise PtsError(msg)
else:
err = self.onewire.write_byte(self.port, self.ROM_MATCH)
block = []
for i in range(8):
block.append(serial_number & 0xFF)
serial_number >>= 8
self.onewire.write_block(self.port, block)
return 0
def read_temp(self, serial_number):
err = self.access(serial_number)
err = self.onewire.write_byte(self.port, self.CONVERT_TEMP)
time.sleep(0.8)
err = self.access(serial_number)
err = self.onewire.write_byte(self.port, self.READ_SCRATCHPAD)
data = self.onewire.read_block(self.port, 9)
temp = (data[1] << 8) | (data[0])
if (temp & 0x1000):
temp = -0x10000 + temp
temp = temp/16.0
return temp
def crc(self, val):
ret = 0
for i in range(64):
if ((ret & 0x01) ^ (val & 0x01)):
ret >>= 1
ret ^= 0x8c
else:
ret >>= 1
val >>= 1
return ret
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus,tname,inf,log):
"""
tests : Thermometer IC22 and unique ID
uses : pts.bit and therm_id.py
"""
FAMILY_CODE = 0x28
pel = PTS_ERROR_LOGGER(inf,log)
try:
# Create bus objects
onewire = COpenCoresOneWire(bus, TEMP_1WIRE_BASE, 99, 19)
ds18b20 = CDS18B20(onewire, 0)
# Reading of unique ID
unique_id = ds18b20.read_serial_number()
family_code = unique_id & 0xff
if (unique_id == -1):
msg = "ERROR: TempID IC22: Unable to read 1-wire thermometer"
pel.set(msg)
else:
inf.write("Unique ID: %016X\n" % (unique_id))
# Reading of temperature
temp = ds18b20.read_temp(unique_id)
inf.write("Current temperature: %3.3f\n" % temp)
# Cheking if received values are reasonable
if (temp < 10.0) or (temp > 50.0):
msg = "ERROR: TempID IC22: Temperature: %d out of range[10 .. 50oC]" % (temp)
pel.set(msg)
if (family_code != FAMILY_CODE):
msg = "ERROR: TempID IC22: Invalid family code (0x%02X)\n" % (family_code, FAMILY_CODE)
pel.set(msg)
return pel.get()
except BusException, e:
raise PtsError("SKT Exception: %s" % (e))
except BusWarning, e:
raise PtsError("SKT Warning: %s" % (e))
#finally:
# return pel.get()
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/ttl_pulse_switch.py 0000664 0000000 0000000 00000022661 12432353720 0030200 0 ustar 00root root 0000000 0000000 ##_______________________________________________________________________________________________
##
## CONV-TTL-RS485 PTS
##
## CERN,BE/CO-HT
##_______________________________________________________________________________________________
##
##-----------------------------------------------------------------------------------------------
##
## CONV-TTL-RS485 TTL pulse repetition test
##
##-----------------------------------------------------------------------------------------------
##
## Description This module implements the TTL pulse repetition test. It tests TTL input Schmitt
## triggers IC4 (TTL) and IC9(INV-TTL), along with bus buffers IC2, IC3 and enable
## NAND gate IC8.
##
## There are ten TTL pulse channels this test checks. Six (CH1-6) are TTL
## channels and four (CH6-10) are INV-TTL channels, but the FPGA gateware sends
## TTL pulses on all channels, since the PCB circuits for TTL and INV-TTL channels
## are the same.
##
## Counters are implemented in the gateware to count the number of pulses sent and
## received on a channel. There are two counters per channel, one for input and
## one for output; the counters increment on the rising edge of a pulse signal. The
## current value of each counter can be read via a special Wishbone-mapped slave,
## accessible at base address 0xC00. Below is the full address map for the TTL
## pulse counters:
##
## WB addr Counter
## 0xC00 TTL_CH1_OUT
## 0xC04 TTL_CH1_IN
## 0xC08 TTL_CH2_OUT
## 0xC0C TTL_CH2_IN
## 0xC10 TTL_CH3_OUT
## 0xC14 TTL_CH3_IN
## 0xC18 TTL_CH4_OUT
## 0xC1C TTL_CH4_IN
## 0xC20 TTL_CH5_OUT
## 0xC24 TTL_CH5_IN
## 0xC28 TTL_CH6_OUT
## 0xC2C TTL_CH6_IN
## 0xC30 TTL_CH7_OUT
## 0xC34 TTL_CH7_IN
## 0xC38 TTL_CH8_OUT
## 0xC3C TTL_CH8_IN
## 0xC40 TTL_CH9_OUT
## 0xC44 TTL_CH9_IN
## 0xC48 TTL_CH10_OUT
## 0xC4C TTL_CH10_IN
##
## At hardware level, the channels are daisy-chained, CH1 output to CH2 input,
## CH2 output to CH3 input and so forth, until the last channel, CH10, which is
## connected back to the CH1 input. CH1 generates pulses twice a second which
## get sent from one channel to the other in the daisy chain.
##
## This module contains a pulse counter class which implements methods to decode
## channel pulse counter numbers into their respective address. In the main
## function of the module, a pulse counter object is created and pulses are
## generated from CH10 for 1 second. These pulses are replicated through the
## daisy chain and the counters are updated on each pulse. At the end of the
## test, at least two pulses should be replicated through the daisy chain. The test
## program waits for 1s, stops pulse generation on CH10 and reads the pulse
## counter values. If the number of pulses received on ALL channels matches
## the expected number of pulse, the test passes, otherwise the circuit that
## might be the fault is indicated.
##
## After the TTL lines are tested, the switch lines are read for correct values.
## The switches should in this purpose be set in their default position:
##
## SW1 SW2
## ON | | | | | | | | |o|
## OFF |o|o|o|o| |o|o|o| |
## 1 2 3 4 1 2 3 4
##
## The test checks these lines and since an ON switch connects the FPGA input to
## GND, the above switch setup should yield the value 0xFF. If this value gets
## read back from the switches, the switch test is successful.
##
## Authors Theodor-Adrian Stana (t.stana@cern.ch)
## Website http://www.ohwr.org/projects/conv-ttl-rs485
## Date 31/10/2013
##-----------------------------------------------------------------------------------------------
##
##------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
import time
import os, errno, re, struct
import os.path
import traceback
# Import common modules
from ctypes import *
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
class CPulseCounter:
def __init__(self, bus, base):
self.bus = bus
self.base = base
def wr_reg(self, addr, val):
self.bus.vv_write(self.base + addr,val)
def rd_reg(self, addr):
return self.bus.vv_read(self.base + addr)
def wr_out_cnt(self, chan, val):
return self.wr_reg((chan-1)*8, val)
def wr_in_cnt(self, chan, val):
return self.wr_reg((chan-1)*8 + 4, val)
def rd_out_cnt(self, chan):
return self.rd_reg((chan-1)*8)
def rd_in_cnt(self, chan):
return self.rd_reg((chan-1)*8 + 4)
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus, tname, inf, log):
"""
tests : TTL pulse repetition, buffers IC2, IC3, Schmitt trigger
inputs IC4, IC9, NAND gate IC8
uses : pts.bit and ttl_pulse_switch.py
"""
pel = PTS_ERROR_LOGGER(inf, log)
chans = ['1', '2', '3', '4', '5', '6', 'A', 'B', 'C', 'D']
try:
# Initialize a pulse counter object
pc = CPulseCounter(bus, PULSE_CNT_BASE)
# Clear pulse counters for the TTL channels
for i in range(1, 11):
pc.wr_out_cnt(i, 0)
pc.wr_in_cnt(i, 0)
# Enable pulse generation
val = bus.vv_read(CSR)
val |= (1 << CSR_TTL_EN_OFS)
bus.vv_write(CSR, val)
# wait one second, then disable pulse generation
time.sleep(1)
val &= ~(1 << CSR_TTL_EN_OFS)
bus.vv_write(CSR, val)
# Read the channel registers
ic_arr = []
oc_arr = []
for i in range(1,11):
ic_arr.append(pc.rd_in_cnt(i))
oc_arr.append(pc.rd_out_cnt(i))
# First, check for all-zeroes in counters, indicating enable NAND gate failure
if all(ic == 0 for ic in ic_arr):
msg = "ERROR: No pulses received - check daisy-chain, or enable NAND gate IC8"
pel.set(msg)
# Then, check if the number of pulses sent on the previous channel has
# been received correctly on the current channel
for i in range(0,10):
if (ic_arr[i] != 0) and (ic_arr[i] == oc_arr[i-1]):
msg = "Ch%s received %d pulses and sent %d pulses - good\n" % (chans[i], ic_arr[i], oc_arr[i])
inf.write(msg)
else:
msg = "ERROR: Ch%s received %d pulses and sent %d pulses - " % (chans[i], ic_arr[i], oc_arr[i])
if (i == 0):
msg += "check daisy-chain, IC4 or IC2, or IC3"
elif (i < 6):
msg += "check daisy-chain, IC4 or IC2"
else:
msg += "check daisy-chain, IC9 or IC3"
pel.set(msg)
# Switches test
switches = (bus.vv_read(CSR) >> CSR_SWITCHES_OFS) & 0xff
if (switches != 0x80):
msg = "ERROR: Switches readout (0x%x) incorrect - expected 0x80" % switches
pel.set(msg)
else:
msg = "Switches readout as expected: 0x%x\n" % switches
inf.write(msg)
inf.write("\n")
# Finally, return the number of errors that occured
return pel.get()
except BusException, e:
raise PtsError("SKT Exception: %s" % e)
except BusWarning, e:
raise PtsError("SKT Warning: %s" % e)
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/python/vv_pts.py 0000664 0000000 0000000 00000017304 12432353720 0026123 0 ustar 00root root 0000000 0000000 #! /usr/bin/python
# coding: utf8
# Copyright CERN, 2014
# Author: Julian Lewis
# Theodor Stana
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
import sys
import time
from ctypes import *
import os, errno, re, sys, struct
import os.path
from ptsexcept import *
import socket
from socket import SHUT_RDWR
import binascii
from ptsdefine import *
class BusException(Exception):
pass
class BusWarning(Exception):
pass
class VME(object):
def __init__(self,lun):
""" The vmeio driver lun (logical unit).
At driver install time, insmod maps lun on to
VME (csr, application window, interrupts).
Lun is set when creating a VME object
"""
self.lib = CDLL('./libvv_pts.so')
int = 0
if type(lun) == type(int):
self.lun = lun
else:
self.lun = int
raise BusWarning("Warning: VME __init__: Bad lun, default to 0")
def vv_init(self):
""" Initialize the library
loads the libvv_pts.so dynamic library
opens vmeio driver for lun 0
prepares the svec bootloader
"""
self.handle = cast(self.lib.vv_init(self.lun), c_void_p)
if self.handle == 0:
raise BusException("Failed vv_init: Can't initialize VME library")
return self.handle
def vv_close(self):
""" Close the driver and free up resources
"""
cc = self.lib.vv_close(self.handle)
self.handle = 0
if cc != 0:
raise BusException("Failed vv_close: Can't close VME library")
return cc
def vv_load(self, bit_stream, id):
""" Load the FPGA
reads the FPGA bitstream image file
initializes the svec bootloader
loads the FPGA image
initializes the loaded VME core for lun 0
"""
cc = self.lib.vv_load(self.handle, bit_stream, id)
if cc == -1:
raise BusException("Failed vv_load: Can't load bit_stream: %s" % (bit_stream))
return cc
def vv_write(self, byte_offset, value):
""" Write to the application FPGA wishbone bus
The byte offset will be aligned to D32
The value is a 32 bit integer
"""
x = c_int(value)
cc = self.lib.vv_write(self.handle, byte_offset, byref(x), 4)
if cc != 0:
raise BusException("Failed vv_write: offset:0x%X value:%d" % (byte_offset, value))
return cc
def vv_write_array(self, byte_offset, buf, size):
""" Write an array of data from the string array buf
size is the number of bytes to write aligned D32
"""
cc = self.lib.vv_write(self.handle, byte_offset, id(buf), size)
if cc != 0:
raise BusException("Failed vv_write_array: offset:0x%X size:%d" % (byte_offset, size))
return cc
def vv_read(self, byte_offset):
""" Read from the application FPGA wishbone bus
The byte offset will be aligned to D32
The value will contain the 32 bit integer read
"""
x = c_int(0)
cc = self.lib.vv_read(self.handle, byte_offset, byref(x), 4)
value = x.value
if cc != 0:
raise BusException("Failed vv_read: offset:0x%X" % (byte_offset))
return value & 0xFFFFFFFF
def vv_read_array(self, byte_offset, buf, size):
""" Read size bytes into the string array buf
The byte_offset and size will be D32 aligned
"""
cc = self.lib.vv_read(self.handle, byte_offset, id(buf), size)
if cc != 0:
raise BusException("Failed vv_read_array: offset:0x%X size:%d" % (byte_offset, size))
return cc
def vv_irqwait(self):
""" Wait for an interrupt
An ISR is installed and reads the interrupt source register from the FPGA application
If no interrupt occurs after one second the return is -1 and errno is ETIME
"""
x = c_int(0)
cc = self.lib.vv_irqwait(self.handle, byref(x))
irq_src = x.value
if cc != 0:
raise BusException("Failed vv_irqwait: No interrupt")
return irq_src
class PCI(object):
def __init__(self,lun):
""" The pciio driver lun (logical unit).
"""
self.lib = CDLL('./libvv_pts.so')
int = 0
if type(lun) == type(int):
self.lun = lun
else:
self.lun = int
raise BusWarning("Warning: PCI __init__: Bad lun, default to 0")
class SKT(object):
def __init__(self,lun):
""" Telnet access over a socket to ELMA I2C bus
"""
int = ELMASLOT
if type(lun) == type(int):
self.lun = lun
else:
self.lun = int
raise BusWarning("Warning: SKT __init__: Bad lun=(slot), default to %s" % int)
self.base = 0;
s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
s.connect((ELMAIP, 23))
s.recv(256)
s.send("admin\r\n")
s.recv(256)
s.send(ELMAPWD + "\r\n")
s.recv(256)
self.handle = s
# get crate firmware version, to apply proper address in readreg/writereg
self.handle.send("version\r\n")
ver = self.handle.recv(256)
pos = ver.find("Software version")
if (pos == -1):
print("Unexpected response from \"version\" command, exiting...")
self.close()
sys.exit(2)
ver = float(ver[pos+17:pos+21])
self.ver = ver
def vv_write(self, byte_offset, value):
""" Write to the application FPGA via ELMA telnet
The byte offset will be aligned to D32
The value is a 32 bit integer
"""
try:
cm = "writereg %d %x %x\r\n" % (self.lun, byte_offset, value)
if (self.ver < 2.27):
rn = byte_offset/4 + 1
cm = "writereg %d %d %x\r\n" % (self.lun,rn,value)
#print "vv_write:Debug:cm:%s\n" % (cm)
self.handle.send(cm)
except Exception as e:
msg = "vv_write: No reply from register at address 0x%03x " % (byte_offset)
raise BusException(msg)
return self.handle.recv(256).find("Done")
def vv_read(self, byte_offset):
""" Read from the application FPGA via ELMA telnet
The byte offset will be aligned to D32
The value will contain the 32 bit integer read
"""
try:
cm = "readreg %d %x\r\n" % (self.lun, byte_offset)
if (self.ver < 2.27):
rn = byte_offset/4 + 1
cm = "readreg %d %d\r\n" % (self.lun,rn)
#print "vv_read:Debug:cm:%s\n" % (cm)
self.handle.send(cm)
orig = self.handle.recv(256)
rp = orig
rp = rp.split(" ")[3]
rp = rp.split("\n")[0]
rp = int(rp,16)
except Exception as e:
msg = "vv_read: No reply from register at address 0x%03x " % (byte_offset)
raise BusException(msg)
return rp
def vv_load(self):
""" Load the FPGA, its sort of a NO-OP in SKT class
"""
bid = self.vv_read(BIDR)
bid = binascii.unhexlify("%s" % "{0:x}".format(bid))
if bid in BIDR_ARR:
return 0
else:
raise BusException("Failed vv_load: FPGA: Bad board ID: %s" % bid)
return 2
def vv_init(self):
""" Init the library, its a NO-OP in SKT class
"""
return self.handle
def vv_close(self):
""" Close the socket
"""
self.handle.shutdown(SHUT_RDWR)
self.handle.close()
self.handle = 0
return 0
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/shell/ 0000775 0000000 0000000 00000000000 12432353720 0024011 5 ustar 00root root 0000000 0000000 conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/shell/flash 0000775 0000000 0000000 00000000144 12432353720 0025033 0 ustar 00root root 0000000 0000000 #!/bin/bash
xc3sprog -c xpc flash_load.bit
xc3sprog -c xpc -I golden-v0.0_release-v1.0.bin:w:0:bin
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/shell/get-fan-speeds 0000775 0000000 0000000 00000000274 12432353720 0026544 0 ustar 00root root 0000000 0000000 #!/bin/bash
echo Get ELMA fan speeds and store them in log/fan-speeds
rm -f ../log/fan-speeds
snmpwalk -v2c -c Gr@nBr@st0 cfvm-864-celma1 1.3.6.1.4.1.37968.1.1.5.2.1.3 > ../log/fan-speeds
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/shell/men-off 0000775 0000000 0000000 00000000166 12432353720 0025271 0 ustar 00root root 0000000 0000000 #!/bin/bash
echo Power OFF ELMA crate
snmpset -v2c -c Gr@nBr@st0 cfvm-864-celma1 1.3.6.1.4.1.37968.1.1.7.2.1.3.1 i 1
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/shell/men-on 0000775 0000000 0000000 00000000166 12432353720 0025133 0 ustar 00root root 0000000 0000000 #!/bin/bash
echo Power ON ELMA crate
snmpset -v2c -c Gr@nBr@st0 cfvm-864-celma1 1.3.6.1.4.1.37968.1.1.7.2.1.3.1 i 0
conv-ttl-rs485-tst-3fdf92d96718a8ae0b0a2a328a2d29dda11e103f/pts/shell/program 0000775 0000000 0000000 00000000045 12432353720 0025405 0 ustar 00root root 0000000 0000000 #!/bin/bash
xc3sprog -c xpc pts.bit