Commit f5df7ceb authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Small changes and additions to HDL guide

parent 28b9e276
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm} \noindent \rule{\textwidth}{.1cm}
\hfill January 5, 2015 \hfill January 6, 2015
\vspace*{3cm} \vspace*{3cm}
......
...@@ -84,7 +84,7 @@ Reset value: 0x54343835 ...@@ -84,7 +84,7 @@ Reset value: 0x54343835
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\ \multicolumn{1}{|c|}{-} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
...@@ -128,13 +128,6 @@ I2C\_WDTO ...@@ -128,13 +128,6 @@ I2C\_WDTO
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
WRPRES
} [\emph{read-only}]: White Rabbit present
\\
1 -- White Rabbit present \\ 0 -- White Rabbit not present
\end{small}
\item \begin{small}
{\bf
I2C\_ERR I2C\_ERR
} [\emph{read/write}]: I2C communication error } [\emph{read/write}]: I2C communication error
\\ \\
...@@ -144,7 +137,8 @@ I2C\_ERR ...@@ -144,7 +137,8 @@ I2C\_ERR
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
\end{small} \end{small}
\end{itemize} \end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{CR -- Control Register} \subsubsection{CR -- Control Register}
\label{app:conv-regs-cr} \label{app:conv-regs-cr}
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...@@ -53,9 +53,9 @@ ...@@ -53,9 +53,9 @@
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...@@ -250,7 +250,7 @@ ...@@ -250,7 +250,7 @@
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y="127.36218" y="127.36218"
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...@@ -75,7 +75,7 @@ work, see \\ ...@@ -75,7 +75,7 @@ work, see \\
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\ \multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline \hline
06-08-2014 & 0.1 & First draft \\ 06-08-2014 & 0.1 & First draft \\
05-01-2015 & 0.2 & Release for gateware v0.0 \\ 06-01-2015 & 0.2 & Release for gateware v0.0 \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -99,6 +99,7 @@ FPGA & Field-Programmable Gate Array \\ ...@@ -99,6 +99,7 @@ FPGA & Field-Programmable Gate Array \\
LSR & Line Status Register \\ LSR & Line Status Register \\
OSWR & Other Switches Register \\ OSWR & Other Switches Register \\
SR & Status Register \\ SR & Status Register \\
SNMP & Simple Network Management Protocol \\
\end{tabular} \end{tabular}
\addcontentsline{toc}{section}{List of abbreviations} \addcontentsline{toc}{section}{List of abbreviations}
...@@ -112,7 +113,7 @@ SR & Status Register \\ ...@@ -112,7 +113,7 @@ SR & Status Register \\
This document is the HDL guide for the CONV-TTL-RS485 project~\cite{conv-ttl-rs485-ohwr}. This document is the HDL guide for the CONV-TTL-RS485 project~\cite{conv-ttl-rs485-ohwr}.
The HDL for the CONV-TTL-RS485 board uses the converter board common gateware~\cite{conv-common-gw} The HDL for the CONV-TTL-RS485 board uses the converter board common gateware~\cite{conv-common-gw}
as a subproject and adds some external logic to it to adapt for peculiarities on the CONV-TTL-RS485. as a subproject and adds some external logic to it to adapt for peculiarities on the CONV-TTL-RS485.
This short HDL guide explains these peculiarities and the corresponding logic implemented, and lists This document explains these peculiarities and the corresponding logic implemented, and lists
the memory map for the gateware in Appendix~\ref{app:memmap}. the memory map for the gateware in Appendix~\ref{app:memmap}.
\subsection{Additional documentation} \subsection{Additional documentation}
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