Commit d81130fe authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Merge branch 'DB-new-conv-common-gw'

parents 5f388fea 060e706b
......@@ -9,9 +9,9 @@
\noindent \rule{\textwidth}{.1cm}
\hfill Gateware v1.0
\hfill Gateware v2.0
\hfill January 27, 2015
\hfill August 29, 2018
\vspace*{3cm}
......@@ -26,7 +26,7 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent {\Large \textbf{CERN/BE-CO-HT}}
\noindent \rule{\textwidth}{.05cm}
......
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......@@ -12,10 +12,15 @@
}
@misc{conv-ttl-rs485-ug,
title = {{CONV-TTL-RS485 User Guide on OHWR}},
title = {{CONV-TTL-RS485 User Guide}},
howpublished = {\url{http://www.ohwr.org/documents/351}}
}
@misc{conv-ttl-RS485-hwguide,
title = {{CONV-TTL-RS485 Hardware Guide}},
howpublished = {\url{https://www.ohwr.org/attachments/5519/hwg-conv-ttl-rs485.pdf}}
}
@misc{conv-ttl-rs485-sch,
title = {{CONV-TTL-RS485 on CERN EDMS}}},
howpublished = {\url{https://edms.cern.ch/nav/P:EDA-02541:V0/I:EDA-02541-V1-0:V0/TAB4}}
......
......@@ -78,6 +78,8 @@ work, see \\
06-01-2015 & 0.2 & Release for gateware v0.0 \\
06-01-2015 & 1.0 & Updated memory map for gateware v1.0 \\
27-01-2015 & 1.1 & Added repository download commands to Section~\ref{sec:intro} \\
29-08-2018 & 2.0 & Updated version for release v2.0 ~\ref{sec:intro} \\
\hline
\end{tabular}
}
......@@ -171,7 +173,7 @@ on.
In addition, because in TTL-BAR mode a lack of signal on the line is high (due
to the on-board Schmitt-trigger buffer), the \textit{no signal detect} block
(Figure~\ref{fig:no-sig-detect}) disables this line if it is high for 100~${\mu}s$,
to allow propagation of blocking pulses arriving on the rear panel while the channel
to allow propagation of pulses arriving on the rear panel while the channel
has no cable plugged in while in TTL-BAR mode.
When in TTL-BAR mode, the FRONTFS bits of the lines status register
......@@ -268,6 +270,21 @@ OSWR (see Appendix~\ref{app:memmap}), as shown in Figure~\ref{fig:switches}.
\caption{\label{fig:switches} Switch input logic}
\end{figure}
%==============================================================================
% SEC: PCB Version
%==============================================================================
\subsection{PCB Version}
\label{sec:pcb-ver}
CONV-TTL-RS485 boards from version 4 onwards, offer the possibility for the FPGA to receive
information on the hardware version. This information is hardwired on the board in the form of
pulled-up or pulled-down resistors for each of the 6 lines~\cite{conv-ttl-RS485-hwguide}
(4 bits for the PCB version number, and 2 bits for the execution).
The PCB version is stored as 6 bits inside the Status Register of the memory map~\ref{app:memmap} for diagnotics.
Since the hardware version is not available on older boards and since the I/O pins now assigned to it were by default pulled-
down, boards v3 and earlier will show the PCB version as 000000.
%==============================================================================
\pagebreak
\section{Output logic}
......@@ -294,6 +311,8 @@ when it is OFF.
%==============================================================================
\subsection{Pulse LED output logic}
\label{sec:pulse-led}
\textit {Note that this very same logic has been moved inside conv-common-gw submodule
for inverted channels.}\\
Since in the CONV-TTL-RS485 schematics the rear-panel pulse LEDs are driven from inverting
Schmitt triggers to ground, the active-high pulse LED output from \textit{conv\_common\_gw}
......
conv-common-gw @ a381f447
Subproject commit 3ae0cfc27599e426d1eeb47bb4312a88a4aff160
Subproject commit a381f44777f923edd813b0068742ccbcf694ea71
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C bus model
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-11-27
--
-- version: 1.0
--
-- description:
-- A very simple I2C bus model for use in simulation, implementing the
-- wired-AND on the I2C protocol.
--
-- Masters and slaves should implement the buffers internally and connect the
-- SCL and SDA lines to the input ports of this model, as below:
-- - masters should connect to mscl_i and msda_i
-- - slaves should connect to sscl_i and ssda_i
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-11-27 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_bus_model is
generic
(
g_nr_masters : positive := 1;
g_nr_slaves : positive := 1
);
port
(
-- Input ports from master lines
mscl_i : in std_logic_vector(g_nr_masters-1 downto 0);
msda_i : in std_logic_vector(g_nr_masters-1 downto 0);
-- Input ports from slave lines
sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0);
ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0);
-- SCL and SDA line outputs
scl_o : out std_logic;
sda_o : out std_logic
);
end entity i2c_bus_model;
architecture behav of i2c_bus_model is
--==============================================================================
-- architecture begin
--==============================================================================
begin
scl_o <= '1' when (mscl_i = (mscl_i'range => '1')) and
(sscl_i = (sscl_i'range => '1')) else
'0';
sda_o <= '1' when (msda_i = (msda_i'range => '1')) and
(ssda_i = (ssda_i'range => '1')) else
'0';
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
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#
# Create work library
#
vlib work
#
# Compile sources
#
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/fastevent_counter.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_regs.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_man_trig.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
vcom -explicit -93 "./print_pkg.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
vcom -explicit -93 "../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
vcom -explicit -93 "../top/conv_ttl_rs485.vhd"
vcom -explicit -93 "./testbench_pkg.vhd"
vcom -explicit -93 "./i2c_master_and_driver.vhd"
vcom -explicit -93 "./i2c_bus_model.vhd"
vcom -explicit -93 "./testbench.vhd"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ns -lib work work.testbench
#
# Source the wave do file
#
do {testbench_wave.fdo}
#
# Set the window types
#
view wave
view structure
view signals
#
# Source the user do file
#
do {testbench.udo}
#
# Run simulation for this time
#
run 2 ms
#
# End
#
\ No newline at end of file
Preliminary testebench specification
Connect I/O of conv-ttl-xxx board:
- Connect Chx front - Send n pulses
- Connect Chy rear - Send m pulses
- Connect inverter channel to a signal
- Connect RTM lines to pattern (Eg: conv-ttl-rs485-rtm-db9)
-------------------------------------------
* Check output ports:
- Check chx front AND rear outputs correspond to front-input
- Check chy front AND rear outputs correspond to rear-input
- Check output channel is exactly the inverted version of the input
-Check all LEDs blink correctly
-------------------------------------------
Implementing I2C master, scheck following:
*Check pulse counters"
- Check pulse counters show correct values for chx (front n pulses, rear 0)
and chy (front 0 pulses, rear m)
- Check counters roll-over when max value reached
- Check counters can be reset remotely
*Check switches:
- Activate "ttl-bar" mode
- Input ttl pulses on chx, check output is inverted
- Activate glitch filter
- Send pulse shorter than 50ns -> check pulse is ignored
- Send pulse longer than 50ns -> check output is synched to clock
* Check RTM line register is correct
* Check correct flagging of errors:
- I2C error (see manual)
* Check time stamping
- Check pulse timetag in last timestamp register
\ No newline at end of file
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diff --git a/top/conv_common_gw.vhd b/top/conv_common_gw.vhd
index 489f311..504a661 100644
--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
@@ -57,6 +57,9 @@ use work.conv_common_gw_pkg.all;
entity conv_common_gw is
generic
(
+ -- Reduces some timeouts to speed up simulations
+ g_simul : boolean := false;
+
-- Number of repeater channels
g_nr_chans : integer := 6;
-- Number of inverter channels
@@ -314,6 +317,7 @@ architecture arch of conv_common_gw is
signal rst_20_n : std_logic;
signal rst_20 : std_logic;
signal rst_ext : std_logic;
+ signal rst_time : positive := 10;
-- Pulse logic signals
signal trig_a : std_logic_vector(g_nr_chans-1 downto 0);
@@ -543,12 +547,14 @@ begin
-- External reset input to reset generator
rst_ext <= rst_fr_reg or (not vme_sysreset_n_i);
+ -- Reset time: 50ns * 2 * (10**6) = 100 ms
+ rst_time <= 10; --2*(10**6) when g_simul = FALSE else 10;
+
-- Configure reset generator for 100ms reset
cmp_reset_gen : conv_reset_gen
generic map
(
- -- Reset time: 50ns * 2 * (10**6) = 100 ms
- g_reset_time => 2*(10**6)
+ g_reset_time => rst_time
)
port map
(
diff --git a/top/conv_common_gw_pkg.vhd b/top/conv_common_gw_pkg.vhd
index e8a0787..1271ca1 100644
--- a/top/conv_common_gw_pkg.vhd
+++ b/top/conv_common_gw_pkg.vhd
@@ -71,6 +71,8 @@ package conv_common_gw_pkg is
component conv_common_gw is
generic
(
+ -- Reduces some timeouts to speed up simulations
+ g_simul : boolean := false;
-- Number of repeater channels
g_nr_chans : integer := 6;
g_nr_inv_chans : integer := 4;
diff --git a/ip_cores/conv-common-gw b/ip_cores/conv-common-gw
--- a/ip_cores/conv-common-gw
+++ b/ip_cores/conv-common-gw
@@ -1 +1 @@
-Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec
+Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec-dirty
diff --git a/top/conv_ttl_rs485.vhd b/top/conv_ttl_rs485.vhd
index 40adb75..53750f0 100644
--- a/top/conv_ttl_rs485.vhd
+++ b/top/conv_ttl_rs485.vhd
@@ -49,6 +49,7 @@ use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_ttl_rs485 is
+ generic (g_simul : boolean := FALSE);
port
(
-- Clocks
@@ -335,7 +336,7 @@ begin
cmp_conv_common : conv_common_gw
generic map
(
- -- Number of repeater channels
+ g_simul => g_simul,
g_nr_chans => c_nr_chans,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
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......@@ -103,27 +103,27 @@ NET "inv_o[3]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Channel LEDs
#------------------------------------------------------------------------------
NET "led_front_o[0]" LOC = H3;
NET "led_front_o[0]" IOSTANDARD = LVCMOS33;
NET "led_front_o[1]" LOC = J4;
NET "led_front_o[1]" IOSTANDARD = LVCMOS33;
NET "led_front_o[2]" LOC = J3;
NET "led_front_o[2]" IOSTANDARD = LVCMOS33;
NET "led_front_o[3]" LOC = K3;
NET "led_front_o[3]" IOSTANDARD = LVCMOS33;
NET "led_front_o[4]" LOC = L4;
NET "led_front_o[4]" IOSTANDARD = LVCMOS33;
NET "led_front_o[5]" LOC = L3;
NET "led_front_o[5]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[0]" LOC = AA4;
NET "led_inv_o[0]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[1]" LOC = AB4;
NET "led_inv_o[1]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[2]" LOC = AB5;
NET "led_inv_o[2]" IOSTANDARD = LVCMOS33;
NET "led_inv_o[3]" LOC = Y5;
NET "led_inv_o[3]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[0]" LOC = H3;
NET "led_front_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[1]" LOC = J4;
NET "led_front_n_o[1]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[2]" LOC = J3;
NET "led_front_n_o[2]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[3]" LOC = K3;
NET "led_front_n_o[3]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[4]" LOC = L4;
NET "led_front_n_o[4]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[5]" LOC = L3;
NET "led_front_n_o[5]" IOSTANDARD = LVCMOS33;
NET "led_front_inv_n_o[0]" LOC = AA4;
NET "led_front_inv_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_front_inv_n_o[1]" LOC = AB4;
NET "led_front_inv_n_o[1]" IOSTANDARD = LVCMOS33;
NET "led_front_inv_n_o[2]" LOC = AB5;
NET "led_front_inv_n_o[2]" IOSTANDARD = LVCMOS33;
NET "led_front_inv_n_o[3]" LOC = Y5;
NET "led_front_inv_n_o[3]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Status LEDs
......@@ -158,6 +158,23 @@ NET "led_gf_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_ttl_i2c_o" LOC = E6;
NET "led_ttl_i2c_o" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# PCB version pins
#------------------------------------------------------------------------------
NET "pcbrev_i[0]" LOC = A3;
NET "pcbrev_i[0]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[1]" LOC = A4;
NET "pcbrev_i[1]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[2]" LOC = R4;
NET "pcbrev_i[2]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[3]" LOC = P4;
NET "pcbrev_i[3]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[4]" LOC = V5;
NET "pcbrev_i[4]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[5]" LOC = Y3;
NET "pcbrev_i[5]" IOSTANDARD = LVCMOS33;
#=============================================================================
# Rear panel signals
......
This diff is collapsed.
files = [
"conv_ttl_rs485.ucf",
"conv_ttl_rs485.vhd"
]
modules = {
"local" : [
"../ip_cores/conv-common-gw"
],
}
This diff is collapsed.
diff --git a/ip_cores/conv-common-gw b/ip_cores/conv-common-gw
--- a/ip_cores/conv-common-gw
+++ b/ip_cores/conv-common-gw
@@ -1 +1 @@
-Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec
+Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec-dirty
diff --git a/top/conv_ttl_rs485.vhd b/top/conv_ttl_rs485.vhd
index 40adb75..53750f0 100644
--- a/top/conv_ttl_rs485.vhd
+++ b/top/conv_ttl_rs485.vhd
@@ -49,6 +49,7 @@ use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_ttl_rs485 is
+ generic (g_simul : boolean := FALSE);
port
(
-- Clocks
@@ -335,7 +336,7 @@ begin
cmp_conv_common : conv_common_gw
generic map
(
- -- Number of repeater channels
+ g_simul => g_simul,
g_nr_chans => c_nr_chans,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
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