Skip to content

C
Conv TTL RS485 - Gateware
Commit d373a166 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
Browse files
Options

Created golden folder for synthesis and golden top file. Moved top release file to release folder

parent 68406e40
Hide whitespace changes
Inline Side-by-side
Showing with 702 additions and 33 deletions
syn/Golden/conv_ttl_rs485.xise
View file @ d373a166
......@@ -93,6 +93,7 @@
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
......@@ -133,7 +134,7 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_rs485|arch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/conv_ttl_rs485.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/Golden/conv_ttl_rs485.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_rs485" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -342,38 +343,38 @@
<libraries/>
<files>
<file xil_pn:name="../../top/conv_ttl_rs485.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../../top/Golden/conv_ttl_rs485.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -397,7 +398,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -406,7 +407,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -421,10 +422,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -433,13 +434,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
......@@ -451,19 +452,20 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../top/conv_ttl_rs485.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<file xil_pn:name="../../top/Golden/conv_ttl_rs485.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -475,7 +477,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -577,13 +579,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -673,7 +675,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -703,16 +705,40 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="147"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="150"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="151"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
</files>
......
top/Golden/conv_ttl_rs485.vhd 0 → 100644
View file @ d373a166
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- CONV-TTL-RS485 gateware
-- URL https://www.ohwr.org/projects/conv-ttl-rs485-hw/wiki/wiki/
--------------------------------------------------------------------------------
--
-- Top-level design for CONV-TTL-RS485
--
-- Dependencies:
-- general-cores repository [1]
--
-- References:
-- [1] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_ttl_rs485 is
generic (g_SIMUL : boolean := false;
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_RST_TIME : positive := 2*(10**6)
);
port
(
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- VME interface
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- PCB version recognition
pcbrev_i : in std_logic_vector(5 downto 0);
-- Channel enable
global_oen_o : out std_logic;
ttl_oen_o : out std_logic;
inv_oen_o : out std_logic;
rs485_oen_o : out std_logic;
-- Front panel channels
ttl_n_i : in std_logic_vector(5 downto 0);
ttl_o : out std_logic_vector(5 downto 0);
inv_n_i : in std_logic_vector(3 downto 0);
inv_o : out std_logic_vector(3 downto 0);
-- Rear panel channels
rs485_n_i : in std_logic_vector(5 downto 0);
rs485_fs_n_i : in std_logic_vector(5 downto 0);
rs485_o : out std_logic_vector(5 downto 0);
-- Rear input and output termination lines
iterm_en_o : out std_logic_vector(5 downto 0);
oterm_en_o : out std_logic_vector(5 downto 0);
-- Channel leds
led_front_n_o : out std_logic_vector(5 downto 0);
led_front_inv_n_o : out std_logic_vector(3 downto 0);
led_rear_n_o : out std_logic_vector(5 downto 0);
-- SPI interface to on-board flash chip
flash_cs_n_o : out std_logic;
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o : out std_logic;
dac20_sclk_o : out std_logic;
dac20_sync_n_o : out std_logic;
-- 125 MHz clock generator control
dac125_din_o : out std_logic;
dac125_sclk_o : out std_logic;
dac125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
sfp_present_i : in std_logic;
sfp_rate_select_o : out std_logic;
sfp_scl_b : inout std_logic;
sfp_sda_b : inout std_logic;
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- Thermometer data port
thermometer_b : inout std_logic;
-- Switches
sw_gp_n_i : in std_logic_vector(7 downto 0);
sw_multicast_n_i : in std_logic_vector(3 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
-- Front panel bicolor LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_gp_2_4_o : out std_logic;
led_gp_1_3_o : out std_logic;
led_oterm_wr_o : out std_logic;
led_iterm_syserror_o : out std_logic;
led_gf_syspw_o : out std_logic;
led_ttl_i2c_o : out std_logic
);
end entity conv_ttl_rs485;
architecture arch of conv_ttl_rs485 is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of repetition channels
constant c_NR_CHANS : integer := 6;
constant c_NR_INV_CHANS : integer := 4;
-- Number of bicolor LED lines & columns
constant c_BICOLOR_LED_LINES : integer := 2;
constant c_BICOLOR_LED_COLS : integer := 6;
-- Board ID - ASCII string "T485"
constant c_BOARD_ID : std_logic_vector(31 downto 0) := x"54343835";
-- Gateware version
constant c_GWVERS : std_logic_vector(7 downto 0) := x"20";
--============================================================================
-- Type declarations
--============================================================================
type t_ttlbar_nosig_cnt is array (c_NR_CHANS-1 downto 0) of unsigned(10 downto 0);
type t_led_inv_cnt is array(c_NR_CHANS-1 downto 0) of unsigned(18 downto 0);
--============================================================================
-- Signal declarations
--============================================================================
-- Reset signal
signal rst_20_n : std_logic;
-- TTL & RS485 signals
signal rs485_fs : std_logic_vector(c_NR_CHANS-1 downto 0);
signal pulse_in : std_logic_vector(c_NR_CHANS-1 downto 0);
signal pulse_out : std_logic_vector(c_NR_CHANS-1 downto 0);
signal inv_pulse_in_n : std_logic_vector(c_NR_INV_CHANS-1 downto 0);
signal inv_pulse_out : std_logic_vector(c_NR_INV_CHANS-1 downto 0);
signal pulse_ttl : std_logic_vector(c_NR_CHANS-1 downto 0);
signal pulse_rs485 : std_logic_vector(c_NR_CHANS-1 downto 0);
signal rs485_phy_n_i : std_logic_vector(c_NR_CHANS-1 downto 0);
signal rs485_fs_phy_n_i : std_logic_vector(c_NR_CHANS-1 downto 0);
signal inhibit_first_pulse : std_logic;
signal inhibit_first_pulse_d0 : std_logic;
signal inhibit_cnt : unsigned(10 downto 0);
-- Line signals -- for reflection in line status register of conv_common_gw
signal line_ttl : std_logic_vector(c_NR_CHANS-1 downto 0);
signal line_invttl : std_logic_vector(3 downto 0);
signal line_rs485 : std_logic_vector(c_NR_CHANS-1 downto 0);
-- Switch signals (for inverting switch inputs to the common g/w)
signal sw_ttl : std_logic;
signal sw_iterm_en : std_logic;
signal sw_oterm_en : std_logic;
signal sw_gp : std_logic_vector(7 downto 0);
signal sw_other : std_logic_vector(31 downto 0);
-- No signal on TTL-BAR
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
signal ttlbar_nosig : std_logic_vector(c_NR_CHANS-1 downto 0);
-- INV-TTL internal signals
signal inv_n : std_logic_vector(3 downto 0);
-- signal inv_n_d0 : std_logic_vector(3 downto 0);
signal inv_n_fedge_p : std_logic_vector(3 downto 0);
-- Channel LED signals
signal led_pulse : std_logic_vector(c_NR_CHANS-1 downto 0);
signal led_inv_pulse : std_logic_vector(c_NR_INV_CHANS-1 downto 0);
-- I2C LEDs
signal led_i2c : std_logic;
signal led_i2c_err : std_logic;
signal led_inv : std_logic_vector(3 downto 0);
signal led_inv_cnt : t_led_inv_cnt;
-- System error (ERR) LED control
signal led_syserr : std_logic;
-- Bicolor LED signals
signal bicolor_led_state : std_logic_vector(2*c_BICOLOR_LED_COLS*c_BICOLOR_LED_LINES-1 downto 0);
signal bicolor_led_col : std_logic_vector(c_BICOLOR_LED_COLS-1 downto 0);
signal bicolor_led_line : std_logic_vector(c_BICOLOR_LED_LINES-1 downto 0);
signal bicolor_led_line_oen : std_logic_vector(c_BICOLOR_LED_LINES-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Channel input logic
--============================================================================
-- TTL switch
sw_ttl <= not sw_gp_n_i(7);
-- The "no signal detect" block
--
-- If the signal line is high for 100 us, the ttlbar_nosig lines disable
-- the input to the TTL side MUX and the OR gate.
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter.
p_ttlbar_nosig : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
for i in 0 to c_NR_CHANS-1 loop
if (rst_20_n = '0') or (ttl_n_i(i) = '0') then
ttlbar_nosig(i) <= '0';
ttlbar_nosig_cnt(i) <= (others => '0');
elsif sw_ttl = '0' then
ttlbar_nosig_cnt(i) <= ttlbar_nosig_cnt(i) + 1;
if ttlbar_nosig_cnt(i) = 1999 then
ttlbar_nosig(i) <= '1';
ttlbar_nosig_cnt(i) <= (others => '0');
end if;
end if;
end loop;
end if;
end process p_ttlbar_nosig;
-- TTL and blocking inputs
pulse_ttl <= not ttl_n_i when sw_ttl = '1' else
ttl_n_i and (not ttlbar_nosig);
-- Pulse input on RS-485 side valid only when failsafe not high
-- see Texas slyt257 for implementation details
gen_rs485_input : for i in 0 to c_NR_CHANS-1 generate
-- physical signal re-assignement for 2-channel rtm type (DB9 RTM) with code 101
rs485_phy_n_i(0) <= rs485_n_i(0);
rs485_phy_n_i(1) <= rs485_n_i(4) when rtmp_i = "101" else rs485_n_i(1);
rs485_phy_n_i(2) <= rs485_n_i(2) when rtmp_i = "101" else rs485_n_i(2);
rs485_phy_n_i(3) <= rs485_n_i(3) when rtmp_i = "101" else rs485_n_i(3);
rs485_phy_n_i(4) <= rs485_n_i(1) when rtmp_i = "101" else rs485_n_i(4);
rs485_phy_n_i(5) <= rs485_n_i(5) when rtmp_i = "101" else rs485_n_i(5);
rs485_fs_phy_n_i(0) <= rs485_fs_n_i(0);
rs485_fs_phy_n_i(1) <= rs485_fs_n_i(4) when rtmp_i = "101" else rs485_fs_n_i(1);
rs485_fs_phy_n_i(2) <= rs485_fs_n_i(2) when rtmp_i = "101" else rs485_fs_n_i(2);
rs485_fs_phy_n_i(3) <= rs485_fs_n_i(3) when rtmp_i = "101" else rs485_fs_n_i(3);
rs485_fs_phy_n_i(4) <= rs485_fs_n_i(1) when rtmp_i = "101" else rs485_fs_n_i(4);
rs485_fs_phy_n_i(5) <= rs485_fs_n_i(5) when rtmp_i = "101" else rs485_fs_n_i(5);
-- Failsafe RS485 implementation for no-signal-detect functionality
rs485_fs(i) <= rs485_phy_n_i(i) nor rs485_fs_phy_n_i(i);
pulse_rs485(i) <= (not rs485_phy_n_i(i)) when rs485_fs(i) = '0' else '0';
end generate gen_rs485_input;
-- This process has the effect of extending the reset an extra 100 us, to avoid
-- a pulse being generated or erroneously counted during the period of no signal
-- detect
p_inhibit_first_pulse : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if rst_20_n = '0' then
inhibit_cnt <= (others => '0');
inhibit_first_pulse <= '1';
elsif inhibit_first_pulse = '1' then
inhibit_cnt <= inhibit_cnt + 1;
if inhibit_cnt = 1999 then
inhibit_first_pulse <= '0';
end if;
end if;
end if;
end process p_inhibit_first_pulse;
-- Delay inhibit first pulse signal, use this to enable input, thus avoiding
-- internal reset states of conv_common_gw
p_inhibit_first_pulse_d0 : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if rst_20_n = '0' then
inhibit_first_pulse_d0 <= '1';
else
inhibit_first_pulse_d0 <= inhibit_first_pulse;
end if;
end if;
end process p_inhibit_first_pulse_d0;
-- Pulse input valid only after inhibit period is over
pulse_in <= (pulse_ttl or pulse_rs485) when inhibit_first_pulse_d0 = '0'
else (others => '0');
-- Line inputs for reflection in status register
line_ttl <= not ttl_n_i;
line_invttl <= not inv_n_i;
line_rs485 <= not rs485_phy_n_i;
-- Switch inputs for reflection in status register
sw_gp <= not sw_gp_n_i;
sw_other( 3 downto 0) <= not sw_multicast_n_i;
sw_other(31 downto 4) <= (others => '0');
--============================================================================
-- Instantiate common generic gateware for converter boards
--============================================================================
cmp_conv_common : conv_common_gw
generic map
(
g_SIMUL => g_SIMUL,
g_RST_TIME => g_RST_TIME,
g_nr_chans => c_NR_CHANS,
g_board_id => c_BOARD_ID,
g_gwvers => c_GWVERS,
g_PGEN_FIXED_WIDTH => false,
g_pgen_gf_len => 1,
g_with_pulse_cnt => false,
g_with_pulse_timetag => false,
g_with_man_trig => false,
g_man_trig_pwidth => 24,
g_with_thermometer => false,
g_bicolor_led_columns => c_BICOLOR_LED_COLS,
g_bicolor_led_lines => c_BICOLOR_LED_LINES
)
port map
(
-- Clocks
clk_20_i => clk_20_i,
clk_125_p_i => clk_125_p_i,
clk_125_n_i => clk_125_n_i,
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o => rst_20_n,
-- Glitch filter active-low enable signal
gf_en_n_i => sw_gp_n_i(0),
-- Burst mode enable signal. Disabled in conv-ttl-rs485
burst_en_n_i => '1',
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
-- In conv-ttl-rs485 this switch is not meaningful
pulse_width_sel_n_i => '0',
-- Channel enable
global_ch_oen_o => global_oen_o,
pulse_front_oen_o => ttl_oen_o,
pulse_rear_oen_o => rs485_oen_o,
inv_oen_o => inv_oen_o,
-- Front panel channels
pulse_i => pulse_in,
pulse_front_i => pulse_ttl,
pulse_rear_i => pulse_rs485,
pulse_o => pulse_out,
-- Inverted pulse I/O
inv_pulse_n_i => inv_pulse_in_n,
inv_pulse_o => inv_pulse_out,
-- Channel leds
led_pulse_o => led_pulse,
-- inverted channel leds
led_inv_pulse_o => led_inv_pulse,
-- I2C interface
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_en_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_en_o,
-- VME interface
vme_sysreset_n_i => vme_sysreset_n_i,
vme_ga_i => vme_ga_i,
vme_gap_i => vme_gap_i,
-- SPI interface to on-board flash chip
flash_cs_n_o => flash_cs_n_o,
flash_sclk_o => flash_sclk_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o => dac20_din_o,
dac20_sclk_o => dac20_sclk_o,
dac20_sync_n_o => dac20_sync_n_o,
-- 125 MHz clock generator control
dac125_din_o => dac125_din_o,
dac125_sclk_o => dac125_sclk_o,
dac125_sync_n_o => dac125_sync_n_o,
-- SFP lines
sfp_los_i => sfp_los_i,
sfp_present_i => sfp_present_i,
sfp_rate_select_o => sfp_rate_select_o,
sfp_sda_b => sfp_scl_b,
sfp_scl_b => sfp_sda_b,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_tx_fault_i => sfp_tx_fault_i,
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o => led_i2c,
-- Switch inputs (for readout from converter status register)
sw_gp_i => sw_gp,
sw_other_i => sw_other,
-- PCB Version information
hwvers_i => pcbrev_i,
-- RTM lines
rtmm_i => rtmm_i,
rtmp_i => rtmp_i,
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i => line_ttl,
line_inv_i => line_invttl,
line_rear_i => line_rs485,
line_front_fs_i => ttlbar_nosig,
line_inv_fs_i => (others => '0'),
line_rear_fs_i => rs485_fs,
-- Thermometer line
thermometer_b => thermometer_b,
-- System error LED, active-high on system error
-- ERR bicolor LED should light red when led_syserr_o = '1'
led_syserr_o => led_syserr,
-- Bicolor LED signals
bicolor_led_state_i => bicolor_led_state,
bicolor_led_col_o => bicolor_led_col,
bicolor_led_line_o => bicolor_led_line,
bicolor_led_line_oen_o => bicolor_led_line_oen
);
ttl_o <= pulse_out when sw_ttl = '1' else
not pulse_out;
-- rs485_o (1 downto 0) <= pulse_out (1 downto 0);
-- Channels 3 and 4 output copies of chans 1 and 2 respectively
-- depending on RTMP Id of RTM connected.
-- *RTM with DB9 connectors has only 2 o/p channels in rs485 RTMP = Gnd Open Gnd
-- *Optical RTM only 2 o/p channels in optical RTMP= Open Open Gnd
-- in these cases channel 3 copies channel 1
-- channel 4 copies channel 2
-- rs485_o (3 downto 2) <= pulse_out (1 downto 0) when rtmp_i = "101" or rtmp_i = "100"
-- rs485_o (5 downto 4) <= pulse_out (5 downto 4);
--============================================================================
-- Channel output logic
--============================================================================
-- Front and rear panel outputs
rs485_o(0) <= pulse_out(0);
rs485_o(1) <= pulse_out(0) when rtmp_i = "101" else pulse_out(1);
rs485_o(2) <= pulse_out(2);
rs485_o(3) <= pulse_out(3);
rs485_o(4) <= pulse_out(1) when rtmp_i = "101" else pulse_out(4);
rs485_o(5) <= pulse_out(1) when rtmp_i = "101" else pulse_out(5);
-- LED outputs
-- Boards earlier than v4 do not use -ve logic for LEDs.
-- For these LED pulse signals are still in +ve logic.
-- Rear pulses are negative logic on all boards
led_front_n_o <= led_pulse when pcbrev_i (5 downto 0) = "000000"
else not led_pulse;
led_front_inv_n_o <= led_inv_pulse when pcbrev_i (5 downto 0) = "000000"
else not led_inv_pulse;
led_rear_n_o(0) <= not led_pulse(0);
led_rear_n_o(1) <= not led_pulse(4) when rtmp_i = "101" else not led_pulse(1);
led_rear_n_o(2) <= not led_pulse(2) when rtmp_i = "101" else not led_pulse(2);
led_rear_n_o(3) <= not led_pulse(3) when rtmp_i = "101" else not led_pulse(3);
led_rear_n_o(4) <= not led_pulse(1) when rtmp_i = "101" else not led_pulse(4);
led_rear_n_o(5) <= not led_pulse(5) when rtmp_i = "101" else not led_pulse(5);
-- INV-TTL outputs
inv_pulse_in_n <= inv_n_i;
inv_o <= inv_pulse_out;
-- Channel terminations
sw_iterm_en <= sw_gp(1);
sw_oterm_en <= sw_gp(2);
iterm_en_o <= (others => sw_iterm_en);
oterm_en_o <= (others => sw_oterm_en);
--============================================================================
-- External logic for bicolor LED control
--============================================================================
-- Assign bicolor LED lines & columns to outputs
led_ttl_i2c_o <= bicolor_led_col(0);
led_oterm_wr_o <= bicolor_led_col(1);
led_iterm_syserror_o <= bicolor_led_col(2);
led_gf_syspw_o <= bicolor_led_col(3);
led_gp_2_4_o <= bicolor_led_col(4);
led_gp_1_3_o <= bicolor_led_col(5);
led_ctrl0_o <= bicolor_led_line(0);
led_ctrl1_o <= bicolor_led_line(1);
led_ctrl0_oen_o <= bicolor_led_line_oen(0);
led_ctrl1_oen_o <= bicolor_led_line_oen(1);
-- TTL mode (state of TTL switch)
bicolor_led_state( 1 downto 0) <= c_LED_GREEN when sw_ttl = '1' else
c_LED_OFF;
-- Output termination enabled
bicolor_led_state( 3 downto 2) <= c_LED_GREEN when sw_oterm_en = '1' else
c_LED_OFF;
-- Input termination enabled
bicolor_led_state( 5 downto 4) <= c_LED_GREEN when sw_iterm_en = '1' else
c_LED_OFF;
-- Glitch filter enabled
bicolor_led_state( 7 downto 6) <= c_LED_GREEN when sw_gp(0) = '1' else
c_LED_OFF;
-- General-purpose 4
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- General-purpose 3
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when led_i2c = '1' else
c_LED_OFF;
-- White Rabbit LED
bicolor_led_state(15 downto 14) <= c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (led_syserr = '1') or
(c_GWVERS(7 downto 4) = "0000" ) else
c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- General-purpose 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- General-purpose 1
bicolor_led_state(23 downto 22) <= c_LED_OFF;
end architecture arch;
--==============================================================================
-- architecture end
--==============================================================================
top/Release/Manifest.py 0 → 100644
View file @ d373a166
files = [
"conv_ttl_rs485.ucf",
"conv_ttl_rs485.vhd"
]
modules = {
"local" : [
"../ip_cores/conv-common-gw"
],
}
top/conv_ttl_rs485.vhd → top/Release/conv_ttl_rs485.vhd
View file @ d373a166
......@@ -308,7 +308,7 @@ begin
inhibit_first_pulse <= '1';
elsif inhibit_first_pulse = '1' then
inhibit_cnt <= inhibit_cnt + 1;
if inhibit_cnt = 9 then -- 1999) then
if inhibit_cnt = 1999 then
inhibit_first_pulse <= '0';
end if;
end if;
......
top/Release/top_patch.patch 0 → 100644
View file @ d373a166
diff --git a/ip_cores/conv-common-gw b/ip_cores/conv-common-gw
--- a/ip_cores/conv-common-gw
+++ b/ip_cores/conv-common-gw
@@ -1 +1 @@
-Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec
+Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec-dirty
diff --git a/top/conv_ttl_rs485.vhd b/top/conv_ttl_rs485.vhd
index 40adb75..53750f0 100644
--- a/top/conv_ttl_rs485.vhd
+++ b/top/conv_ttl_rs485.vhd
@@ -49,6 +49,7 @@ use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_ttl_rs485 is
+ generic (g_simul : boolean := FALSE);
port
(
-- Clocks
@@ -335,7 +336,7 @@ begin
cmp_conv_common : conv_common_gw
generic map
(
- -- Number of repeater channels
+ g_simul => g_simul,
g_nr_chans => c_nr_chans,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment