Commit 954c8112 authored by Evangelia Gousiou's avatar Evangelia Gousiou

switched conv-common-gw branch to DB-rs485-integration

testbench wip
parent 515449df
conv-common-gw @ 1fbe6c0a
Subproject commit 656898b60e9755f6d73b0933bf0c25d3ff80db7b
Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec
--------------------------------------------------------------------------------
-- Title : ModelSim library for Riviera-PRO
-- Project :
--------------------------------------------------------------------------------
-- File : modelsim_lib.vhd
-- Author : M. Henze
-- Email :
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created :
--------------------------------------------------------------------------------
-- Simulator : Riviera-PRO
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- CAUTION - this file shall not be used for new designs. It is only kept
-- for compliance with old designs.
-- For new designs use VHDL2008 syntax instead.
--
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
-- Copyright (C) 2016, MEN Mikro Elektronik Nuremberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
--------------------------------------------------------------------------------
LIBRARY aldec;
USE aldec.signal_agent_pkg.ALL;
USE aldec.aldec_tools.ALL;
----------------------------------------
-- CAUTION! Don't use for new designs!
-- Use VHDL2008 instead!
----------------------------------------
PACKAGE util IS
TYPE force_type IS (default, deposit, drive, freeze);
type del_mode is (MTI_INERTIAL, MTI_TRANSPORT);
PROCEDURE init_signal_spy( source : IN string;
destination : IN string;
verbose : IN integer;
control : IN integer);
procedure init_signal_spy(
source : in string;
dest : in string
);
PROCEDURE signal_force( destination : IN string;
value : IN string;
rel_time : IN time;
forcetype : IN force_type;
cancel_period : IN time;
verbose : IN integer);
PROCEDURE signal_release( destination : IN string;
verbose : IN integer);
procedure init_signal_driver(
src_obj : in string;
dest_obj : in string;
delay : in time;
delay_type : in del_mode;
verbose : in integer
);
END;
PACKAGE BODY util IS
PROCEDURE init_signal_spy( source : IN string;
destination : IN string;
verbose : IN integer;
control : IN integer) IS
BEGIN
signal_agent(source, destination ,verbose);
END PROCEDURE init_signal_spy;
procedure init_signal_spy(
source : in string;
dest : in string
) is
begin
signal_agent(source,dest,0);
end procedure init_signal_spy;
PROCEDURE signal_force( destination : IN string;
value : IN string;
rel_time : IN time;
forcetype : IN force_type;
cancel_period : IN time;
verbose : IN integer) IS
BEGIN
------------------------------------------------
-- in RivieraPRO2014 the force command changed
------------------------------------------------
--force(force_type'image(forcetype), destination, value);
force_signal(force_type'image(forcetype), destination, value);
END PROCEDURE signal_force;
PROCEDURE signal_release( destination : IN string;
verbose : IN integer) IS
BEGIN
------------------------------------------------
-- in RivieraPRO2014 the force command changed
------------------------------------------------
--noforce ( destination );
noforce_signal ( destination );
END PROCEDURE signal_release;
procedure init_signal_driver(
src_obj : in string;
dest_obj : in string;
delay : in time;
delay_type : in del_mode;
verbose : in integer
) is
begin
signal_agent(src_obj, dest_obj, 0);
end procedure init_signal_driver;
END;
......@@ -32,7 +32,7 @@ use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.conv_common_gw_pkg.all;
use work.testbench_pkg.all;
use work.print_pkg.all;
entity testbench is
end entity testbench;
......@@ -64,7 +64,7 @@ architecture behav of testbench is
signal clk_20, clk_125 : std_logic;
signal clk_125_p, clk_125_n : std_logic;
signal rst_n : std_logic := '0';
signal vme_sysreset_n : std_logic := '0';
signal gf_en_n_in : std_logic;
......@@ -111,10 +111,10 @@ architecture behav of testbench is
procedure read_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out : in t_i2c_master_out;
constant slv_addr : in std_logic_vector(6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
signal rcvd_val : out std_logic_vector(31 downto 0)) is
signal i2c_m_out : in t_i2c_master_out;
constant slv_addr : in std_logic_vector(6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
signal rcvd_val : out std_logic_vector(31 downto 0)) is
begin
report "read_i2c: start ";
......@@ -132,10 +132,10 @@ architecture behav of testbench is
i2c_m_in.i2c_master_start <= '0';
wait until i2c_m_out.i2c_master_finish = '1';
rcvd_val <= i2c_m_out.i2c_master_rcvd_val;
report "-------> I2C value read from x... " & integer'image(to_integer(unsigned(i2c_m_out.i2c_master_rcvd_val)));
print_s_std("-------> I2C value read from ", reg_addr);
print_s_std("is: ", i2c_m_out.i2c_master_rcvd_val);
wait until i2c_m_out.i2c_master_finish = '0';
report "read_i2c: OK ";
wait for 50us;
end procedure read_i2c;
--==============================================================================
......@@ -163,7 +163,7 @@ begin
sda_en_o => ssda_en_out,
-- VME interface
vme_sysreset_n_i => rst_n,
vme_sysreset_n_i => vme_sysreset_n,
vme_ga_i => "11110", --
vme_gap_i => '0',
......@@ -267,17 +267,17 @@ begin
clk_125_p <= clk_125;
clk_125_n <= not clk_125;
p_rst_n: process
p_vme_sysreset_n: process
begin
rst_n <= '0';
vme_sysreset_n <= '0';
wait for c_reset_width;
rst_n <= '1';
vme_sysreset_n <= '1';
wait for c_reset_width;
rst_n <= '0';
vme_sysreset_n <= '0';
wait for c_reset_width;
rst_n <= '1';
vme_sysreset_n <= '1';
wait;
end process p_rst_n;
end process p_vme_sysreset_n;
--============================================================================
......@@ -287,7 +287,7 @@ begin
cmp_i2c_master_and_driver: entity work.i2c_master_and_driver
port map (
clk_i => clk_20,
rst_n_i => rst_n,
rst_n_i => vme_sysreset_n,
ready_o => i2c_m_out.i2c_master_ready,
start_i => i2c_m_in.i2c_master_start,
finish_o => i2c_m_out.i2c_master_finish,
......@@ -339,13 +339,14 @@ begin
i2c_m_in.i2c_master_reg_addr <= (others => '0');
i2c_m_in.i2c_master_send_val <= (others => '1');
wait until rst_n = '1';
wait until vme_sysreset_n = '1';
report "started stimulus";
wait for 50us;
wait for 1us;
generate_pulses (ttl_n_in, 256);
read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0030", i2c_master_rcvd_val );
read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0000", i2c_master_rcvd_val );
read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_000C", i2c_master_rcvd_val );
end process p_stim_i2c;
......@@ -373,7 +374,7 @@ begin
-- i2c_m_in.i2c_master_reg_addr <= (others => '0');
-- i2c_m_in.i2c_master_send_val <= (others => '1');
-- wait until rst_n = '1';
-- wait until vme_sysreset_n = '1';
-- report "started stimulus";
-- wait for 50us;
......@@ -395,7 +396,7 @@ begin
-- i2c_m_in.i2c_master_reg_addr <= (others => '0');
-- i2c_m_in.i2c_master_send_val <= (others => '1');
-- wait until rst_n = '1';
-- wait until vme_sysreset_n = '1';
-- report "started stimulus";
-- wait for 50us;
......
......@@ -23,7 +23,7 @@ use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.print_pkg.all;
package testbench_pkg is
......
......@@ -420,7 +420,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
......@@ -528,7 +528,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../top/conv_ttl_rs485.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
......@@ -588,7 +588,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
......@@ -876,15 +876,15 @@
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../sim/i2c_bus_model.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../sim/i2c_master_and_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
<file xil_pn:name="../../sim/testbench.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="127"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="127"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="127"/>
......@@ -906,11 +906,15 @@
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../sim/testbench_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../sim/print_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
</files>
<bindings/>
......
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