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Conv TTL RS485 - Gateware
Commit 7d1e1f2c authored by Evangelia Gousiou's avatar Evangelia Gousiou
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added TTL bar test

parent 8301a504
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Showing with 83 additions and 67 deletions
sim/testbench.vhd
View file @ 7d1e1f2c
......@@ -48,53 +48,47 @@ architecture behav of testbench is
-- Signal declarations
--============================================================================
signal i2c_m_in : t_i2c_master_in;
signal i2c_m_out : t_i2c_master_out;
signal i2c_m_in : t_i2c_master_in;
signal i2c_m_out : t_i2c_master_out;
signal clk_20, clk_125 : std_logic;
signal clk_125_p, clk_125_n : std_logic;
signal vme_sysreset_n : std_logic := '0';
signal clk_20, clk_125 : std_logic;
signal clk_125_p, clk_125_n : std_logic;
signal vme_sysreset_n : std_logic := '0';
signal gf_en_n_in : std_logic;
signal ttl_n_in, ttl_out : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '1');
signal rs485_n_in, rs485_fs_n_in : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '1');
signal rs485_out : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '1');
signal inv_n_in, inv_out : std_logic_vector(C_NR_INV_CHANS-1 downto 0) := (others => '0');
signal ttl_n_in, ttl_out : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '1');
signal rs485_n_in, rs485_fs_n_in : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '1');
signal rs485_out : std_logic_vector(C_NR_CHANS-1 downto 0) := (others => '1');
signal inv_n_in, inv_out : std_logic_vector(C_NR_INV_CHANS-1 downto 0) := (others => '0');
signal sscl_out : std_logic;
signal sscl_en_out : std_logic;
signal ssda_out : std_logic;
signal ssda_en_out : std_logic;
signal sscl_out : std_logic;
signal sscl_en_out : std_logic;
signal ssda_out : std_logic;
signal ssda_en_out : std_logic;
signal mscl_out : std_logic;
signal mscl_en_out : std_logic;
signal msda_out : std_logic;
signal msda_en_out : std_logic;
signal mscl_out : std_logic;
signal mscl_en_out : std_logic;
signal msda_out : std_logic;
signal msda_en_out : std_logic;
signal sw_gp_n_in : std_logic_vector(7 downto 0);
signal sw_other_in : std_logic_vector(31 downto 0);
signal pcbrev : std_logic_vector(5 downto 0);
signal rtm_in : std_logic_vector(5 downto 0);
signal i2c_master_rcvd_val : std_logic_vector(31 downto 0);
signal i2c_master_rcvd_val1 : std_logic_vector(31 downto 0);
signal sw_gp_n_in : std_logic_vector(7 downto 0);
signal sw_other_in : std_logic_vector(31 downto 0);
signal pcbrev : std_logic_vector(5 downto 0);
signal rtm_in : std_logic_vector(5 downto 0);
signal i2c_master_rcvd_val : std_logic_vector(31 downto 0);
signal i2c_master_rcvd_val1 : std_logic_vector(31 downto 0);
signal mscl, msda : std_logic_vector(C_NR_MASTERS-1 downto 0);
signal sscl, ssda : std_logic_vector(C_NR_SLAVES-1 downto 0);
signal scl, sda : std_logic;
---
signal buf_byte_cnt : natural;
-- signal nb_pulses_to_send_slv : std_logic_vector(31 downto 0);
signal reg_id : integer := 0;
signal adr : std_logic_vector(31 downto 0);
signal nb_of_pulses_rcved : integer := 0;
type cnt_ch_array is array (C_NR_CHANS-1 downto 0) of integer;
signal fp_rp_same, fp_rp_oppos, pulse_cnt_ttl, pulse_cnt_rs485 : cnt_ch_array;
type cnt_inv_ch_array is array (C_NR_INV_CHANS-1 downto 0) of integer;
signal inv_err: cnt_ch_array;
signal mscl, msda : std_logic_vector(C_NR_MASTERS-1 downto 0);
signal sscl, ssda : std_logic_vector(C_NR_SLAVES-1 downto 0);
signal scl, sda : std_logic;
signal rst_copm : std_logic;
type cnt_ch_array is array (C_NR_CHANS-1 downto 0) of integer;
signal fp_rp_same, fp_rp_oppos : cnt_ch_array;
signal in_out_oppos, in_out_same : cnt_ch_array;
signal pulse_cnt_ttl, pulse_cnt_rs485 : cnt_ch_array;
signal inv_err : cnt_ch_array;
type cnt_inv_ch_array is array (C_NR_INV_CHANS-1 downto 0) of integer;
--==============================================================================
......@@ -106,6 +100,7 @@ begin
-- Instantiate DUT
--============================================================================
cmp_DUT: conv_ttl_rs485
generic map (g_simul => false)
port map
(
-- Clocks
......@@ -280,19 +275,29 @@ begin
compare_front_rear_pulses: process (clk_125)
begin
if rising_edge (clk_125) then
if vme_sysreset_n = '0' then
fp_rp_same <= (others=> (0));
fp_rp_oppos <= (others=> (0));
if vme_sysreset_n = '0' or rst_copm = '1' then
fp_rp_same <= (others=> (0));
fp_rp_oppos <= (others=> (0));
in_out_same <= (others=> (0));
in_out_oppos <= (others=> (0));
else
for i in 0 to C_NR_CHANS-1 loop
if ttl_out(i) /= rs485_out(i) then
fp_rp_same(i) <= fp_rp_same(i)+1;
end if;
if ttl_out(i) = not rs485_out(i) then
if ttl_out(i) /= not rs485_out(i) then
fp_rp_oppos(i) <= fp_rp_oppos(i)+1;
end if;
if ttl_out(i) /= not ttl_n_in(i) then
in_out_oppos(i) <= in_out_oppos(i)+1;
end if;
if ttl_out(i) /= ttl_n_in(i) then
in_out_same(i) <= in_out_same(i)+1;
end if;
end loop;
end if;
end if;
......@@ -384,8 +389,9 @@ begin
variable nb_pulses_to_send_fp : integer := 17;
variable nb_pulses_to_send_fp_slv : std_logic_vector(31 downto 0);
variable nb_pulses_to_send_rp : integer := 5;
variable nb_pulses_to_send_inv : integer := 5;
variable nb_pulses_to_send_rp_slv : std_logic_vector(31 downto 0);
variable nb_pulses_to_send_inv : integer := 5;
variable nb_pulses_to_send_bar : integer := 6;
variable glitch_filter_en : std_logic := '0'; -- glitch filter disabled
variable ttl_out_bar_en : std_logic := '0'; -- TTLbar disabled
variable err_cnt, err : integer := 0;
......@@ -418,17 +424,13 @@ begin
---------------------------------------------------------------------------
-- I2C readings
print_now("----------------------------------------------------------------");
print_now("---> Test 01: I2C regs reading");
print_now("---> Test 01: I2C reg reading");
print_now("----------------------------------------------------------------");
-- I2C reading of the board ID register
print_now_s("I2C reading of the register ", c_REG_MAP(0).reg_name);
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, c_REG_MAP(0).reg_addr, c_REG_MAP(0).reg_name, i2c_master_rcvd_val, C_BOARD_ID, TRUE, err);
err_cnt := err_cnt +err;
-- I2C reading of the board ID register
print_now_s("I2C reading of the register ", c_REG_MAP(1).reg_name);
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, c_REG_MAP(1).reg_addr, c_REG_MAP(1).reg_name, i2c_master_rcvd_val, x"EF2AFF10", TRUE, err);
err_cnt := err_cnt +err;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
......@@ -456,7 +458,7 @@ begin
-- Sending pulses to Front Panel Channel 1
nb_pulses_to_send_fp_slv := std_logic_vector(to_unsigned(nb_pulses_to_send_fp, nb_pulses_to_send_fp_slv'length));
print_now_s_i("Sending TTL pulses to TTL_N_I(0)", nb_pulses_to_send_fp);
generate_pulse (ttl_n_in(0), nb_pulses_to_send_fp, "fp", rs485_fs_n_in(0), 200ns, 200ns);
generate_pulse (ttl_n_in(0), nb_pulses_to_send_fp, "fp", rs485_fs_n_in(0), 200ns, 200ns); -- 200ns so that the counters can count correctly
-- Checking if the number of TTL output pulses matches the sent ones
print_now("Check that the pulses arrived to the TTL_O(0)");
......@@ -465,6 +467,15 @@ begin
else
print_now_s_i("[ERR] Number of pulses measured at TTL_O(0): ",pulse_cnt_ttl(0));
err_cnt := err_cnt + 1;
end if;
-- Check if TTL_N_IN out and TTL_O out are opposite
print_now("Check that TTL_O(0) is the inverted TTL_N_IN(0)");
if in_out_oppos(0) = 0 then
print_now("[OK] TTL_O(0) is exactly the inverted TTL_N_IN(0)");
else
print_now("[ERR] TTL_O(0) is not exactly the inverted TTL_N_IN(0)");
err_cnt := err_cnt + 1;
end if;
-- Check if TTL out and RS485 out are the same
......@@ -535,7 +546,6 @@ begin
print_now_s_i("Sending pulses to RS485_N_I(0): ", nb_pulses_to_send_rp);
generate_pulse (rs485_n_in(0), nb_pulses_to_send_rp, "rp", rs485_fs_n_in(0), 200ns, 200ns);
pulse_timetag := (now/K);
print_now_s_i("**************Time: ",pulse_timetag);
-- Checking if the number of RS485 output pulses matches the sent ones
print_now("Check that the pulses arrived to the RS485_O(0)");
......@@ -592,13 +602,10 @@ begin
print_now_s_i("Estimated timetag cycles: ",time_intrvl);
if to_integer(unsigned(i2c_master_rcvd_val1(27 downto 0))) > time_intrvl+1000 or to_integer(unsigned(i2c_master_rcvd_val1(27 downto 0))) < time_intrvl-1000 then
print_now_s_std_s_std("[ERR] Registered cycles: ", i2c_master_rcvd_val1, " is far from the estimated: ", std_logic_vector(to_unsigned(time_intrvl,28)));
err_cnt := err_cnt + 1;
else
print_now_s_std_s_std("[OK] Registered cycles: ", i2c_master_rcvd_val1(27 downto 0), " is close to the estimated: ", std_logic_vector(to_unsigned(time_intrvl,28)));
err_cnt := err_cnt + 1;
end if;
err_cnt := err_cnt + err;
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, CH1LTSTLR, "CH1LTSTL", i2c_master_rcvd_val, (others =>'0'), TRUE, err);
err_cnt := err_cnt + err;
read_i2c (i2c_m_in, i2c_m_out, C_I2C_MASTER_SLV_ADDR, CH1LTSCYR, "CH1LTSCY", i2c_master_rcvd_val, i2c_master_rcvd_val1, TRUE, err);
......@@ -639,7 +646,9 @@ begin
glitch_filter_en := '1';
ttl_out_bar_en := '0';
settings_config (glitch_filter_en, ttl_out_bar_en, sw_gp_n_in, sw_other_in, pcbrev, rtm_in);
generate_pulse (ttl_n_in(3), nb_pulses_to_send_fp, "fp", rs485_fs_n_in(3), 50ns, 50ns);
wait for 2 us; -- ML: does not work without this wait, no idea way?
print_now_s_i("Sending pulses 50ns-long each to TTL_N_I(3): ", nb_pulses_to_send_fp);
generate_pulse (ttl_n_in(3), nb_pulses_to_send_fp, "fp", rs485_fs_n_in(3), 50ns, 20ns);
-- Checking if any pulse was passed to the output
print_now("Check that the glitches were filtered and there is no pulse in the TTL_O(3) output");
......@@ -664,26 +673,32 @@ begin
glitch_filter_en := '0';
ttl_out_bar_en := '1';
settings_config (glitch_filter_en, ttl_out_bar_en, sw_gp_n_in, sw_other_in, pcbrev, rtm_in);
generate_pulse (ttl_n_in(4), nb_pulses_to_send_fp, "fp", rs485_fs_n_in(4), 200ns, 200ns);
rst_copm <= '1';
wait for 2 us; -- ML: does not work without this wait, no idea way?
rst_copm <= '0';
-- Checking if any pulse was passed to the output
print_now("Check that ...");
if pulse_cnt_ttl(4) = 0 then
print_now("[OK] Glitch filter filtered the glitches");
generate_pulse (ttl_n_in(5), nb_pulses_to_send_bar, "fp", rs485_fs_n_in(5), 200ns, 200ns);
-- Check if TTL_N_IN out and TTL_O out are the same
print_now("Check that TTL_O(5) matches TTL_N_IN(5)");
if in_out_same(5) = 0 then
print_now("[OK] TTL_O(5) matches TTL_N_IN(5)");
else
print_now_s_i("[ERR] Number of pulses measured at TTL_O(3): ",pulse_cnt_ttl(3));
print_now("[ERR] TTL_O(5) does not match TTL_N_IN(5)");
err_cnt := err_cnt + 1;
end if;
---------------------------------------------------------------------------
print_now_s_i("Errors so far: ", err_cnt);
---------------------------------------------------------------------------
wait for 1 us;
print("*****************************************************************************");
print(" Tests Summary");
print("*****************************************************************************");
print_now_s_i("Total number of errors: ", err_cnt);
print("*****************************************************************************");
wait for 500 us;
end process p_stim;
......
sim/testbench_pkg.vhd
View file @ 7d1e1f2c
......@@ -142,6 +142,7 @@ package testbench_pkg is
-- Components declarations
--============================================================================
component conv_ttl_rs485 is
generic (g_simul : boolean := FALSE);
port
(
-- Clocks
......@@ -301,21 +302,21 @@ package body testbench_pkg is
signal pcbrev : out std_logic_vector(5 downto 0);
signal rtm : out std_logic_vector(5 downto 0)) is
begin
sw_gp_n(7) <= glitch_filter_en;
sw_gp_n(0) <= not glitch_filter_en;
if glitch_filter_en = '1' then
print_now("Glitch filter enabled");
else
print_now("Glitch filter disabled");
end if;
sw_gp_n(0) <= ttl_out_bar_en;
sw_gp_n(7) <= ttl_out_bar_en;
if ttl_out_bar_en = '1' then
print_now("TTL output BAR enabled");
else
print_now("TTL output BAR disabled");
end if;
print_now_s_std("RTMP & RTMM set to x", C_RTM);
--print_now_s_std("RTMP & RTMM set to x", C_RTM);
sw_gp_n(6 downto 1) <= (others => '0'); -- not used
sw_other <= (others => '0'); -- not used
......
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