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Conv TTL RS485 - Gateware
Commit 515449df authored by Evangelia Gousiou's avatar Evangelia Gousiou
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WIP: testbench

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sim/i2c_bus_model.vhd 0 → 100644
View file @ 515449df
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C bus model
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-11-27
--
-- version: 1.0
--
-- description:
-- A very simple I2C bus model for use in simulation, implementing the
-- wired-AND on the I2C protocol.
--
-- Masters and slaves should implement the buffers internally and connect the
-- SCL and SDA lines to the input ports of this model, as below:
-- - masters should connect to mscl_i and msda_i
-- - slaves should connect to sscl_i and ssda_i
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-11-27 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_bus_model is
generic
(
g_nr_masters : positive := 1;
g_nr_slaves : positive := 1
);
port
(
-- Input ports from master lines
mscl_i : in std_logic_vector(g_nr_masters-1 downto 0);
msda_i : in std_logic_vector(g_nr_masters-1 downto 0);
-- Input ports from slave lines
sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0);
ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0);
-- SCL and SDA line outputs
scl_o : out std_logic;
sda_o : out std_logic
);
end entity i2c_bus_model;
architecture behav of i2c_bus_model is
--==============================================================================
-- architecture begin
--==============================================================================
begin
scl_o <= '1' when (mscl_i = (mscl_i'range => '1')) and
(sscl_i = (sscl_i'range => '1')) else
'0';
sda_o <= '1' when (msda_i = (msda_i'range => '1')) and
(ssda_i = (ssda_i'range => '1')) else
'0';
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
sim/i2c_master_and_driver.vhd 0 → 100644
View file @ 515449df
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- I2C master and its driver
-- https://www.ohwr.org/projects/conv-common-gw
--------------------------------------------------------------------------------
--
-- unit name: Top-level simulation of conv_common_gw
--
-- description:
--
--
--
--------------------------------------------------------------------------------
-- Copyright (c) 2010-2012 CERN / BE-CO-HT
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity i2c_master_and_driver is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Driver interface
ready_o : out std_logic;
start_i : in std_logic;
finish_o : out std_logic;
rdwr_i : in std_logic; -- 1: read, 0: write
slv_addr_i : in std_logic_vector(6 downto 0);
reg_addr_i : in std_logic_vector(31 downto 0);
send_val_i : in std_logic_vector(31 downto 0);
rcvd_val_o : out std_logic_vector(31 downto 0);
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_oen : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oen : out std_logic
);
end entity i2c_master_and_driver;
architecture arch of i2c_master_and_driver is
type t_state_i2c_mst is
(
IDLE,
I2C_ADDR, I2C_ADDR_ACK,
WB_ADDR_B0, WB_ADDR_B0_ACK,
WB_ADDR_B1, WB_ADDR_B1_ACK,
ST_OP,
RD_RESTART, RD_RESTART_ACK,
RD, RD_ACK,
WR, WR_ACK,
STO,
SUCCESS,
ERR
);
-- I2C signals
signal state_i2c_mst : t_state_i2c_mst;
signal mst_sta : std_logic;
signal mst_sto : std_logic;
signal mst_rd : std_logic;
signal mst_wr : std_logic;
signal mst_ack : std_logic;
signal mst_dat_in : std_logic_vector(7 downto 0);
signal mst_dat_out : std_logic_vector(7 downto 0);
signal mst_cmd_ack : std_logic;
signal ack_fr_slv : std_logic;
signal cnt : unsigned(2 downto 0);
signal once : boolean;
signal byte_cnt : unsigned(1 downto 0);
signal rcvd : std_logic_vector(31 downto 0);
signal send : std_logic_vector(31 downto 0);
signal rst : std_logic;
begin
rst <= not rst_n_i;
-- from general-cores/modules/wishbone/wb_i2c_master/
cmp_master : entity work.i2c_master_byte_ctrl
port map(
clk => clk_i,
rst => rst,
nReset => rst_n_i,
ena => '1',
clk_cnt => x"0027",
-- input signals
start => mst_sta,
stop => mst_sto,
read => mst_rd,
write => mst_wr,
ack_in => mst_ack,
din => mst_dat_in,
-- output signals
cmd_ack => mst_cmd_ack,
ack_out => ack_fr_slv,
i2c_busy => open,
i2c_al => open,
dout => mst_dat_out,
-- i2c lines
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
------------------------------------------------------------------------------
-- This FSM controls the signals to the master component to implement the I2C
-- protocol defined together with ELMA. The FSM is controlled by the
-- stimuli process below
------------------------------------------------------------------------------
p_mst_fsm : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state_i2c_mst <= IDLE;
mst_sta <= '0';
mst_wr <= '0';
mst_sto <= '0';
mst_rd <= '0';
mst_dat_in <= (others => '0');
mst_ack <= '0';
cnt <= (others => '0');
once <= true;
byte_cnt <= (others => '0');
rcvd <= (others => '0');
send <= (others => '0');
ready_o <= '0';
finish_o <= '0';
else
case state_i2c_mst is
when IDLE =>
if (start_i = '1') then
state_i2c_mst <= I2C_ADDR;
send <= std_logic_vector(send_val_i);
ready_o <= '0';
else
ready_o <= '1';
end if;
finish_o <= '0';
when I2C_ADDR =>
mst_sta <= '1';
mst_wr <= '1';
mst_dat_in <= slv_addr_i & '0';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= I2C_ADDR_ACK;
end if;
when I2C_ADDR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B0;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B0 =>
mst_wr <= '1';
mst_dat_in <= reg_addr_i(15 downto 8);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B0_ACK;
end if;
when WB_ADDR_B0_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B1;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B1 =>
mst_wr <= '1';
mst_dat_in <= reg_addr_i(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B1_ACK;
end if;
when WB_ADDR_B1_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= ST_OP;
else
state_i2c_mst <= ERR;
end if;
end if;
when ST_OP =>
if (rdwr_i = '1') then
state_i2c_mst <= RD_RESTART;
else
state_i2c_mst <= WR;
end if;
when RD_RESTART =>
mst_wr <= '1';
mst_dat_in <= slv_addr_i & '1';
mst_sta <= '1';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= RD_RESTART_ACK;
end if;
when RD_RESTART_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= RD;
rcvd <= (others => '0');
else
state_i2c_mst <= ERR;
end if;
end if;
when RD =>
mst_rd <= '1';
mst_ack <= '0';
if (byte_cnt = 3) then
mst_ack <= '1';
end if;
if (mst_cmd_ack = '1') then
mst_rd <= '0';
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when RD_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when WR =>
mst_wr <= '1';
mst_dat_in <= send(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WR_ACK;
end if;
when WR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
byte_cnt <= byte_cnt + 1;
send <= x"00" & send(31 downto 8);
state_i2c_mst <= WR;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
else
state_i2c_mst <= ERR;
end if;
end if;
when STO =>
mst_sto <= '1';
if (mst_cmd_ack = '1') then
mst_sto <= '0';
state_i2c_mst <= IDLE;
end if;
finish_o <= '1';
when ERR =>
if (once) then
report("Error!");
once <= false;
end if;
when others =>
state_i2c_mst <= ERR;
end case;
end if;
end if;
end process p_mst_fsm;
rcvd_val_o <= rcvd;
end architecture arch;
sim/modelsim_lib.vhd 0 → 100644
View file @ 515449df
--------------------------------------------------------------------------------
-- Title : ModelSim library for Riviera-PRO
-- Project :
--------------------------------------------------------------------------------
-- File : modelsim_lib.vhd
-- Author : M. Henze
-- Email :
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created :
--------------------------------------------------------------------------------
-- Simulator : Riviera-PRO
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- CAUTION - this file shall not be used for new designs. It is only kept
-- for compliance with old designs.
-- For new designs use VHDL2008 syntax instead.
--
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
-- Copyright (C) 2016, MEN Mikro Elektronik Nuremberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
--------------------------------------------------------------------------------
LIBRARY aldec;
USE aldec.signal_agent_pkg.ALL;
USE aldec.aldec_tools.ALL;
----------------------------------------
-- CAUTION! Don't use for new designs!
-- Use VHDL2008 instead!
----------------------------------------
PACKAGE util IS
TYPE force_type IS (default, deposit, drive, freeze);
type del_mode is (MTI_INERTIAL, MTI_TRANSPORT);
PROCEDURE init_signal_spy( source : IN string;
destination : IN string;
verbose : IN integer;
control : IN integer);
procedure init_signal_spy(
source : in string;
dest : in string
);
PROCEDURE signal_force( destination : IN string;
value : IN string;
rel_time : IN time;
forcetype : IN force_type;
cancel_period : IN time;
verbose : IN integer);
PROCEDURE signal_release( destination : IN string;
verbose : IN integer);
procedure init_signal_driver(
src_obj : in string;
dest_obj : in string;
delay : in time;
delay_type : in del_mode;
verbose : in integer
);
END;
PACKAGE BODY util IS
PROCEDURE init_signal_spy( source : IN string;
destination : IN string;
verbose : IN integer;
control : IN integer) IS
BEGIN
signal_agent(source, destination ,verbose);
END PROCEDURE init_signal_spy;
procedure init_signal_spy(
source : in string;
dest : in string
) is
begin
signal_agent(source,dest,0);
end procedure init_signal_spy;
PROCEDURE signal_force( destination : IN string;
value : IN string;
rel_time : IN time;
forcetype : IN force_type;
cancel_period : IN time;
verbose : IN integer) IS
BEGIN
------------------------------------------------
-- in RivieraPRO2014 the force command changed
------------------------------------------------
--force(force_type'image(forcetype), destination, value);
force_signal(force_type'image(forcetype), destination, value);
END PROCEDURE signal_force;
PROCEDURE signal_release( destination : IN string;
verbose : IN integer) IS
BEGIN
------------------------------------------------
-- in RivieraPRO2014 the force command changed
------------------------------------------------
--noforce ( destination );
noforce_signal ( destination );
END PROCEDURE signal_release;
procedure init_signal_driver(
src_obj : in string;
dest_obj : in string;
delay : in time;
delay_type : in del_mode;
verbose : in integer
) is
begin
signal_agent(src_obj, dest_obj, 0);
end procedure init_signal_driver;
END;
sim/print_pkg.vhd 0 → 100644
View file @ 515449df
---------------------------------------------------------------
-- Title : Print Package
-- Project : none
---------------------------------------------------------------
-- File : print_pkg.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 26/08/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
-- several procedures and functions for screen printing
---------------------------------------------------------------
-- Hierarchy:
--
-- none
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.9 $
--
-- $Log: print_pkg.vhd,v $
-- Revision 1.9 2015/11/12 14:57:26 AGeissler
-- R1: Missing now procedure with one string
-- M1: Overload existing print_now_s with sting instead of integer
--
-- Revision 1.8 2015/11/12 13:56:46 AGeissler
-- R1: Missing character to std_logic_vector conversion function
-- M1: Added functions std_logic_vector_to_char and char_to_std_logic_vector
-- R2: Missing now procedures
-- M2: Added for each procedure a equivalent one, with an additional time print
--
-- Revision 1.7 2015/11/12 11:04:50 AGeissler
-- R1: The user shall decide, when and if spaces are used
-- M1: Removed spaces from print procedures
--
-- Revision 1.6 2015/03/10 10:20:34 AGeissler
-- R1: Improvement
-- M1.1: Added overloaded function for print_s_hb, print_s_hw, print_s_hl with std_logic_vector as parameter
-- M1.2: Replaced print_s_bit with print_s_std as a overloaded function with a std_logic as parameter
-- M1.3: Added short description for each function
--
-- Revision 1.5 2015/03/10 09:25:56 AGeissler
-- R1: Missing function to print an single bit
-- M1: Added function print_s_bit
--
-- Revision 1.4 2014/12/02 17:27:10 AGeissler
-- R1: Missing print functions for integer in hex with different sizes
-- M1: Added print functions print_s_hb, print_s_hw, print_s_hl
--
-- Revision 1.3 2014/11/24 11:26:00 AGeissler
-- R1: Missing function to print two strings for example text + time
-- (print_s(" it took ", time'image(tmp_time));)
-- M1: Added procedure print_s
--
-- Revision 1.2 2006/03/01 09:34:09 mmiehling
-- added print_now_s
--
-- Revision 1.1 2005/10/20 10:42:26 mmiehling
-- Initial Revision
--
-- Revision 1.1 2005/09/15 12:05:59 MMiehling
-- Initial Revision
--
-- Revision 1.2 2004/05/13 14:22:49 MMiehling
-- multifunction device support
--
-- Revision 1.1 2004/04/14 09:42:28 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_textio.all;
USE ieee.numeric_std.all;
LIBRARY std;
USE std.textio.all;
PACKAGE print_pkg IS
PROCEDURE print_mtest ( source : string;
address : std_logic_vector;
is_data : std_logic_vector;
should_data : std_logic_vector;
arg : boolean);
PROCEDURE print (s: IN string);
PROCEDURE print_s (s: IN string; s2: IN string);
PROCEDURE print_s_s (s: IN string; s2: IN string; s3: IN string);
PROCEDURE print_s_i (s: IN string; s2: IN integer);
PROCEDURE print_s_h (s: IN string; s2: IN integer);
PROCEDURE print_s_hb (s: IN string; s2: IN integer);
PROCEDURE print_s_hw (s: IN string; s2: IN integer);
PROCEDURE print_s_hl (s: IN string; s2: IN integer);
PROCEDURE print_s_hb (s: IN string; s2: IN std_logic_vector(7 DOWNTO 0));
PROCEDURE print_s_hw (s: IN string; s2: IN std_logic_vector(15 DOWNTO 0));
PROCEDURE print_s_hl (s: IN string; s2: IN std_logic_vector(31 DOWNTO 0));
PROCEDURE print_s_dl (s: IN string; s2: IN std_logic_vector);
PROCEDURE print_cycle ( header : string;
address : std_logic_vector;
data : std_logic_vector;
sel_o_int : std_logic_vector(3 DOWNTO 0);
ende : string);
PROCEDURE print_s_std (s: IN string; bit: IN std_logic);
PROCEDURE print_s_std (s: IN string; vec: IN std_logic_vector);
PROCEDURE print_time (s: IN string);
PROCEDURE print_sum (intext: IN string; mstr_err: IN integer; wb_err: IN integer);
-- now procedures
PROCEDURE print_now (s: IN string);
PROCEDURE print_now_s (s: IN string; s2: IN integer);
PROCEDURE print_now_s (s: IN string; s2: IN string);
PROCEDURE print_now_s_s (s: IN string; s2: IN string; s3: IN string);
PROCEDURE print_now_s_i (s: IN string; s2: IN integer);
PROCEDURE print_now_s_h (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hb (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hw (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hl (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hb (s: IN string; s2: IN std_logic_vector(7 DOWNTO 0));
PROCEDURE print_now_s_hw (s: IN string; s2: IN std_logic_vector(15 DOWNTO 0));
PROCEDURE print_now_s_hl (s: IN string; s2: IN std_logic_vector(31 DOWNTO 0));
PROCEDURE print_now_s_dl (s: IN string; s2: IN std_logic_vector);
PROCEDURE print_now_s_std (s: IN string; bit: IN std_logic);
PROCEDURE print_now_s_std (s: IN string; vec: IN std_logic_vector);
FUNCTION char_to_std_logic_vector(arg : character) RETURN std_logic_vector;
FUNCTION std_logic_vector_to_char(arg : std_logic_vector(7 DOWNTO 0)) RETURN character;
END print_pkg;
PACKAGE BODY print_pkg IS
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string with the current simulation time
PROCEDURE print_time(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITELINE(output,l);
END print_time;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic
PROCEDURE print_s_std(s: IN string; bit: IN std_logic) IS
VARIABLE l: line;
VARIABLE s2: string(1 TO 3);
BEGIN
WRITE(l, s);
IF bit = '1' THEN
s2 := "'1'";
ELSE
s2 := "'0'";
END IF;
WRITE(l, s2);
WRITELINE(output,l);
END print_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_s_std(s: IN string; vec: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, vec);
WRITELINE(output,l);
END print_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print wishbone information
PROCEDURE print_cycle( header : string;
address : std_logic_vector;
data : std_logic_vector;
sel_o_int: std_logic_vector(3 DOWNTO 0);
ende : string) IS
VARIABLE l : line;
BEGIN
WRITE(l,header);
WRITE(l,string'(" "));
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l,string'(" ADR: "));
HWRITE(l,address,justified=>left);
WRITE(l,string'(" DATA: "));
IF address(1) = '0' THEN
CASE sel_o_int IS
WHEN "1111" => HWRITE(l,data);
WHEN "0001" => HWRITE(l,data(7 DOWNTO 0));
WRITE(l,string'(" "));
WHEN "0010" => HWRITE(l,data(15 DOWNTO 8));
WRITE(l,string'(" "));
WHEN "0100" => HWRITE(l,data(23 DOWNTO 16));
WRITE(l,string'(" "));
WHEN "1000" => HWRITE(l,data(31 DOWNTO 24));
WRITE(l,string'(" "));
WHEN "0011" => HWRITE(l,data(15 DOWNTO 0));
WRITE(l,string'(" "));
WHEN "1100" => HWRITE(l,data(31 DOWNTO 16));
WRITE(l,string'(" "));
WHEN OTHERS => ASSERT FALSE REPORT "PRINT_PKG Error: sel_o is undefined" SEVERITY error;
END CASE;
ELSE
HWRITE(l,data);
END IF;
WRITE(l,string'(" "));
WRITE(l,ende);
WRITELINE(output,l);
END print_cycle;
----------------------------------------------------------------------------------------------------------------------------------------
-- print the result of a memory test
PROCEDURE print_mtest( source : string;
address : std_logic_vector;
is_data : std_logic_vector;
should_data : std_logic_vector;
arg : boolean) IS
VARIABLE tranx : line;
BEGIN
WRITE(tranx,source);
WRITE(tranx,now, justified=>right,field =>10, unit=> ns );
WRITE(tranx,string'(" Memory Test "));
WRITE(tranx,string'(" ADR: "));
HWRITE(tranx,address,justified=>left);
IF NOT arg THEN
WRITE(tranx,string'(" DATA should be: "));
HWRITE(tranx,should_data);
WRITE(tranx, string'(" is "));
ELSE
WRITE(tranx,string'(" DATA: "));
END IF;
HWRITE(tranx,is_data);
WRITE(tranx,string'(" "));
IF arg THEN
WRITE(tranx,string'("OK"));
ELSE
WRITE(tranx,string'("ERROR!"));
END IF;
WRITELINE(output,tranx);
END print_mtest;
----------------------------------------------------------------------------------------------------------------------------------------
-- print string
PROCEDURE print(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITELINE(output,l);
END print;
----------------------------------------------------------------------------------------------------------------------------------------
-- print two strings (for example to print string and time = print_s(" it took ", time'image(tmp_time));
PROCEDURE print_s(s: IN string;s2: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print three strings (for example to print string, value and type = print_s(" it took ", integer, "ns");
PROCEDURE print_s_s(s: IN string; s2: IN string; s3: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITE(l, s3);
WRITELINE(output,l);
END print_s_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a integer as a decimal number
PROCEDURE print_s_i(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_s_i;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits (equal to print_s_hl but is needed to be backward compatible)
PROCEDURE print_s_h(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_s_h;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 2 digits
PROCEDURE print_s_hb(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,8)));
WRITELINE(output,l);
END print_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 4 digits
PROCEDURE print_s_hw(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,16)));
WRITELINE(output,l);
END print_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits
PROCEDURE print_s_hl(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 2 digits
PROCEDURE print_s_hb(s: IN string;s2: IN std_logic_vector(7 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 4 digits
PROCEDURE print_s_hw(s: IN string;s2: IN std_logic_vector(15 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 8 digits
PROCEDURE print_s_hl(s: IN string;s2: IN std_logic_vector(31 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a decimal number
PROCEDURE print_s_dl(s: IN string;s2: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, to_integer(unsigned(s2)));
WRITELINE(output,l);
END print_s_dl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print the result of a test case
PROCEDURE print_sum(intext: IN string; mstr_err: IN integer; wb_err: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, string'(" "));
WRITELINE(output,l);
IF mstr_err = 0 AND wb_err = 0 THEN
WRITE(l, string'(" P A S S "));
WRITE(l, intext);
WRITELINE(output,l);
ELSE
WRITE(l, string'(" F A I L "));
WRITE(l, intext);
WRITELINE(output,l);
WRITE(l, string'(" Number of PCI errors: "));
WRITE(l, mstr_err);
WRITELINE(output,l);
WRITE(l, string'(" Number of WB errors: "));
WRITE(l, wb_err);
WRITELINE(output,l);
END IF;
WRITE(l, string'("*************************************************************************************************************"));
WRITELINE(output,l);
END print_sum;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string with the current simulation time
PROCEDURE print_now(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITELINE(output,l);
END print_now;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and an integer as decimal number withthe current simulation time
PROCEDURE print_now_s(s: IN string; s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print two strings (for example to print string and time = print_s(" it took ", time'image(tmp_time));
PROCEDURE print_now_s(s: IN string;s2: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print three strings (for example to print string, value and type = print_s(" it took ", integer, "ns");
PROCEDURE print_now_s_s(s: IN string; s2: IN string; s3: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITE(l, s3);
WRITELINE(output,l);
END print_now_s_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a integer as a decimal number
PROCEDURE print_now_s_i(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s_i;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits (equal to print_s_hl but is needed to be backward compatible)
PROCEDURE print_now_s_h(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_now_s_h;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 2 digits
PROCEDURE print_now_s_hb(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,8)));
WRITELINE(output,l);
END print_now_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 4 digits
PROCEDURE print_now_s_hw(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,16)));
WRITELINE(output,l);
END print_now_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits
PROCEDURE print_now_s_hl(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_now_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 2 digits
PROCEDURE print_now_s_hb(s: IN string;s2: IN std_logic_vector(7 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 4 digits
PROCEDURE print_now_s_hw(s: IN string;s2: IN std_logic_vector(15 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 8 digits
PROCEDURE print_now_s_hl(s: IN string;s2: IN std_logic_vector(31 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a decimal number
PROCEDURE print_now_s_dl(s: IN string;s2: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, to_integer(unsigned(s2)));
WRITELINE(output,l);
END print_now_s_dl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic
PROCEDURE print_now_s_std(s: IN string; bit: IN std_logic) IS
VARIABLE l: line;
VARIABLE s2: string(1 TO 3);
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
IF bit = '1' THEN
s2 := "'1'";
ELSE
s2 := "'0'";
END IF;
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_now_s_std(s: IN string; vec: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, vec);
WRITELINE(output,l);
END print_now_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- function to convert character to std_logic_vector
FUNCTION char_to_std_logic_vector( arg : character) RETURN std_logic_vector IS
BEGIN
RETURN std_logic_vector(to_unsigned(character'POS(arg), 8));
END FUNCTION char_to_std_logic_vector;
----------------------------------------------------------------------------------------------------------------------------------------
-- function to convert std_logic_vector to character
FUNCTION std_logic_vector_to_char( arg : std_logic_vector(7 DOWNTO 0) ) RETURN character IS
BEGIN
CASE arg IS
-- NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
-- BS, HT, LF, VT, FF, CR, SO, SI,
WHEN "00000000" =>
RETURN NUL;
WHEN "00000001" =>
RETURN SOH;
WHEN "00000010" =>
RETURN STX;
WHEN "00000011" =>
RETURN ETX;
WHEN "00000100" =>
RETURN EOT;
WHEN "00000101"=>
RETURN ENQ;
WHEN "00000110" =>
RETURN ACK;
WHEN "00000111" =>
RETURN BEL;
WHEN "00001000" =>
RETURN BS;
WHEN "00001001" =>
RETURN HT;
WHEN "00001010" =>
RETURN LF;
WHEN "00001011" =>
RETURN VT;
WHEN "00001100" =>
RETURN FF;
WHEN "00001101" =>
RETURN CR;
WHEN "00001110" =>
RETURN SO;
WHEN "00001111" =>
RETURN SI;
-- DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
-- CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
WHEN "00010000" =>
RETURN DLE;
WHEN "00010001" =>
RETURN DC1;
WHEN "00010010" =>
RETURN DC2;
WHEN "00010011" =>
RETURN DC3;
WHEN "00010100" =>
RETURN DC4;
WHEN "00010101" =>
RETURN NAK;
WHEN "00010110" =>
RETURN SYN;
WHEN "00010111" =>
RETURN ETB;
WHEN "00011000" =>
RETURN CAN;
WHEN "00011001" =>
RETURN EM;
WHEN "00011010" =>
RETURN SUB;
WHEN "00011011" =>
RETURN ESC;
WHEN "00011100" =>
RETURN FSP;
WHEN "00011101" =>
RETURN GSP;
WHEN "00011110" =>
RETURN RSP;
WHEN "00011111" =>
RETURN USP;
-- ' ', '!', '"', '#', '$', '%', '&', ''',
-- '(', ')', '*', '+', ',', '-', '.', '/',
WHEN "00100000" =>
RETURN ' ';
WHEN "00100001" =>
RETURN '!';
WHEN "00100010" =>
RETURN '"'; --"
WHEN "00100011" =>
RETURN '#';
WHEN "00100100" =>
RETURN '$';
WHEN "00100101" =>
RETURN '%';
WHEN "00100110" =>
RETURN '&';
WHEN "00100111" =>
RETURN ''';
WHEN "00101000" =>
RETURN '(';
WHEN "00101001" =>
RETURN ')';
WHEN "00101010" =>
RETURN '*';
WHEN "00101011" =>
RETURN '+';
WHEN "00101100" =>
RETURN ',';
WHEN "00101101" =>
RETURN '-';
WHEN "00101110" =>
RETURN '.';
WHEN "00101111" =>
RETURN '/';
-- '0', '1', '2', '3', '4', '5', '6', '7',
-- '8', '9', ':', ';', '<', '=', '>', '?',
WHEN "00110000" =>
RETURN '0';
WHEN "00110001" =>
RETURN '1';
WHEN "00110010" =>
RETURN '2';
WHEN "00110011" =>
RETURN '3';
WHEN "00110100" =>
RETURN '4';
WHEN "00110101" =>
RETURN '5';
WHEN "00110110" =>
RETURN '6';
WHEN "00110111" =>
RETURN '7';
WHEN "00111000" =>
RETURN '8';
WHEN "00111001" =>
RETURN '9';
WHEN "00111010" =>
RETURN ':';
WHEN "00111011" =>
RETURN ';';
WHEN "00111100" =>
RETURN '<';
WHEN "00111101" =>
RETURN '=';
WHEN "00111110" =>
RETURN '>';
WHEN "00111111" =>
RETURN '?';
-- '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
-- 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
WHEN "01000000" =>
RETURN '@';
WHEN "01000001" =>
RETURN 'A';
WHEN "01000010" =>
RETURN 'B';
WHEN "01000011" =>
RETURN 'C';
WHEN "01000100" =>
RETURN 'D';
WHEN "01000101" =>
RETURN 'E';
WHEN "01000110" =>
RETURN 'F';
WHEN "01000111" =>
RETURN 'G';
WHEN "01001000" =>
RETURN 'H';
WHEN "01001001" =>
RETURN 'I';
WHEN "01001010" =>
RETURN 'J';
WHEN "01001011" =>
RETURN 'K';
WHEN "01001100" =>
RETURN 'L';
WHEN "01001101" =>
RETURN 'M';
WHEN "01001110" =>
RETURN 'N';
WHEN "01001111" =>
RETURN 'O';
-- 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
-- 'X', 'Y', 'Z', '[', '\', ']', '^', '_',
WHEN "01010000" =>
RETURN 'P';
WHEN "01010001" =>
RETURN 'Q';
WHEN "01010010" =>
RETURN 'R';
WHEN "01010011" =>
RETURN 'S';
WHEN "01010100" =>
RETURN 'T';
WHEN "01010101" =>
RETURN 'U';
WHEN "01010110" =>
RETURN 'V';
WHEN "01010111" =>
RETURN 'W';
WHEN "01011000" =>
RETURN 'X';
WHEN "01011001" =>
RETURN 'Y';
WHEN "01011010" =>
RETURN 'Z';
WHEN "01011011" =>
RETURN '[';
WHEN "01011100" =>
RETURN '\';
WHEN "01011101" =>
RETURN ']';
WHEN "01011110" =>
RETURN '^';
WHEN "01011111" =>
RETURN '_';
-- '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
-- 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
WHEN "01100000" =>
RETURN '`';
WHEN "01100001" =>
RETURN 'a';
WHEN "01100010" =>
RETURN 'b';
WHEN "01100011" =>
RETURN 'c';
WHEN "01100100" =>
RETURN 'd';
WHEN "01100101" =>
RETURN 'e';
WHEN "01100110" =>
RETURN 'f';
WHEN "01100111" =>
RETURN 'g';
WHEN "01101000" =>
RETURN 'h';
WHEN "01101001" =>
RETURN 'i';
WHEN "01101010" =>
RETURN 'j';
WHEN "01101011" =>
RETURN 'k';
WHEN "01101100" =>
RETURN 'l';
WHEN "01101101" =>
RETURN 'm';
WHEN "01101110" =>
RETURN 'n';
WHEN "01101111" =>
RETURN 'o';
-- 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
-- 'x', 'y', 'z', '{', '|', '}', '~', DEL,
WHEN "01110000" =>
RETURN 'p';
WHEN "01110001" =>
RETURN 'q';
WHEN "01110010" =>
RETURN 'r';
WHEN "01110011" =>
RETURN 's';
WHEN "01110100" =>
RETURN 't';
WHEN "01110101" =>
RETURN 'u';
WHEN "01110110" =>
RETURN 'v';
WHEN "01110111" =>
RETURN 'w';
WHEN "01111000" =>
RETURN 'x';
WHEN "01111001" =>
RETURN 'y';
WHEN "01111010" =>
RETURN 'z';
WHEN "01111011" =>
RETURN '{';
WHEN "01111100" =>
RETURN '|';
WHEN "01111101" =>
RETURN '}';
WHEN "01111110" =>
RETURN '~';
WHEN "01111111" =>
RETURN DEL;
WHEN OTHERS =>
RETURN '0';
END CASE;
-- missing characters:
-- C128, C129, C130, C131, C132, C133, C134, C135,
-- C136, C137, C138, C139, C140, C141, C142, C143,
-- C144, C145, C146, C147, C148, C149, C150, C151,
-- C152, C153, C154, C155, C156, C157, C158, C159,
-- ' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
-- '¨', '©', 'ª', '«', '¬', '­', '®', '¯',
-- '°', '±', '²', '³', '´', 'µ', '¶', '·',
-- '¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
-- 'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
-- 'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
-- 'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
-- 'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
-- 'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
-- 'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
-- 'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
-- 'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ');
END FUNCTION std_logic_vector_to_char;
END;
\ No newline at end of file
sim/run.do 0 → 100644
View file @ 515449df
vlib work
vsim -t 1 ms -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
#add wave *
do wave.do
run 1 ms
wave zoomfull
sim/testbench.vhd
View file @ 515449df
--==============================================================================
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Testbench for CONV-TTL-BLO design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-02-18
-- Converter Common Gateware
-- https://www.ohwr.org/projects/conv-common-gw
--------------------------------------------------------------------------------
--
-- version: 1.0
-- unit name: Top-level simulation of conv_common_gw
--
-- description:
-- Design-wide simulation testbench for the CONV-TTL-BLO gateware. Currently
-- simulated features include:
-- - pulse triggering
-- - I2C master for reading register contents
--
-- dependencies:
-- None.
--
--
--==============================================================================
--------------------------------------------------------------------------------
-- Copyright (c) 2010-2012 CERN / BE-CO-HT
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -30,16 +24,14 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-02-18 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.conv_common_gw_pkg.all;
use work.testbench_pkg.all;
entity testbench is
......@@ -49,263 +41,102 @@ end entity testbench;
architecture behav of testbench is
--============================================================================
-- Type declarations
-- Functions and procedures
--============================================================================
type t_state_i2c_mst is
(
IDLE,
I2C_ADDR, I2C_ADDR_ACK,
WB_ADDR_B0, WB_ADDR_B0_ACK,
WB_ADDR_B1, WB_ADDR_B1_ACK,
ST_OP,
RD_RESTART, RD_RESTART_ACK,
RD, RD_ACK,
WR, WR_ACK,
STO,
SUCCESS,
ERR
);
--============================================================================
-- Constant declarations
-- Signal declarations
--============================================================================
-- Clock periods
constant c_clk_20_per : time := 50 ns;
constant c_clk_125_per : time := 8 ns;
-- Number of I2C masters and slaves for the I2C bus model
constant c_nr_masters : positive := 1;
constant c_nr_slaves : positive := 1;
type t_i2c_master_in is record
i2c_master_start : std_logic;
i2c_master_rdwr : std_logic;
i2c_master_slv_addr : std_logic_vector(6 downto 0);
i2c_master_reg_addr : std_logic_vector(31 downto 0);
i2c_master_send_val : std_logic_vector(31 downto 0);
end record;
--============================================================================
-- Component declarations
--============================================================================
component conv_ttl_blo is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4;
g_sim : boolean := false
);
port
(
-- Clocks
-- 20 MHz from VCXO
clk_20_vcxo_i : in std_logic;
-- 125 MHz from clock generator
fpga_clk_p_i : in std_logic;
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
type t_i2c_master_out is record
i2c_master_ready : std_logic;
i2c_master_finish : std_logic;
i2c_master_rcvd_val : std_logic_vector(31 downto 0);
end record;
signal clk_20, clk_125 : std_logic;
signal clk_125_p, clk_125_n : std_logic;
signal rst_n : std_logic := '0';
signal gf_en_n_in : std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
signal ttl_n_in, ttl_out : std_logic_vector(c_nr_chans-1 downto 0);
signal rs485_n_in : std_logic_vector(c_nr_chans-1 downto 0);
-- Blocking power supply reset line
mr_n_o : out std_logic;
-- signal sscl_in : std_logic;
-- signal ssda_in : std_logic;
signal sscl_out : std_logic;
signal sscl_en_out : std_logic;
signal ssda_out : std_logic;
signal ssda_en_out : std_logic;
-- Thermometer line
thermometer_b : inout std_logic;
-- signal mscl_in : std_logic;
-- signal msda_in : std_logic;
signal mscl_out : std_logic;
signal mscl_en_out : std_logic;
signal msda_out : std_logic;
signal msda_en_out : std_logic;
-- PLL DACs
-- DAC1: 20 MHz VCXO control
fpga_plldac1_din_o : out std_logic;
fpga_plldac1_sclk_o : out std_logic;
fpga_plldac1_sync_n_o : out std_logic;
-- DAC2: 125 MHz clock generator control
fpga_plldac2_din_o : out std_logic;
fpga_plldac2_sclk_o : out std_logic;
fpga_plldac2_sync_n_o : out std_logic;
signal sw_gp_n_in : std_logic_vector(7 downto 0);
signal sw_other_in : std_logic_vector(31 downto 0);
signal pcbrev : std_logic_vector(5 downto 0);
signal rtmm_in : std_logic_vector(2 downto 0);
signal rtmp_in : std_logic_vector(2 downto 0);
-- SFP lines
fpga_sfp_los_i : in std_logic;
fpga_sfp_mod_def0_i : in std_logic;
fpga_sfp_rate_select_o : out std_logic;
fpga_sfp_mod_def1_b : inout std_logic;
fpga_sfp_mod_def2_b : inout std_logic;
fpga_sfp_tx_disable_o : out std_logic;
fpga_sfp_tx_fault_i : in std_logic;
signal line_front_in : std_logic_vector(c_nr_chans-1 downto 0);
signal line_inv_in : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal line_rear_in : std_logic_vector(c_nr_chans-1 downto 0);
signal line_front_fs_in : std_logic_vector(c_nr_chans-1 downto 0);
signal line_inv_fs_in : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal line_rear_fs_in : std_logic_vector(c_nr_chans-1 downto 0);
signal i2c_master_rcvd_val, i2c_master_rcvd_val1,i2c_master_rcvd_val2, i2c_master_rcvd_val3, i2c_master_rcvd_val4 : std_logic_vector(31 downto 0);
signal i2c_master_rcvd_val_str : string(1 to 8);
signal i2c_m_in : t_i2c_master_in;
signal i2c_m_out : t_i2c_master_out;
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
);
end component conv_ttl_blo;
-- I2C bus model
component i2c_bus_model is
generic
(
g_nr_masters : positive := 1;
g_nr_slaves : positive := 1
);
port
(
-- Input ports from master lines
mscl_i : in std_logic_vector(g_nr_masters-1 downto 0);
msda_i : in std_logic_vector(g_nr_masters-1 downto 0);
-- Input ports from slave lines
sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0);
ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0);
-- SCL and SDA line outputs
scl_o : out std_logic;
sda_o : out std_logic
);
end component i2c_bus_model;
-- I2C master
component i2c_master_byte_ctrl is
port
(
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
--============================================================================
-- Signal declarations
--============================================================================
signal clk_20, clk_125 : std_logic;
signal clk_125_p, clk_125_n : std_logic;
signal rst_n, rst : std_logic;
signal pulse_led_front_n : std_logic_vector(6 downto 1);
signal pulse_led_front : std_logic_vector(6 downto 1);
signal pulse_led_rear_n : std_logic_vector(6 downto 1);
signal pulse_led_rear : std_logic_vector(6 downto 1);
signal ttl_inp_n, ttl_outp : std_logic_vector(6 downto 1);
signal ttl_pulse : std_logic_vector(6 downto 1);
signal inv_pulse : std_logic_vector(6 downto 1);
signal blo_inp, blo_outp : std_logic_vector(6 downto 1);
signal blo_pulse : std_logic_vector(6 downto 1);
signal oe, blo_oe, ttl_oe, inv_oe : std_logic;
signal ttl_switch_n : std_logic;
signal switches_n : std_logic_vector(7 downto 1);
-- I2C signals
signal state_i2c_mst : t_state_i2c_mst;
signal mst_fsm_op : std_logic;
signal mst_fsm_start : std_logic;
signal stim_cnt : unsigned(31 downto 0);
signal cnt : unsigned(2 downto 0);
signal buf_byte_cnt : integer;
signal once : boolean;
signal byte_cnt : unsigned(1 downto 0);
signal rcvd : std_logic_vector(31 downto 0);
signal send : std_logic_vector(31 downto 0);
signal send_val : std_logic_vector(31 downto 0);
signal wrote : std_logic;
signal slv_addr : std_logic_vector(6 downto 0);
signal adr : std_logic_vector(31 downto 0);
signal mst_sta : std_logic;
signal mst_sto : std_logic;
signal mst_rd : std_logic;
signal mst_wr : std_logic;
signal mst_ack : std_logic;
signal mst_dat_in : std_logic_vector(7 downto 0);
signal mst_dat_out : std_logic_vector(7 downto 0);
signal mst_cmd_ack : std_logic;
signal ack_fr_slv : std_logic;
signal mscl, msda : std_logic_vector(c_nr_masters-1 downto 0);
signal sscl, ssda : std_logic_vector(c_nr_slaves-1 downto 0);
signal scl, sda : std_logic;
---
signal buf_byte_cnt: integer;
signal scl_fr_mst : std_logic;
signal scl_en_mst : std_logic;
signal sda_fr_mst : std_logic;
signal sda_en_mst : std_logic;
signal scl_fr_slv : std_logic;
signal scl_en_slv : std_logic;
signal sda_fr_slv : std_logic;
signal sda_en_slv : std_logic;
signal t : boolean;
procedure read_i2c (signal i2c_m_in : out t_i2c_master_in;
signal i2c_m_out : in t_i2c_master_out;
constant slv_addr : in std_logic_vector(6 downto 0);
constant reg_addr : in std_logic_vector(31 downto 0);
signal rcvd_val : out std_logic_vector(31 downto 0)) is
begin
report "read_i2c: start ";
i2c_m_in.i2c_master_start <= '0';
i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
i2c_m_in.i2c_master_slv_addr <= "1011110";
i2c_m_in.i2c_master_reg_addr <= (others => '0');
i2c_m_in.i2c_master_send_val <= (others => '1');
wait for 50us;
i2c_m_in.i2c_master_slv_addr <= slv_addr;
i2c_m_in.i2c_master_reg_addr <= reg_addr;
i2c_m_in.i2c_master_start <= '1';
i2c_m_in.i2c_master_rdwr <= '1'; --0: write
wait for c_clk_20_per;
i2c_m_in.i2c_master_start <= '0';
wait until i2c_m_out.i2c_master_finish = '1';
rcvd_val <= i2c_m_out.i2c_master_rcvd_val;
report "-------> I2C value read from x... " & integer'image(to_integer(unsigned(i2c_m_out.i2c_master_rcvd_val)));
report "read_i2c: OK ";
wait for 50us;
end procedure read_i2c;
--==============================================================================
-- architecture begin
......@@ -313,7 +144,109 @@ architecture behav of testbench is
begin
--============================================================================
-- Generate clock signals
-- Instantiate DUT
--============================================================================
cmp_DUT: conv_ttl_rs485
port map
(
-- Clocks
clk_20_i => clk_20,
clk_125_p_i => clk_125_p,
clk_125_n_i => clk_125_n,
-- I2C interface
scl_i => scl,
scl_o => sscl_out,
scl_en_o => sscl_en_out,
sda_i => sda,
sda_o => ssda_out,
sda_en_o => ssda_en_out,
-- VME interface
vme_sysreset_n_i => rst_n,
vme_ga_i => "11110", --
vme_gap_i => '0',
-- PCB version recognition
pcbrev_i => pcbrev,
-- Channel enable
global_oen_o => open,
ttl_oen_o => open,
inv_oen_o => open,
rs485_oen_o => open,
-- Front panel channels
ttl_n_i => ttl_n_in, --: in std_logic_vector(5 downto 0);
ttl_o => ttl_out, --: out std_logic_vector(5 downto 0);
inv_n_i => (others => '0'), --inv_n_in, --: in std_logic_vector(3 downto 0);
inv_o => open, --inv_n_out, --: out std_logic_vector(3 downto 0);
-- Rear panel channels
rs485_n_i => rs485_n_in, --: in std_logic_vector(5 downto 0);
rs485_fs_n_i => (others => '0'), --: in std_logic_vector(5 downto 0); --failsafe?
rs485_o => open, --: out std_logic_vector(5 downto 0);
-- Rear input and output termination lines
iterm_en_o => open,
oterm_en_o => open,
-- Channel leds
led_front_n_o => open,
led_front_inv_n_o => open,
led_rear_n_o => open,
-- SPI interface to on-board flash chip
flash_cs_n_o => open,
flash_sclk_o => open,
flash_mosi_o => open,
flash_miso_i => 'Z',
-- PLL DACs
dac20_din_o => open,
dac20_sclk_o => open,
dac20_sync_n_o => open,
dac125_din_o => open,
dac125_sclk_o => open,
dac125_sync_n_o => open,
-- SFP lines
sfp_los_i => '1',
sfp_present_i => '0',
sfp_rate_select_o => open,
sfp_sda_b => open,
sfp_scl_b => open,
sfp_tx_disable_o => open,
sfp_tx_fault_i => '1',
-- Thermometer data port
thermometer_b => open,
-- Switches
sw_gp_n_i => sw_gp_n_in,
sw_multicast_n_i => (others => '0'), -- not used
-- RTM lines
rtmm_i => rtmm_in,
rtmp_i => rtmp_in,
-- Front panel bicolor LEDs
led_ctrl0_o => open,
led_ctrl0_oen_o => open,
led_ctrl1_o => open,
led_ctrl1_oen_o => open,
led_gp_2_4_o => open,
led_gp_1_3_o => open,
led_oterm_wr_o => open,
led_iterm_syserror_o => open,
led_gf_syspw_o => open,
led_ttl_i2c_o => open);
sscl(0) <= sscl_out when (sscl_en_out = '1') else '1';
ssda(0) <= ssda_out when (ssda_en_out = '1') else '1';
--============================================================================
-- Generate clock and reset signals
--============================================================================
p_clk_20 : process
begin
......@@ -333,233 +266,58 @@ begin
clk_125_p <= clk_125;
clk_125_n <= not clk_125;
--============================================================================
-- Instantiate the DUT
--============================================================================
cmp_dut : conv_ttl_blo
generic map
(
g_nr_ttl_chan => 6,
g_nr_inv_chan => 4,
g_sim => true
)
port map
(
-- Clocks
-- 20 MHz from VCXO
clk_20_vcxo_i => clk_20,
-- 125 MHz from clock generator
fpga_clk_p_i => clk_125_p,
fpga_clk_n_i => clk_125_n,
-- LEDs
led_ctrl0_o => open,
led_ctrl0_oen_o => open,
led_ctrl1_o => open,
led_ctrl1_oen_o => open,
led_multicast_2_0_o => open,
led_multicast_3_1_o => open,
led_wr_gmt_ttl_ttln_o => open,
led_wr_link_syserror_o => open,
led_wr_ok_syspw_o => open,
led_wr_ownaddr_i2c_o => open,
-- I/Os for pulses
pulse_front_led_n_o => pulse_led_front_n,
pulse_rear_led_n_o => pulse_led_rear_n,
fpga_input_ttl_n_i => ttl_inp_n,
fpga_out_ttl_o => ttl_outp,
fpga_blo_in_i => blo_inp,
fpga_trig_blo_o => blo_outp,
inv_in_n_i => (others => '1'),
inv_out_o => open,
-- Output enable lines
fpga_oe_o => oe,
fpga_blo_oe_o => blo_oe,
fpga_trig_ttl_oe_o => ttl_oe,
fpga_inv_oe_o => inv_oe,
--TTL/INV_TTL_N
ttl_switch_n_i => ttl_switch_n,
extra_switch_n_i => switches_n,
-- Lines for the i2c_slave
scl_i => scl,
scl_o => scl_fr_slv,
scl_oe_o => scl_en_slv,
sda_i => sda,
sda_o => sda_fr_slv,
sda_oe_o => sda_en_slv,
fpga_ga_i => "11110",
fpga_gap_i => '0',
-- Flash memory lines
fpga_prom_cclk_o => open,
fpga_prom_cso_b_n_o => open,
fpga_prom_mosi_o => open,
fpga_prom_miso_i => 'Z',
-- Blocking power supply reset line
mr_n_o => rst_n,
-- Thermometer line
thermometer_b => open,
-- PLL DACs
-- DAC1: 20 MHz VCXO control
fpga_plldac1_din_o => open,
fpga_plldac1_sclk_o => open,
fpga_plldac1_sync_n_o => open,
-- DAC2: 125 MHz clock generator control
fpga_plldac2_din_o => open,
fpga_plldac2_sclk_o => open,
fpga_plldac2_sync_n_o => open,
-- SFP lines
fpga_sfp_los_i => '1',
fpga_sfp_mod_def0_i => '1',
fpga_sfp_rate_select_o => open,
fpga_sfp_mod_def1_b => open,
fpga_sfp_mod_def2_b => open,
fpga_sfp_tx_disable_o => open,
fpga_sfp_tx_fault_i => '1',
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i => (others => '0'),
fpga_rtmp_n_i => (others => '0')
);
-- Tri-state buffers on the I2C lines
sscl(0) <= scl_fr_slv when (scl_en_slv = '1') else
'1';
ssda(0) <= sda_fr_slv when (sda_en_slv = '1') else
'1';
-- Active-high reset
rst <= not rst_n;
--============================================================================
-- Pulse outputs assignment based on OE signals
--============================================================================
ttl_pulse <= ttl_outp when (oe = '1') and (ttl_oe = '1') else (others => '0');
blo_pulse <= blo_outp when (oe = '1') and (blo_oe = '1') else (others => '0');
inv_pulse <= blo_outp when (oe = '1') and (inv_oe = '1') else (others => '0');
--============================================================================
-- Switches
--============================================================================
-- TTL
ttl_switch_n <= '0';
-- GF
switches_n(1) <= '0';
-- other
switches_n(7 downto 2) <= (others => '1');
--============================================================================
-- Pulse LEDs
--============================================================================
pulse_led_front <= not pulse_led_front_n;
pulse_led_rear <= not pulse_led_rear_n;
--============================================================================
-- Pulse stimuli
--============================================================================
blo_inp(6) <= '0';
ttl_inp_n(5 downto 1) <= (others => '1');
gen_pulse_chain : for i in 6 downto 2 generate
blo_inp(i-1) <= blo_outp(i);
end generate gen_pulse_chain;
p_stim_pulse : process
begin
ttl_inp_n(6) <= '1';
wait until t = true;
while (t = true) loop
wait for 240 us;
ttl_inp_n(6) <= '0';
wait for 500 ns;
ttl_inp_n(6) <= '1';
if ttl_outp(6) /= '1' then
assert false report "ttl_outp not '1'" severity warning;
end if;
if blo_outp(6) /= '1' then
assert false report "blo_outp not '1'" severity warning;
end if;
end loop;
end process p_stim_pulse;
process
p_rst_n: process
begin
t <= true;
wait for 2 ms;
t <= false;
wait for 500 ms;
t <= true;
wait for 10 ms;
t <= false;
rst_n <= '0';
wait for c_reset_width;
rst_n <= '1';
wait for c_reset_width;
rst_n <= '0';
wait for c_reset_width;
rst_n <= '1';
wait;
end process;
end process p_rst_n;
--============================================================================
-- I2C master
-- Instantiate I2C master to access DUT
--============================================================================
------------------------------------------------------------------------------
-- First, the component instantiation
------------------------------------------------------------------------------
cmp_master : i2c_master_byte_ctrl
port map
(
clk => clk_20,
rst => rst,
nReset => rst_n,
ena => '1',
clk_cnt => x"0027",
-- input signals
start => mst_sta,
stop => mst_sto,
read => mst_rd,
write => mst_wr,
ack_in => mst_ack,
din => mst_dat_in,
-- output signals
cmd_ack => mst_cmd_ack,
ack_out => ack_fr_slv,
i2c_busy => open,
i2c_al => open,
dout => mst_dat_out,
-- i2c lines
scl_i => scl,
scl_o => scl_fr_mst,
scl_oen => scl_en_mst,
sda_i => sda,
sda_o => sda_fr_mst,
sda_oen => sda_en_mst
);
-- Then, the tri-state_i2c_mst buffers on the line
mscl(0) <= scl_fr_mst when (scl_en_mst = '0') else
'1';
msda(0) <= sda_fr_mst when (sda_en_mst = '0') else
'1';
cmp_i2c_master_and_driver: entity work.i2c_master_and_driver
port map (
clk_i => clk_20,
rst_n_i => rst_n,
ready_o => i2c_m_out.i2c_master_ready,
start_i => i2c_m_in.i2c_master_start,
finish_o => i2c_m_out.i2c_master_finish,
rdwr_i => i2c_m_in.i2c_master_rdwr,
slv_addr_i => i2c_m_in.i2c_master_slv_addr,
reg_addr_i => i2c_m_in.i2c_master_reg_addr,
send_val_i => i2c_m_in.i2c_master_send_val,
rcvd_val_o => i2c_m_out.i2c_master_rcvd_val,
scl_i => scl,
scl_o => mscl_out,
scl_oen => mscl_en_out,
sda_i => sda,
sda_o => msda_out,
sda_oen => msda_en_out
);
-- Tri-state buffers on the I2C lines
mscl(0) <= mscl_out when (mscl_en_out = '0') else '1';
msda(0) <= msda_out when (msda_en_out = '0') else '1';
------------------------------------------------------------------------------
-- Bus model instantiation and connection to master and slaves
------------------------------------------------------------------------------
cmp_i2c_bus : i2c_bus_model
generic map
(
cmp_i2c_bus : entity work.i2c_bus_model
generic map(
g_nr_masters => c_nr_masters,
g_nr_slaves => c_nr_slaves
)
port map
(
port map (
mscl_i => mscl,
msda_i => msda,
sscl_i => sscl,
......@@ -567,227 +325,109 @@ begin
scl_o => scl,
sda_o => sda
);
--============================================================================
-- processes to provide stimulus and checks
--============================================================================
------------------------------------------------------------------------------
-- This FSM controls the signals to the master component to implement the I2C
-- protocol defined together with ELMA. The FSM is controlled by the
-- stimuli process below
------------------------------------------------------------------------------
p_mst_fsm : process (clk_20) is
--i2c access
p_stim_i2c : process
begin
if rising_edge(clk_20) then
if (rst_n = '0') then
state_i2c_mst <= IDLE;
mst_sta <= '0';
mst_wr <= '0';
mst_sto <= '0';
mst_rd <= '0';
mst_dat_in <= (others => '0');
mst_ack <= '0';
cnt <= (others => '0');
once <= true;
byte_cnt <= (others => '0');
rcvd <= (others => '0');
send <= (others => '0');
else
case state_i2c_mst is
when IDLE =>
if (mst_fsm_start = '1') then
state_i2c_mst <= I2C_ADDR;
send <= std_logic_vector(send_val);
end if;
when I2C_ADDR =>
mst_sta <= '1';
mst_wr <= '1';
mst_dat_in <= slv_addr & '0';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= I2C_ADDR_ACK;
end if;
when I2C_ADDR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B0;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B0 =>
mst_wr <= '1';
mst_dat_in <= adr(15 downto 8);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B0_ACK;
end if;
when WB_ADDR_B0_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B1;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B1 =>
mst_wr <= '1';
mst_dat_in <= adr(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B1_ACK;
end if;
when WB_ADDR_B1_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= ST_OP;
else
state_i2c_mst <= ERR;
end if;
end if;
when ST_OP =>
if (mst_fsm_op = '1') then
state_i2c_mst <= RD_RESTART;
else
state_i2c_mst <= WR;
end if;
when RD_RESTART =>
mst_wr <= '1';
mst_dat_in <= slv_addr & '1';
mst_sta <= '1';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= RD_RESTART_ACK;
end if;
when RD_RESTART_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= RD;
else
state_i2c_mst <= ERR;
end if;
end if;
when RD =>
mst_rd <= '1';
mst_ack <= '0';
if (byte_cnt = 3) then
mst_ack <= '1';
end if;
if (mst_cmd_ack = '1') then
mst_rd <= '0';
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when RD_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when WR =>
mst_wr <= '1';
mst_dat_in <= send(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WR_ACK;
end if;
when WR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
byte_cnt <= byte_cnt + 1;
send <= x"00" & send(31 downto 8);
state_i2c_mst <= WR;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
else
state_i2c_mst <= ERR;
end if;
end if;
when STO =>
mst_sto <= '1';
if (mst_cmd_ack = '1') then
mst_sto <= '0';
state_i2c_mst <= IDLE;
end if;
when ERR =>
if (once) then
report("Error!");
once <= false;
end if;
when others =>
state_i2c_mst <= ERR;
end case;
end if;
end if;
end process p_mst_fsm;
i2c_m_in.i2c_master_start <= '0';
i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
i2c_m_in.i2c_master_slv_addr <= "1011110";
i2c_m_in.i2c_master_reg_addr <= (others => '0');
i2c_m_in.i2c_master_send_val <= (others => '1');
wait until rst_n = '1';
report "started stimulus";
wait for 50us;
generate_pulses (ttl_n_in, 256);
read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0030", i2c_master_rcvd_val );
end process p_stim_i2c;
------------------------------------------------------------------------------
-- Process to "stimulate" the master FSM above
------------------------------------------------------------------------------
p_stim_mst_fsm : process (rst_n, t, state_i2c_mst)
begin
if (rst_n = '0') then
mst_fsm_start <= '0';
mst_fsm_op <= '0';
slv_addr <= "1011110";
adr <= (others => '0');
buf_byte_cnt <= 0;
elsif (not t) and (state_i2c_mst = IDLE) then
mst_fsm_start <= '1';
mst_fsm_op <= '1';
buf_byte_cnt <= buf_byte_cnt + 1;
case buf_byte_cnt is
when 0 =>
adr(11 downto 0) <= x"030";
when 1 =>
adr(11 downto 0) <= x"034";
when 2 =>
adr(11 downto 0) <= x"038";
when 3 =>
adr(11 downto 0) <= x"02c";
buf_byte_cnt <= 0;
when others =>
buf_byte_cnt <= 0;
end case;
else
mst_fsm_start <= '0';
end if;
end process p_stim_mst_fsm;
--i2c access
-- p_stim_i2c : process
-- begin
-- i2c_m_in.i2c_master_start <= '0';
-- i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
-- i2c_m_in.i2c_master_slv_addr <= "1011110";
-- i2c_m_in.i2c_master_reg_addr <= (others => '0');
-- i2c_m_in.i2c_master_send_val <= (others => '1');
-- wait until rst_n = '1';
-- report "started stimulus";
-- wait for 50us;
-- settings_config (sw_gp_n_in, sw_other_in, pcbrev, rtmm_in);
-- generate_pulses (ttl_n_in, 2000);
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0000", i2c_master_rcvd_val1 );
-- end process p_stim_i2c;
-- i2c access
-- p_stim_i2c : process
-- begin
-- i2c_m_in.i2c_master_start <= '0';
-- i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
-- i2c_m_in.i2c_master_slv_addr <= "1011110"; -- I2C slave base address??
-- i2c_m_in.i2c_master_reg_addr <= (others => '0');
-- i2c_m_in.i2c_master_send_val <= (others => '1');
-- wait until rst_n = '1';
-- report "started stimulus";
-- wait for 50us;
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0000", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0000" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_000C", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0000" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0034", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0000" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0038", i2c_master_rcvd_val );
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_002c", i2c_master_rcvd_val );
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_000C", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_000C" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0010", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0010" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0014", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0014" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- read_i2c (i2c_m_in, i2c_m_out, "1011110",x"0000_0018", i2c_master_rcvd_val );
-- report "-------> I2C value read from x0000_0018" & integer'image(to_integer(unsigned(i2c_master_rcvd_val)));
-- end process p_stim_i2c;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
sim/testbench_pkg.vhd 0 → 100644
View file @ 515449df
--==============================================================================
-- CERN (BE-CO-HT)
-- TTL-RS485 pkg package
--==============================================================================
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
package testbench_pkg is
--============================================================================
-- Constant declarations
--============================================================================
-- Clock periods
constant c_clk_20_per : time := 50 ns;
constant c_clk_125_per : time := 8 ns;
constant c_reset_width : time := 1 us;
-- DUT configuration (generics):
constant c_nr_chans : integer := 6;
constant c_nr_inv_chans : integer := 4;
constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
constant c_gwvers : std_logic_vector(7 downto 0) :=x"40";
-- Number of I2C masters and slaves for the I2C bus model
constant c_nr_masters : positive := 1;
constant c_nr_slaves : positive := 1;
--============================================================================
-- Types declarations
--============================================================================
type t_i2c_master_in is record
i2c_master_start : std_logic;
i2c_master_rdwr : std_logic;
i2c_master_slv_addr : std_logic_vector(6 downto 0);
i2c_master_reg_addr : std_logic_vector(31 downto 0);
i2c_master_send_val : std_logic_vector(31 downto 0);
end record;
type t_i2c_master_out is record
i2c_master_ready : std_logic;
i2c_master_finish : std_logic;
i2c_master_rcvd_val : std_logic_vector(31 downto 0);
end record;
--============================================================================
-- Components declarations
--============================================================================
component conv_ttl_rs485 is
port
(
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- VME interface
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- PCB version recognition
pcbrev_i : in std_logic_vector(5 downto 0);
-- Channel enable
global_oen_o : out std_logic;
ttl_oen_o : out std_logic;
inv_oen_o : out std_logic;
rs485_oen_o : out std_logic;
-- Front panel channels
ttl_n_i : in std_logic_vector(5 downto 0);
ttl_o : out std_logic_vector(5 downto 0);
inv_n_i : in std_logic_vector(3 downto 0);
inv_o : out std_logic_vector(3 downto 0);
-- Rear panel channels
rs485_n_i : in std_logic_vector(5 downto 0);
rs485_fs_n_i : in std_logic_vector(5 downto 0);
rs485_o : out std_logic_vector(5 downto 0);
-- Rear input and output termination lines
iterm_en_o : out std_logic_vector(5 downto 0);
oterm_en_o : out std_logic_vector(5 downto 0);
-- Channel leds
led_front_n_o : out std_logic_vector(5 downto 0);
led_front_inv_n_o : out std_logic_vector(3 downto 0);
led_rear_n_o : out std_logic_vector(5 downto 0);
-- SPI interface to on-board flash chip
flash_cs_n_o : out std_logic;
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o : out std_logic;
dac20_sclk_o : out std_logic;
dac20_sync_n_o : out std_logic;
-- 125 MHz clock generator control
dac125_din_o : out std_logic;
dac125_sclk_o : out std_logic;
dac125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
sfp_present_i : in std_logic;
sfp_rate_select_o : out std_logic;
sfp_scl_b : inout std_logic;
sfp_sda_b : inout std_logic;
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- Thermometer data port
thermometer_b : inout std_logic;
-- Switches
sw_gp_n_i : in std_logic_vector(7 downto 0);
sw_multicast_n_i : in std_logic_vector(3 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
-- Front panel bicolor LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_gp_2_4_o : out std_logic;
led_gp_1_3_o : out std_logic;
led_oterm_wr_o : out std_logic;
led_iterm_syserror_o : out std_logic;
led_gf_syspw_o : out std_logic;
led_ttl_i2c_o : out std_logic
);
end component conv_ttl_rs485;
-- procedure read_i2c (signal i2c_m_out : in t_i2c_master_out;
-- signal i2c_m_in : out t_i2c_master_in;
-- signal slv_addr : in std_logic_vector( 6 downto 0);
-- signal reg_addr : in std_logic_vector(31 downto 0);
-- signal rcvd_val : out std_logic_vector(31 downto 0));
procedure generate_pulses (signal ttl_n_out: out std_logic_vector (c_nr_chans-1 downto 0);
numb : natural);
end testbench_pkg;
package body testbench_pkg is
--==============================================================================
-- Procedures
--==============================================================================
-- procedure write_i2c (signal slv_addr: in std_logic_vector( 6 downto 0);
-- signal reg_addr: in std_logic_vector(31 downto 0);
-- signal send_val: in std_logic_vector(31 downto 0)) is
-- begin
-- wait until i2c_master_ready = '1';
-- i2c_master_slv_addr <= slv_addr;
-- i2c_master_reg_addr <= reg_addr;
-- i2c_master_send_val <= send_val;
-- i2c_master_start <= '1';
-- i2c_master_rdwr <= '0'; --0: write
-- wait until i2c_master_ready = '1';
-- report "write_i2c: OK";
-- end procedure write_i2c;
procedure settings_config (signal sw_gp_n_in : out std_logic_vector(7 downto 0);
signal sw_other_in : out std_logic_vector(31 downto 0);
signal pcbrev : out std_logic_vector(5 downto 0);
signal rtmm_in : out std_logic_vector(2 downto 0)) is
begin
wait for 2 us; -- does not work without this wait, no idea way ???
sw_gp_n_in(0) <= '1'; -- disable glitch filter ?
sw_gp_n_in(1) <= '1';
sw_gp_n_in(7 downto 2) <= (others => '0');
sw_other_in <= (others => '0');
pcbrev <= "111100";
rtmm_in <= (others => '0');
end procedure;
-- procedure read_i2c (signal i2c_m_out : in t_i2c_master_out;
-- signal i2c_m_in : out t_i2c_master_in;
-- signal slv_addr : in std_logic_vector( 6 downto 0);
-- signal reg_addr : in std_logic_vector(31 downto 0);
-- signal rcvd_val : out std_logic_vector(31 downto 0)) is
-- begin
-- report "read_i2c: start ";
-- i2c_m_in.i2c_master_start <= '0';
-- i2c_m_in.i2c_master_rdwr <= '0'; --mst_fsm_op
-- i2c_m_in.i2c_master_slv_addr <= "1011110";
-- i2c_m_in.i2c_master_reg_addr <= (others => '0');
-- i2c_m_in.i2c_master_send_val <= (others => '1');
-- wait for 50us;
-- i2c_m_in.i2c_master_slv_addr <= slv_addr;
-- i2c_m_in.i2c_master_reg_addr <= reg_addr;
-- i2c_m_in.i2c_master_start <= '1';
-- i2c_m_in.i2c_master_rdwr <= '1'; --0: write
-- wait for c_clk_20_per;
-- i2c_m_in.i2c_master_start <= '0';
-- wait until i2c_m_out.i2c_master_finish = '1';
-- rcvd_val <= i2c_m_out.i2c_master_rcvd_val;
-- report "-------> I2C value read from x... " & integer'image(to_integer(unsigned(i2c_m_out.i2c_master_rcvd_val)));
-- report "read_i2c: OK ";
-- wait for 50us;
-- end procedure read_i2c;
procedure generate_pulses (signal ttl_n_out: out std_logic_vector (c_nr_chans-1 downto 0);
numb : natural) is
variable numb_cnt : natural;
begin
numb_cnt := 0;
while not(numb_cnt = numb) loop
ttl_n_out <= (others => '1');
wait for 200 ns; --min period is 240us??
ttl_n_out <= (others => '0');
wait for 100 ns;
ttl_n_out <= (others => '1');
wait for 200 ns; --min period is 240us??
numb_cnt:= numb_cnt + 1;
end loop;
end procedure generate_pulses;
end;
-----------------------------------------------------------------------------------
syn/Release/conv_ttl_rs485.xise
View file @ 515449df
......@@ -54,6 +54,7 @@
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
......@@ -68,7 +69,9 @@
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
......@@ -94,6 +97,7 @@
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
......@@ -103,9 +107,9 @@
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -120,10 +124,12 @@
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -131,18 +137,20 @@
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_rs485|arch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/conv_ttl_rs485.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_rs485" xil_pn:valueState="non-default"/>
<property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gc_frequency_meter|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gc_frequency_meter" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -150,13 +158,18 @@
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="All" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
......@@ -164,6 +177,8 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
......@@ -194,10 +209,13 @@
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="gc_frequency_meter" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -211,15 +229,17 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="conv_ttl_rs485_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="conv_ttl_rs485_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="conv_ttl_rs485_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="conv_ttl_rs485_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="gc_frequency_meter_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="gc_frequency_meter_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="gc_frequency_meter_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="gc_frequency_meter_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -236,7 +256,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="gc_frequency_meter" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -257,8 +277,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench/cmp_DUT/cmp_sync_ffs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.gc_sync_ffs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -268,22 +288,28 @@
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="100 ps" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.gc_sync_ffs" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -292,7 +318,13 @@
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -306,6 +338,7 @@
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -316,17 +349,20 @@
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0x1FFF" xil_pn:valueState="non-default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behav" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
......@@ -348,525 +384,533 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/sim/top_level/testbench.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_regs_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../sim/testbench_pkg.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="142"/>
</file>
</files>
<bindings/>
......
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