Commit 515449df authored by Evangelia Gousiou's avatar Evangelia Gousiou

WIP: testbench

parent 32e5ada5
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C bus model
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-11-27
--
-- version: 1.0
--
-- description:
-- A very simple I2C bus model for use in simulation, implementing the
-- wired-AND on the I2C protocol.
--
-- Masters and slaves should implement the buffers internally and connect the
-- SCL and SDA lines to the input ports of this model, as below:
-- - masters should connect to mscl_i and msda_i
-- - slaves should connect to sscl_i and ssda_i
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-11-27 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_bus_model is
generic
(
g_nr_masters : positive := 1;
g_nr_slaves : positive := 1
);
port
(
-- Input ports from master lines
mscl_i : in std_logic_vector(g_nr_masters-1 downto 0);
msda_i : in std_logic_vector(g_nr_masters-1 downto 0);
-- Input ports from slave lines
sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0);
ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0);
-- SCL and SDA line outputs
scl_o : out std_logic;
sda_o : out std_logic
);
end entity i2c_bus_model;
architecture behav of i2c_bus_model is
--==============================================================================
-- architecture begin
--==============================================================================
begin
scl_o <= '1' when (mscl_i = (mscl_i'range => '1')) and
(sscl_i = (sscl_i'range => '1')) else
'0';
sda_o <= '1' when (msda_i = (msda_i'range => '1')) and
(ssda_i = (ssda_i'range => '1')) else
'0';
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
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--------------------------------------------------------------------------------
-- Title : ModelSim library for Riviera-PRO
-- Project :
--------------------------------------------------------------------------------
-- File : modelsim_lib.vhd
-- Author : M. Henze
-- Email :
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created :
--------------------------------------------------------------------------------
-- Simulator : Riviera-PRO
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- CAUTION - this file shall not be used for new designs. It is only kept
-- for compliance with old designs.
-- For new designs use VHDL2008 syntax instead.
--
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
-- Copyright (C) 2016, MEN Mikro Elektronik Nuremberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
--------------------------------------------------------------------------------
LIBRARY aldec;
USE aldec.signal_agent_pkg.ALL;
USE aldec.aldec_tools.ALL;
----------------------------------------
-- CAUTION! Don't use for new designs!
-- Use VHDL2008 instead!
----------------------------------------
PACKAGE util IS
TYPE force_type IS (default, deposit, drive, freeze);
type del_mode is (MTI_INERTIAL, MTI_TRANSPORT);
PROCEDURE init_signal_spy( source : IN string;
destination : IN string;
verbose : IN integer;
control : IN integer);
procedure init_signal_spy(
source : in string;
dest : in string
);
PROCEDURE signal_force( destination : IN string;
value : IN string;
rel_time : IN time;
forcetype : IN force_type;
cancel_period : IN time;
verbose : IN integer);
PROCEDURE signal_release( destination : IN string;
verbose : IN integer);
procedure init_signal_driver(
src_obj : in string;
dest_obj : in string;
delay : in time;
delay_type : in del_mode;
verbose : in integer
);
END;
PACKAGE BODY util IS
PROCEDURE init_signal_spy( source : IN string;
destination : IN string;
verbose : IN integer;
control : IN integer) IS
BEGIN
signal_agent(source, destination ,verbose);
END PROCEDURE init_signal_spy;
procedure init_signal_spy(
source : in string;
dest : in string
) is
begin
signal_agent(source,dest,0);
end procedure init_signal_spy;
PROCEDURE signal_force( destination : IN string;
value : IN string;
rel_time : IN time;
forcetype : IN force_type;
cancel_period : IN time;
verbose : IN integer) IS
BEGIN
------------------------------------------------
-- in RivieraPRO2014 the force command changed
------------------------------------------------
--force(force_type'image(forcetype), destination, value);
force_signal(force_type'image(forcetype), destination, value);
END PROCEDURE signal_force;
PROCEDURE signal_release( destination : IN string;
verbose : IN integer) IS
BEGIN
------------------------------------------------
-- in RivieraPRO2014 the force command changed
------------------------------------------------
--noforce ( destination );
noforce_signal ( destination );
END PROCEDURE signal_release;
procedure init_signal_driver(
src_obj : in string;
dest_obj : in string;
delay : in time;
delay_type : in del_mode;
verbose : in integer
) is
begin
signal_agent(src_obj, dest_obj, 0);
end procedure init_signal_driver;
END;
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vlib work
vsim -t 1 ms -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
#add wave *
do wave.do
run 1 ms
wave zoomfull
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