conv_ttl_rs485.xise 78.7 KB
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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  <header>
    <!-- ISE source project file created by Project Navigator.             -->
    <!--                                                                   -->
    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
    <!-- along with the project source files, is sufficient to open and    -->
    <!-- implement in ISE Project Navigator.                               -->
    <!--                                                                   -->
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    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
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  </header>

  <autoManagedFiles>
    <!-- The following files are identified by `include statements in verilog -->
    <!-- source files and are automatically managed by Project Navigator.     -->
    <!--                                                                      -->
    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
    <!-- project is analyzed based on files automatically identified as       -->
    <!-- include files.                                                       -->
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    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
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  </autoManagedFiles>

  <properties>
    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
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    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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    <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
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    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
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    <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
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    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
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    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_rs485|arch" xil_pn:valueState="non-default"/>
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    <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/Release/conv_ttl_rs485.vhd" xil_pn:valueState="non-default"/>
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    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_rs485" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
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    <property xil_pn:name="Language" xil_pn:value="All" xil_pn:valueState="default"/>
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    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
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    <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
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    <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x0b000044" xil_pn:valueState="non-default"/>
    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x0b170000" xil_pn:valueState="non-default"/>
    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g next_config_register_write:Disable" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
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    <property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Output File Name" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="default"/>
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    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
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    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="conv_ttl_rs485_map.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="conv_ttl_rs485_timesim.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="conv_ttl_rs485_synthesis.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="conv_ttl_rs485_translate.v" xil_pn:valueState="default"/>
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    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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    <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
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    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
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    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
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    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
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    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/gc_arbitrated_mux" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.gc_arbitrated_mux" xil_pn:valueState="non-default"/>
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    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
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    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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    <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
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    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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    <property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
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    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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    <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
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    <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
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    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.gc_arbitrated_mux" xil_pn:valueState="default"/>
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    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
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    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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    <property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
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    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
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    <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
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    <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
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    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
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    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
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    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0x1FFF" xil_pn:valueState="non-default"/>
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    <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
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    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
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    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|arch" xil_pn:valueState="non-default"/>
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    <property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-07-24T16:52:24" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B340E1CEFABAF7AEA6E4A2576F7AC596" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
  </properties>

  <libraries/>

  <files>
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    <file xil_pn:name="../../top/Release/conv_ttl_rs485.ucf" xil_pn:type="FILE_UCF">
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_regs.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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    </file>
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    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
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    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
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    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
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    </file>
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    <file xil_pn:name="../../top/Release/conv_ttl_rs485.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
653 654
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
655
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
656
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
657 658
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
659
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
660
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
661 662
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
663
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
664
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
665 666
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
667
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
668
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
669 670
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
671
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
672
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
673 674
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
675
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
676
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
677 678
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
679
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
680
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
681 682
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
683
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
684
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
685 686
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
687
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
688
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
689 690
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
691
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
692
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
693 694
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
695
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
696
      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
697 698
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
699
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
700
      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
701 702
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
703
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
704
      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
705 706
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
707
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
708
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
709 710
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
711
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
712
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
713 714
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
715
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
716
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
717 718
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
719
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
720
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
721 722
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
723
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
724
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
725 726
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
727
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
728
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
729 730
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
731
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
732
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
733 734
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
735
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
736
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
737 738
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
739
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
740
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
741 742
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
743
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
744
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
745 746
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
747
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
748
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
749 750
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
751
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
752
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
753 754
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
755
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
756
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
757 758
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
759
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
760
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
761 762
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
763
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
764
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
765 766
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
767
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
768
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
769 770
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
771
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
772
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
773 774
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
775
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
776
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
777 778
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
779
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
780
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
781 782
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
783
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
784
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
785 786
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
787
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
788
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
789 790
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
791
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
792
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
793 794
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
795
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
796
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
797 798
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
799
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
800
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
801 802
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
803
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
804
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
805 806
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
807
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
808
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
809 810
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
811
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
812
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
813 814
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
815
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
816
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
817 818
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
819
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
820
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
821 822
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
823
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
824
      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
825 826
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
827
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
828
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
829 830
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
831
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
832
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
833 834
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
835
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
836
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
837 838
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
839
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
840
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
841 842
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
843
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
844
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
845 846
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
847
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
848
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
849 850
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
851
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
852
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
853 854
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
855
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
856
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
857 858
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
859
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
860
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
861 862
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
863
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
864
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
865 866
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
867
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
868
      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
869 870
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
871
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
872
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
873 874
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
875
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
876 877
      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
    </file>
878 879 880 881 882
    <file xil_pn:name="../../sim/i2c_bus_model.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="185"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="185"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="185"/>
883
    </file>
884 885 886 887 888
    <file xil_pn:name="../../sim/i2c_master_and_driver.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="186"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="186"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="186"/>
889
    </file>
890 891 892 893 894
    <file xil_pn:name="../../sim/print_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="187"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="187"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="187"/>
895
    </file>
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    <file xil_pn:name="../../sim/testbench.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="188"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="188"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="188"/>
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    </file>
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    <file xil_pn:name="../../sim/testbench_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="189"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="189"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="189"/>
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    </file>
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    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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    </file>
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    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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    </file>
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    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
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    </file>
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    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
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    </file>
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    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
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    </file>
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    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
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      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
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    </file>
  </files>

  <bindings/>

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  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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</project>