conv_ttl_rs485.xise 62.3 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <header>
    <!-- ISE source project file created by Project Navigator.             -->
    <!--                                                                   -->
    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
    <!-- along with the project source files, is sufficient to open and    -->
    <!-- implement in ISE Project Navigator.                               -->
    <!--                                                                   -->
unknown's avatar
unknown committed
12
    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
13 14 15 16 17 18 19 20 21
  </header>

  <autoManagedFiles>
    <!-- The following files are identified by `include statements in verilog -->
    <!-- source files and are automatically managed by Project Navigator.     -->
    <!--                                                                      -->
    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
    <!-- project is analyzed based on files automatically identified as       -->
    <!-- include files.                                                       -->
unknown's avatar
unknown committed
22 23 24
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
25 26 27 28 29 30 31 32 33 34 35 36 37
  </autoManagedFiles>

  <properties>
    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
unknown's avatar
unknown committed
38 39
    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
40 41 42 43 44 45 46 47 48 49 50 51
    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
unknown's avatar
unknown committed
52
    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134
    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
unknown's avatar
unknown committed
135 136
    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_rs485|arch" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/conv_ttl_rs485.vhd" xil_pn:valueState="non-default"/>
137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_rs485" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
unknown's avatar
unknown committed
159
    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345
    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x0b000044" xil_pn:valueState="non-default"/>
    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x0b170000" xil_pn:valueState="non-default"/>
    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Output File Name" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="conv_ttl_rs485_map.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="conv_ttl_rs485_timesim.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="conv_ttl_rs485_synthesis.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="conv_ttl_rs485_translate.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0x1FFF" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_rs485" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-07-24T16:52:24" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B340E1CEFABAF7AEA6E4A2576F7AC596" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
  </properties>

  <libraries/>

  <files>
    <file xil_pn:name="../../top/conv_ttl_rs485.ucf" xil_pn:type="FILE_UCF">
unknown's avatar
unknown committed
346
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
347 348
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
349
      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
350 351
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
352
      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
353 354
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
355
      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
356 357
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_regs.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
358
      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
359 360
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
361
      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
362 363
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
364
      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
365 366
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
367
      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
368 369
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
370
      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
371 372
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
373
      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
374 375
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
376
      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
377 378
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
379
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
380 381
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
382
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
383 384
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
385
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
386 387
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
388
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
389 390
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
391
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
392 393
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
394
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
395 396
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
397
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
398 399
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
400
      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
401 402
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
403
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
404 405
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
406
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
407 408
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
409
      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
410 411
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
412
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
413 414
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
415
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
416 417
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
418
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
419 420
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
421
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
422 423
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
424
      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
425 426
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
427
      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
428 429
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
430
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
431 432
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
433
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
434 435
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
436
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
437 438
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
439
      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
440 441
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
442
      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
443 444
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
445
      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
446
    </file>
unknown's avatar
unknown committed
447 448
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
449
    </file>
unknown's avatar
unknown committed
450 451
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
452
    </file>
unknown's avatar
unknown committed
453 454
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
455 456
    </file>
    <file xil_pn:name="../../top/conv_ttl_rs485.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
457
      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
458 459
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
460
      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
461 462
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
463
      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
464 465
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
466
      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
467 468
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
469
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
470 471
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
472
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
473 474
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
475
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
476 477
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
478
      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
479 480
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
481
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
482 483
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
484
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
485 486
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
487
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
488 489
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
490
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
491 492
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
493
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
494 495
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
496
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
497 498
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
499
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
500 501
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
502
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
503 504
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
505
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
506 507
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
508
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
509 510
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
511
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
512 513
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
514
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
515 516
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
517
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
518 519
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
520
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
521 522
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
523
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
524 525
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
526
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
527 528
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
529
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
530 531
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
532
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
533 534
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
535
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
536 537
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
538
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
539 540
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
541
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
542 543
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
544
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
545 546
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
547
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
548 549
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
550
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
551 552
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
553
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
554 555
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
556
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
557 558
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
559
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
560 561
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
562
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
563 564
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
565
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
566 567
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
568
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
569 570
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
571
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
572 573
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
574
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
575 576
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
577
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
578 579
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
580
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
581 582
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
583
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
584 585
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
586
      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
587 588
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
589
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
590 591
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
592
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
593 594
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
595
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
596 597
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
598
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
599 600
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
601
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
602 603
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
604
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
605 606
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
607
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
608 609
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
610
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
611 612
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
613
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
614 615
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
616
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
617 618
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
619
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
620 621
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
622
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
623 624
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
625
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
626 627
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
628
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
629 630
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
631
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
632 633
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
634
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
635 636
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
637
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
638 639
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
640
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
641 642
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
unknown's avatar
unknown committed
643
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
644 645
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
646
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
647 648
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
649
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
650 651
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
652
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
653 654
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
655
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
656 657
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
658
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
659 660
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
661
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
662 663
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
664
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
665 666
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
667
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
668 669
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
670
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
671 672
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
673
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
674 675
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
676
      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
677 678
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
679
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
680 681
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
682
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
683 684
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
685
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
686 687
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
688
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
689 690
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
691
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
692 693
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
694
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
695 696
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
697
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
698 699
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
700
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
701 702
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
703
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
704 705
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
706
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
707 708
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
709
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
710 711
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
712
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
713 714
    </file>
    <file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
unknown's avatar
unknown committed
715
      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
716 717 718 719 720
    </file>
  </files>

  <bindings/>

unknown's avatar
unknown committed
721
  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
722 723

</project>