top_common_patch.patch 1.74 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
diff --git a/top/conv_common_gw.vhd b/top/conv_common_gw.vhd
index 489f311..504a661 100644
--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
@@ -57,6 +57,9 @@ use work.conv_common_gw_pkg.all;
 entity conv_common_gw is
   generic
   (
+    -- Reduces some timeouts to speed up simulations
+    g_simul                : boolean := false;
+ 
     -- Number of repeater channels
     g_nr_chans             : integer := 6;
     -- Number of inverter channels
@@ -314,6 +317,7 @@ architecture arch of conv_common_gw is
   signal rst_20_n            	: std_logic;
   signal rst_20            		: std_logic;
   signal rst_ext             	: std_logic;
+  signal rst_time               : positive := 10;
 
   -- Pulse logic signals
   signal trig_a              	: std_logic_vector(g_nr_chans-1 downto 0);
@@ -543,12 +547,14 @@ begin
   -- External reset input to reset generator
   rst_ext <= rst_fr_reg or (not vme_sysreset_n_i);
 
+  -- Reset time: 50ns * 2 * (10**6) = 100 ms
+  rst_time <= 10; --2*(10**6) when g_simul = FALSE else 10;
+
   -- Configure reset generator for 100ms reset
   cmp_reset_gen : conv_reset_gen
     generic map
     (
-  -- Reset time: 50ns * 2 * (10**6) = 100 ms
-      g_reset_time => 2*(10**6) 
+      g_reset_time => rst_time 
     )
     port map
     (
diff --git a/top/conv_common_gw_pkg.vhd b/top/conv_common_gw_pkg.vhd
index e8a0787..1271ca1 100644
--- a/top/conv_common_gw_pkg.vhd
+++ b/top/conv_common_gw_pkg.vhd
@@ -71,6 +71,8 @@ package conv_common_gw_pkg is
   component conv_common_gw is
     generic
     (
+      -- Reduces some timeouts to speed up simulations
+      g_simul               : boolean := false;
       -- Number of repeater channels
       g_nr_chans            : integer := 6;
 	  g_nr_inv_chans        : integer := 4;