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\addcontentsline{toc}{section}{Licensing information}
\section*{Licensing information}

\noindent
This document is licensed under a Creative Commons Attribution-ShareAlike 4.0
International License. If you have not received a copy of the license along with this
work, see \\
\url{http://creativecommons.org/licenses/by-sa/4.0/}

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\section*{Revision history}
\addcontentsline{toc}{section}{Revision history}

\centerline
{
  \rowcolors{2}{white}{gray!25}
  \begin{tabular}{l c p{.6\textwidth}}
  \hline
  \multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
  \hline
  06-08-2014 & 0.1 & First draft \\
  06-01-2015 & 0.2 & Release for gateware v0.0 \\
  06-01-2015 & 1.0 & Updated memory map for gateware v1.0 \\
  27-01-2015 & 1.1 & Added repository download commands to Section~\ref{sec:intro} \\
  \hline
  \end{tabular}
} 

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% List of abbreviations
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\pagebreak
\section*{List of abbreviations}
\begin{tabular}{l l}
FPGA & Field-Programmable Gate Array \\
LSR  & Line Status Register \\
OSWR & Other Switches Register \\
SR   & Status Register \\
SNMP & Simple Network Management Protocol \\
\end{tabular}
\addcontentsline{toc}{section}{List of abbreviations}

%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}

This document is the HDL guide for the CONV-TTL-RS485 project~\cite{conv-ttl-rs485-ohwr}.
The HDL for the CONV-TTL-RS485 board uses the converter board common gateware~\cite{conv-common-gw}
as a subproject and adds some external logic to it to adapt for peculiarities on the CONV-TTL-RS485.
This document explains these peculiarities and the corresponding logic implemented, and lists
the memory map for the gateware in Appendix~\ref{app:memmap}.

The HDL files can be obtained by cloning the repository along with its submodules using the following commands:

\begin{footnotesize}
\begin{verbatim}
git clone git://ohwr.org/level-conversion/conv-ttl-rs485/conv-ttl-rs485-gw.git
cd conv-ttl-rs485-gw/
git submodule update --init --recursive
\end{verbatim}
\end{footnotesize}

\subsection{Additional documentation}

\begin{itemize}
  \item Converter board common gateware~\cite{conv-common-gw}
  \item CONV-TTL-RS485 User Guide~\cite{conv-ttl-rs485-ug}
  \item CONV-TTL-RS485 schematics~\cite{conv-ttl-rs485-sch}
  \item CONV-TTL-RS485 OHWR Wiki page~\cite{conv-ttl-rs485-ohwr}
\end{itemize}

%==============================================================================
% SEC: Overview
%==============================================================================
\section{Overview}
\label{sec:overview}

A block diagram of the HDL is shown in Figure~\ref{fig:block-diagram}. This document
will detail each of the blocks in the following sections. For a more
general look at the pulse repetition logic, refer to the CONV-TTL-RS485 User Guide~\cite{conv-ttl-rs485-ug}.

\begin{figure}[h]
  \centerline{\includegraphics[width=1.08\textwidth]{fig/block-diagram}}
  \caption{\label{fig:block-diagram} Block diagram of CONV-TTL-RS485 gateware}
\end{figure}

%==============================================================================
\pagebreak
\section{Input logic}
%==============================================================================

%==============================================================================
% SEC: TTL input logic
%==============================================================================
\subsection{TTL/TTL-BAR input logic}
\label{sec:ttl-input}

The TTL/TTL-BAR input logic is shown in Figure~\ref{fig:ttl-inp}. It assures
an active-high pulse to the \textit{pulse\_i} input of the \textit{conv\_common\_gw}
component and adapts for TTL-BAR pulses that may be input when the TTL switch is
on.

In addition, because in TTL-BAR mode a lack of signal on the line is high (due
to the on-board Schmitt-trigger buffer), the \textit{no signal detect} block
(Figure~\ref{fig:no-sig-detect}) disables this line if it is high for 100~${\mu}s$,
to allow propagation of blocking pulses arriving on the rear panel while the channel
has no cable plugged in while in TTL-BAR mode.

When in TTL-BAR mode, the FRONTFS bits of the lines status register
(LSR -- see Appendix~\ref{app:conv-regs-lsr}) contain the state of the no signal detect
block for each channel and can be used to check if no cable is plugged into the channel.
When in TTL mode, the FRONTFS bits are unused.

\begin{figure}[h]
  \centerline{\includegraphics[width=.9\textwidth]{fig/ttl-inp}}
  \caption{\label{fig:ttl-inp} TTL/TTL-BAR input logic}

  \centerline{\includegraphics[width=.8\textwidth]{fig/no-sig-detect}}
  \caption{\label{fig:no-sig-detect} No signal detect block}
\end{figure}

%==============================================================================
% SEC: RS-485 input logic
%==============================================================================
\subsection{RS-485 input logic}
\label{sec:rs485-input}

A simplified diagram of the RS-485 input logic is shown in Figure~\ref{fig:rs485-inp}.
The actual logic is active-low logic, due to the Schmitt trigger inverters on the
signals from the RS-485 and failsafe transceiver chips. The RS-485 trigger is only propagated to
\textit{conv\_common\_gw} if a cable is plugged in, indicated by the signal loss detection
mechanism~\cite{rs485-fs}. The AND gate in the mechanism is implemented internally to the FPGA and it is this gate that
enables RS-485 trigger propagation.

The failsafe lines are reflected in the LSR register (see the memory map in the
CONV-TTL-RS485 User Guide~\cite{conv-ttl-rs485-ug}), as shown in the figure.

\begin{figure}[h]
  \centerline{\includegraphics[width=.8\textwidth]{fig/rs485-inp}}
  \caption{\label{fig:rs485-inp} Simplified diagram of RS-485 logic}
\end{figure}

%==============================================================================
% SEC: First pulse inhibit
%==============================================================================
\subsection{First pulse inhibit mechanism}
\label{sec:first-pulse-inhibit}

The first pulse inhibit mechanism (Figure~\ref{fig:first-pulse-inhibit}) is implemented
in the form of a counter which waits for 100~${\mu}s$ after reset prior to enabling the
line. It is implemented because in TTL-BAR mode, until an inactive line is disabled,
the TTL line is high and this may lead to a pulse triggered on the channel, due to reset
of modules within the \textit{conv\_common\_gw} component.

By keeping the line disabled until the no signal detect block in the TTL input logic
(Section~\ref{sec:ttl-input}) disables the line, no pulse is triggered on the channel.
As seen in Figure~\ref{fig:first-pulse-inhibit}, an extra clock cycle delay is needed before
the channel is enabled, to make sure that all reset states inside the \textit{conv\_common\_gw}
block have been finished and no pulses are generated.

To keep the logic simple, the pulse inhibit logic disables the line even when the board is in
TTL repetition mode. Since in practice the effect it has on the input to the 
\textit{conv\_common\_gw} is extending the 100~ms reset by 100~${\mu}s$, an extra
0.1\% delay from reset to full pulse replication capabilities is deemed insignificant
in comparison to logic simplification.

\begin{figure}[h]
  \centerline{\includegraphics[width=.9\textwidth]{fig/first-pulse-inhibit}}
  \caption{\label{fig:first-pulse-inhibit} First pulse inhibit mechanism}
\end{figure}

%==============================================================================
% SEC: Line input logic
%==============================================================================
\subsection{Line input logic}
\label{sec:line-input}

Since the TTL and RS-485 lines are passed through Schmitt trigger inverters
prior to being input to the FPGA, they are active-low. The line input logic
(Figure~\ref{fig:line-inp}) adapts this to active-high logic prior to inputting
them to the LSR, so that the state of the line at the input of the board (before
the Schmitt trigger) is reflected in the LSR.

\begin{figure}[h]
  \centerline{\includegraphics[width=.7\textwidth]{fig/line-inp}}
  \caption{\label{fig:line-inp} Line input logic}
\end{figure}

%==============================================================================
% SEC: Switch input logic
%==============================================================================
\subsection{Switch input logic}
\label{sec:sw-input}

The switch lines must also be negated for their active-high reflection in the SR and
OSWR (see Appendix~\ref{app:memmap}), as shown in Figure~\ref{fig:switches}.

\begin{figure}[h]
  \centerline{\includegraphics[width=.6\textwidth]{fig/switches}}
  \caption{\label{fig:switches} Switch input logic}
\end{figure}

%==============================================================================
\pagebreak
\section{Output logic}
%==============================================================================

%==============================================================================
% SEC: TTL/TTL-BAR output logic
%==============================================================================
\subsection{TTL/TTL-BAR output logic}
\label{sec:ttl-output}

The TTL/TTL-BAR output logic (Figure~\ref{fig:ttl-outp}) ensures that TTL pulses
are propagated from the \textit{pulse\_o} output of \textit{conv\_common\_o} to
the FPGA output when the TTL switch is ON, or that TTL-BAR pulses are propagated
when it is OFF.

\begin{figure}[h]
  \centerline{\includegraphics[width=.6\textwidth]{fig/ttl-outp}}
  \caption{\label{fig:ttl-outp} TTL output logic}
\end{figure}

%==============================================================================
% SEC: Pulse LED logic
%==============================================================================
\subsection{Pulse LED output logic}
\label{sec:pulse-led}

Since in the CONV-TTL-RS485 schematics the rear-panel pulse LEDs are driven from inverting
Schmitt triggers to ground, the active-high pulse LED output from \textit{conv\_common\_gw}
must be inverted prior to driving the Schmitt trigger. This is done in the pulse
LED logic (Figure~\ref{fig:pulse-led}). As can be seen in the figure, since the front-panel
LED lines are not inverted on-board, they are driven directly from the FPGA.

\begin{figure}[h]
  \centerline{\includegraphics[width=.6\textwidth]{fig/pulse-led}}
  \caption{\label{fig:pulse-led} Pulse LED logic}
\end{figure}

%==============================================================================
% SEC: Bicolor LED logic
%==============================================================================
\subsection{Bicolor LED output logic}
\label{sec:bicolor-led}

The bicolor LED logic external to the \textit{conv\_common\_gw} takes the
bicolor LED outputs as well as specific control pins (such as, for example,
the I$^2$C LED drive pin, flashing four times on an I$^2$C transfer) and connects
them to the bicolor LEDs, adding multiplexer logic where needed to control the lighting
and color of the LED.

The way in which each LED is turned on is described in the CONV-TTL-RS485 User Guide~\cite{conv-ttl-rs485-ug}.

%======================================================================================
% Appendices
%======================================================================================
\pagebreak

\begin{appendices}

%==============================================================================
% APP: Memmap
%==============================================================================
\section{Memory map}
\label{app:memmap}

Table~\ref{tbl:memmap} shows the complete memory map of the gateware. The
following sections list the memory map of each peripheral.

In order to convert address values to register index values for SNMP access,
the following formula should be used:

\begin{center}
$reg. index = \frac{addr}{4} + 1$
\end{center}

\begin{table}[h]
\caption{\textit{conv\_common\_gw} memory map}
\label{tbl:memmap}
\centerline
{
  \rowcolors{2}{white}{gray!25}
  \begin{tabular}{l l l p{.4\textwidth}}
  \hline
  \multicolumn{1}{c}{\textbf{Peripheral}} & \multicolumn{2}{c}{\textbf{Address range}} & \multicolumn{1}{c}{\textbf{Description}} \\
  \hline
  Board registers & 0x000 & 0x0{}f{}f & Coverter board registers \\
  MultiBoot       & 0x100 & 0x11f & MultiBoot module \\
  One-wire master & 0x200 & 0x2f{}f & One-wire master for DS18B20 thermometer module \\
  SDB descriptor  & 0xf00 & 0xf{}f{}f & SDB descriptor (see~\cite{sdb}) \\
  \hline
  \end{tabular}
}
\end{table}

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%==============================================================================
\end{appendices}
%==============================================================================
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% Bibliography
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\bibliography{hdlg-conv-ttl-rs485}
\addcontentsline{toc}{section}{References}

\end{document}
