target = "xilinx"
action = "synthesis"
syn_device  = "xc6slx45t"
syn_grade   = "-3"
syn_package = "fgg484"
syn_top     = "conv_ttl_rs485"
syn_project = "conv_ttl_rs485.xise"

modules = {
    "local" : [
      "../../top"
      ]
    }
