Commit fab59cbd authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Add new memory map and dedicated timestamp registers

parent 9b312b0a
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill August 12, 2014
\hfill August 22, 2014
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......@@ -119,3 +119,8 @@
title = {{DS18B20 -- Programmable Resolution 1-Wire Digital Thermometer}},
note = {\url{}}
title = {{SDB specification v1.1}},
howpublished = {\url{}}
......@@ -9,8 +9,8 @@
% Hyperrefs
colorlinks = true,
linkcolor = Mahogany,
citecolor = Mahogany,
linkcolor = black,
citecolor = black,
urlcolor = blue,
......@@ -78,6 +78,7 @@
12-08-2014 & 2.21 & Small error corrections (\textit{writereg} instead of \textit{readreg} in Section~\ref{sec:diag-remote-reset},
and typo in Section~\ref{sec:reprog-bitstreams}), and addition of how to read gateware version in
Section~\ref{sec:reprog-bitstreams} \\
22-08-2014 & 3.00 & Changed memory map, adding latest per-channel timestamp readout and line status registers \\
......@@ -1035,7 +1036,9 @@ The architecture of the time-tagging mechanism is shown in Figure~\ref{fig:timet
Every time a pulse arrives on a channel, a timetag sample is stored to a 128-deep
ring buffer. While this ring buffer is not entirely accessible in the addressing
space of the FPGA, it can be read sample by sample by reading the TBCYR, TBL/HR and
TBMR registers (see Appendix~\ref{app:conv-regs}).
TBMR registers (see Appendix~\ref{app:conv-regs}). At the same time the timestamp is
stored into the time-tag buffer, it is also stored to the latest timestamp registers
(CHxLTS*R -- see Appendix~\ref{app:conv-regs}).
\subsubsection{Pulse timetags}
......@@ -1045,10 +1048,8 @@ Two timetags are available on the CONV-TTL-BLO. These timetags are listed in
Table~\ref{tbl:timetags}. When White-Rabbit (WR) is present, the precise centralized
and synchronized timing from the WR network is used. When WR is not present, the local
time tag is used. Note that due to the fact that this timetag is unsynchronized,
it will differ slightly between two different boards in a crate.
Each timetag sample consists of a cycles value, which counts 8~ns cycles, and a TAI seconds
it will differ slightly between two different boards in a crate. Each timetag sample
consists of a cycles value, which counts 8~ns cycles, and a TAI seconds value.
\caption{Timetag types}
......@@ -1088,7 +1089,7 @@ a timetag is stored to the ring buffer. This delay is shown in Figure~\ref{fig:t
\subsubsection{Reading the timetags}
\subsubsection{Reading the timetags from the ring buffer}
The TBCYR, TBTLR and TBTHR (see Appendix~\ref{app:conv-regs}) contain the actual
......@@ -1166,6 +1167,18 @@ of samples written to the buffer. When the buffer is full, the USEDW field is 0
FULL bit is set. Setting the CLR bit of the TBCSR will bring the read and write pointers
to 0 and set the USEDW field to 0.
\subsubsection{Latest timestamp registers}
There are three registers per channel dedicated to the storage of the latest timestamp.
These registers always store the latest time at which a pulse arrived on a channel and
can be useful when other channels fill up the ring buffer before a relevant timestamp
is read.
The memory map~\ref{app:conv-regs} contains further details about the implementation of
each register.
% SUBSEC: Remote reset
......@@ -1255,7 +1268,7 @@ number is not in the range 1..6, no pulse is generated on any channel and no
error is reported.
\caption{Manual pulse triggering logic}
......@@ -1682,9 +1695,10 @@ $reg. index = \frac{addr}{4} + 1$
\multicolumn{1}{c}{\textbf{Peripheral}} & \multicolumn{2}{c}{\textbf{Address range}} & \multicolumn{1}{c}{\textbf{Description}} \\
Board registers & 0x000 & 0x020 & Coverter board registers \\
MultiBoot & 0x040 & 0x050 & MultiBoot module \\
Thermometer & 0x080 & 0x084 & Thermometer chip \\
Board registers & 0x000 & 0x0ff & Converter board registers \\
MultiBoot & 0x100 & 0x01f & MultiBoot module \\
Thermometer & 0x200 & 0x2ff & Thermometer chip \\
SDB descriptor & 0xf00 & 0xfff & SDB descriptor table (see~\cite{sdb}) \\
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