Skip to content

C
Conv TTL Blocking
Commit f8d6788d authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
Browse files
Options

Doc: user manual updated with limit on blocking channels per crates

parent 1a01a5bb
Hide whitespace changes
Inline Side-by-side
Showing with 109 additions and 16 deletions
doc/ug/ug-conv-ttl-blo.tex
View file @ f8d6788d
......@@ -152,7 +152,7 @@ pulses (see Section~\ref{sec:pulse-def}). The main features of the board are:
\end{itemize}
\item Four general-purpose inverter channels
\item Support for high frequency bursts
\item Selectable pulse width: 1.2 us for 50kHz-100kHz repetition frequencies, 250ns for 500kHz-2MHz repetition frequencies
\item Selectable pulse width: 1.2 us for 50kHz-104kHz repetition frequencies, 250ns for 500kHz-2MHz repetition frequencies
\item Each input channel has 50~$\Omega$ input termination
\item Each channel capable of driving 50~$\Omega$ load
\item SFP connector
......@@ -422,8 +422,8 @@ panel (via a CONV-TTL-RTM).
The various characteristics of the pulse signals are defined in
Figure~\ref{fig:pulse-def} and outlined in Table~\ref{tbl:pulse-def-ttl} for
TTL and TTL-BAR pulses, and in Table~\ref{tbl:pulse-def-blo} for blocking
pulses.
TTL and TTL-BAR pulses, and in Tables~\ref{tbl:pulse-def-blo-short-500k} to~\ref{tbl:pulse-def-blo-long-104k} for blocking
pulses of different pulse widths and frequencies. This distinction is not made in Table~\ref{tbl:pulse-def-ttl} for TTL and TTL-BAR signals as they their input and output circuitry is not impacted by the pulse widths and switching frequency.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-def}}
......@@ -447,8 +447,9 @@ pulses.
$V_{OH}$ & Output pulse high-level amplitude & 2.4 & 3.3 & 5 & V \\
$V_{OL}$ & Output pulse low-level amplitude & & 0 & 0.7 & V \\
$t_{p,i}$& Input pulse width & 100 & & & ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 241 & & & ${\mu}s$ \\
$t_{p,o}$& Output pulse width & 250 & & 1.2 & ${\mu}s$ \\
$T_{min}$& Period of pulse signal for 250ns pulses (3)& 0.5 & & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal for $1.2\mu s$ pulses (3)& 9.6 & & & ${\mu}s$ \\
$t_r$ & Rise time & 1 & 3.2 & 4.9 & ns \\
$t_f$ & Fall time & 2 & 4 & 5.6 & ns \\
\hline
......@@ -463,8 +464,56 @@ by the FPGA gateware. \\
\pagebreak
\begin{table}[h]
\caption{Blocking pulse characteristics}
\label{tbl:pulse-def-blo}
\caption{Blocking pulse characteristics- 250ns pulse @500kHz}
\label{tbl:pulse-def-blo-short-500k}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l c c c c}
\hline
\multicolumn{1}{c}{\textbf{Symbol}} & \multicolumn{1}{c}{\textbf{Parameter}} &
\textbf{Min.} & \textbf{Typ.} & \textbf{Max.} & \textbf{Unit}\\
\hline
$V_{IH}$ & Input pulse high-level amplitude (1) & 3.8 & & 25 & V \\
$V_{IL}$ & Input pulse low-level amplitude & -5 & & & V \\
$V_{OH}$ & Output pulse high-level amplitude (2)& 21.8 & 24 & 22.1 & V \\
$V_{OL}$ & Output pulse low-level amplitude (2) & & 0 & & V \\
$t_{p,i}$& Input pulse width & 100 & & 1900& ns \\
$t_{p,o}$& Output pulse width & & 250 & & $ns$ \\
$T_{min}$& Period of pulse signal (3) & 1.75& & & ${\mu}s$ \\
$t_r$ & Rise time & 85 & & 96 & ns \\
$t_f$ & Fall time & 55 & & 58& ns \\
\hline
\end{tabular}
}
\caption{Blocking pulse characteristics- 250ns pulse @2MHz}
\label{tbl:pulse-def-blo-short-2m}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l c c c c}
\hline
\multicolumn{1}{c}{\textbf{Symbol}} & \multicolumn{1}{c}{\textbf{Parameter}} &
\textbf{Min.} & \textbf{Typ.} & \textbf{Max.} & \textbf{Unit}\\
\hline
$V_{IH}$ & Input pulse high-level amplitude (1) & 10 & & 25 & V \\
$V_{IL}$ & Input pulse low-level amplitude & -5 & & & V \\
$V_{OH}$ & Output pulse high-level amplitude (2)& 16.2 & & 21.5 & V \\
$V_{OL}$ & Output pulse low-level amplitude (2) & & 0 & & V \\
$t_{p,i}$& Input pulse width & 100 & & 400& ns \\
$t_{p,o}$& Output pulse width & & 250 & & $ns$ \\
$T_{min}$& Period of pulse signal (3) & 0.5 & & & ${\mu}s$ \\
$t_r$ & Rise time & 110 & & 120 & ns \\
$t_f$ & Fall time & 35 & & 56& ns \\
\hline
\end{tabular}
}\textbf{}
\end{table}
\begin{table}[h]
\caption{Blocking pulse characteristics- $1.2\mu s$ pulse @52kHz}
\label{tbl:pulse-def-blo-long-52k}
\centerline
{
\rowcolors{2}{white}{gray!25}
......@@ -477,14 +526,37 @@ by the FPGA gateware. \\
$V_{IL}$ & Input pulse low-level amplitude & -5 & & & V \\
$V_{OH}$ & Output pulse high-level amplitude (2)& 23 & 24 & 25 & V \\
$V_{OL}$ & Output pulse low-level amplitude (2) & & 0 & & V \\
$t_{p,i}$& Input pulse width & 100 & & 3900& ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 241 & & & ${\mu}s$ \\
$t_r$ & Rise time & 75 & 140 & 225 & ns \\
$t_f$ & Fall time & 75 & 160 & 225 & ns \\
$t_{p,i}$& Input pulse width & 100 & & 1900& ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & $\mu s$ \\
$T_{min}$& Period of pulse signal (3) & 19.2& & & ${\mu}s$ \\
$t_r$ & Rise time & 62 & & 67 & ns \\
$t_f$ & Fall time & 82 & & 92.5& ns \\
\hline
\end{tabular}
}
\caption{Blocking pulse characteristics- $1.2\mu s$ pulse @104kHz}
\label{tbl:pulse-def-blo-long-104k}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l c c c c}
\hline
\multicolumn{1}{c}{\textbf{Symbol}} & \multicolumn{1}{c}{\textbf{Parameter}} &
\textbf{Min.} & \textbf{Typ.} & \textbf{Max.} & \textbf{Unit}\\
\hline
$V_{IH}$ & Input pulse high-level amplitude (1) & 3.8 & & 25 & V \\
$V_{IL}$ & Input pulse low-level amplitude & -5 & & & V \\
$V_{OH}$ & Output pulse high-level amplitude (2)& 23 & 24 & 25 & V \\
$V_{OL}$ & Output pulse low-level amplitude (2) & & 0 & & V \\
$t_{p,i}$& Input pulse width & 100 & & 9500& ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & $\mu s$ \\
$T_{min}$& Period of pulse signal (3) & 9.6 & & & ${\mu}s$ \\
$t_r$ & Rise time & 62 & & 67 & ns \\
$t_f$ & Fall time & 82 & & 92.5& ns \\
\hline
\end{tabular}
}\textbf{}
\end{table}
\noindent Note 1: Pulse amplitude for which a $t_{p,o}$ pulse is replicated at the output. \\
......@@ -557,7 +629,7 @@ Moreover, for a given pulse width, the board is able to support higher frequenci
\textbf{Burst mode} \\
\hline
v2.1-v3 & $1.2 \mu s$ & $4.16 kHz$ & N/A \\
\hline
\hline
v4.0 & $250 ns$ & $571 kHz$ & $ 2MHz $ \\
\hline
v4.0 & $1.2 \mu s$ & $52 kHz$ & $ 104kHz $ \\
......@@ -600,9 +672,11 @@ about the implementation of the PG block, refer to the CONV-TTL-BLO HDL Guide~\c
\begin{tabular}{p{.96\textwidth}}
\hline
\large \hspace*{22pt} Burst control block not activated for v3 boards and earlier \\
\large \hspace*{22pt} Burst control block is not activated for v3 boards and earlier \\
\hline
\end{tabular}
After the PG block, a Burst Control (BC) block has been added for v4.0 boards (Corresponding
to gateware release v4). For earlier versions of the board, this option is deactivated. The block
implements a thermal model of the board. An internal counter
......@@ -760,8 +834,27 @@ can be left in the \textbf{OFF} position.
\noindent Note 1: If the glitch filter is enabled, it adds an extra 350~ns delay to $t_{PD}$. \\
\noindent Note 2: Measured visually using cursors on an oscilloscope.
%======================================================================================
% SEC: Protecting CONV-TTL-BLO Boards
%======================================================================================
\pagebreak
\section{Protecting CONV-TTL-BLO Boards}
\label{sec:protection}
The CONV-TTL-BLO board generates the +27V required for the blocking output stage, from the +12V provided on all VME ELMA crates. To do so, it uses a boost controller chip.\\
In terms of power, ELMA specifies 66W available on the +12V power supply (corresponding to 5.5~A maximum current) for 1U-3U crates. For 9U crates the current limit is 12~Amps.\\
As the board can potentially operate six blocking channels, each with 3 outputs, the +27V supply may not be able to cope with current demand if all outputs were active.\\
Therefore the board is fuse-protected on the 3.3V, 5V and +12V power supply rails. Of particular importance is the 5~Amps fuse present on the +12V rail. If too many blocking outputs are in operation, and if the number of outputs exceeds the maximum recommended, then the fuse will blow causing the blocking output to fail. \\
Therefore, a limit on blocking outputs/crate, must be imposed. In worst case scenarios, each output port requires a maximum current consumption $I_{blo-out}$ of 420~mA for maximum repetition frequency (2MHz repetition).
As a rule of thumb, the maximum number of active output ports $N_{blo-out}$ \textbf{per crate} is:
\begin {equation}
N_{blo-out}= \frac{I_{fuse+12V}}{I_{blo-out}}
\end{equation}
\begin {equation}
N_{blo-out}= 5/0.4\approx12
\end{equation}
\textbf{\textit{This means that during planning and installations, it is important to not allocate any more than 12 blocking output ports per crate. As the board is fuse-protected, failing to respect this limit will not damage the board, but will cause a failure in blocking repetition and will necessitate human intervention to replace the damaged fuse.}}
%======================================================================================
% SEC: Communicating to the CONV-TTL-BLO
%======================================================================================
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment