Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
C
Conv TTL Blocking
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
5
Issues
5
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Conv TTL Blocking
Commits
ce34f774
Commit
ce34f774
authored
Sep 30, 2014
by
Theodor-Adrian Stana
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
doc: Updates to user guide
parent
5e08bdd9
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
31 additions
and
12 deletions
+31
-12
cern-title.tex
doc/ug/cern-title.tex
+1
-1
conv-regs.tex
doc/ug/conv-regs.tex
+1
-1
ug-conv-ttl-blo.tex
doc/ug/ug-conv-ttl-blo.tex
+29
-10
No files found.
doc/ug/cern-title.tex
View file @
ce34f774
...
@@ -9,7 +9,7 @@
...
@@ -9,7 +9,7 @@
\noindent
\rule
{
\textwidth
}{
.1cm
}
\noindent
\rule
{
\textwidth
}{
.1cm
}
\hfill
September
26
, 2014
\hfill
September
30
, 2014
\vspace*
{
3cm
}
\vspace*
{
3cm
}
...
...
doc/ug/conv-regs.tex
View file @
ce34f774
...
@@ -1550,7 +1550,7 @@ Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\
...
@@ -1550,7 +1550,7 @@ Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\
FRONTINV
FRONTINV
}
[
\emph
{
read-only
}
]: Front panel INV-TTL input state
}
[
\emph
{
read-only
}
]: Front panel INV-TTL input state
\\
\\
Line state at board input
\\
Bit 0 -- channel
1
\\
Bit 1 -- channel 2
\\
etc.
Line state at board input
\\
Bit 0 -- channel
A
\\
Bit 1 -- channel B
\\
Bit 2 -- channel C
\\
Bit 3 -- channel D
\end{small}
\end{small}
\item
\begin{small}
\item
\begin{small}
{
\bf
{
\bf
...
...
doc/ug/ug-conv-ttl-blo.tex
View file @
ce34f774
...
@@ -49,8 +49,21 @@
...
@@ -49,8 +49,21 @@
% Revision history
% Revision history
%------------------------------------------------------------------------------
%------------------------------------------------------------------------------
\pagebreak
\pagebreak
\addcontentsline
{
toc
}{
section
}{
Revision history
}
\thispagestyle
{
empty
}
\addcontentsline
{
toc
}{
section
}{
Licensing information
}
\section*
{
Licensing information
}
\noindent
This document is licensed under a Creative Commons Attribution-ShareAlike 4.0
International License. If you have not received a copy of the license along with this
work, see
\\
\url
{
http://creativecommons.org/licenses/by-sa/4.0/
}
\section*
{
Revision history
}
\section*
{
Revision history
}
\addcontentsline
{
toc
}{
section
}{
Revision history
}
\centerline
\centerline
{
{
...
@@ -77,8 +90,10 @@
...
@@ -77,8 +90,10 @@
12-08-2014
&
2.21
&
Small error corrections (
\textit
{
writereg
}
instead of
\textit
{
readreg
}
in Section~
\ref
{
sec:diag-remote-reset
}
,
12-08-2014
&
2.21
&
Small error corrections (
\textit
{
writereg
}
instead of
\textit
{
readreg
}
in Section~
\ref
{
sec:diag-remote-reset
}
,
and typo in Section~
\ref
{
sec:reprog-bitstreams
}
), and addition of how to read gateware version in
and typo in Section~
\ref
{
sec:reprog-bitstreams
}
), and addition of how to read gateware version in
Section~
\ref
{
sec:reprog-bitstreams
}
\\
Section~
\ref
{
sec:reprog-bitstreams
}
\\
26-09-2014
&
3.00
&
Added latest per-channel timestamp readout and line status registers.
\newline
26-09-2014
&
3.00
&
Added latest per-channel timestamp readout and line status registers.
\newline
\textbf
{
Note: this version changes the memory mapping of various modules
}
\\
\textbf
{
Note: this version changes the memory mapping of various modules
}
\\
30-09-2014
&
3.01
&
Added licensing information, made LSR.FRONTINV bits clearer (Appendix~
\ref
{
app:conv-regs-lsr
}
),
added fallback to golden bitstream as system error (Section~
\ref
{
sec:diag-syserr
}
)
\\
\hline
\hline
\end{tabular}
\end{tabular}
}
}
...
@@ -1334,11 +1349,14 @@ set when the error occurs, are shown in Table~\ref{tbl:syserr}.
...
@@ -1334,11 +1349,14 @@ set when the error occurs, are shown in Table~\ref{tbl:syserr}.
\centerline
\centerline
{
{
\rowcolors
{
2
}{
white
}{
gray
!
25
}
\rowcolors
{
2
}{
white
}{
gray
!
25
}
\begin
{
tabular
}{
l
l p
{
.
5
\textwidth
}}
\begin
{
tabular
}{
p
{
.
25
\textwidth
}
l p
{
.
5
\textwidth
}}
\hline
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Error
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Register
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Error
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Register
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\hline
\hline
Fallback to golden bitstream
&
SR.GWVERS
&
Error when booting from application bitstream,
fallback to golden bitstream occured
(
see Section~
\ref
{
sec:reprog
-
bitstreams
}
)
\\
I
$^
2
$
C timeout
&
SR.I
2
C
\_
WDTO
&
An I
$^
2
$
C transfer is not completed
I
$^
2
$
C timeout
&
SR.I
2
C
\_
WDTO
&
An I
$^
2
$
C transfer is not completed
within
24
~ms
(
see Section~
\ref
{
sec:comm
-
timeout
}
)
\\
within
24
~ms
(
see Section~
\ref
{
sec:comm
-
timeout
}
)
\\
I
$^
2
$
C error
&
SR.I
2
C
\_
ERR
&
Attempted to access a non
-
memory
-
mapped address via I
$^
2
$
C
\\
I
$^
2
$
C error
&
SR.I
2
C
\_
ERR
&
Attempted to access a non
-
memory
-
mapped address via I
$^
2
$
C
\\
...
@@ -1351,6 +1369,7 @@ set when the error occurs, are shown in Table~\ref{tbl:syserr}.
...
@@ -1351,6 +1369,7 @@ set when the error occurs, are shown in Table~\ref{tbl:syserr}.
%------------------------------------------------------------------------------
%------------------------------------------------------------------------------
% SUBSEC: LSR
% SUBSEC: LSR
%------------------------------------------------------------------------------
%------------------------------------------------------------------------------
\pagebreak
\subsection
{
Line state readout
}
\subsection
{
Line state readout
}
\label
{
sec:diag
-
line
-
stat
}
\label
{
sec:diag
-
line
-
stat
}
...
@@ -1367,16 +1386,16 @@ that show the state of the channel line at the board input. Figure~\ref{fig:line
...
@@ -1367,16 +1386,16 @@ that show the state of the channel line at the board input. Figure~\ref{fig:line
shows a diagram of this mapping, from the board input, through the on
-
board circuitry,
shows a diagram of this mapping, from the board input, through the on
-
board circuitry,
to the LSR.
to the LSR.
Note that while in TTL
-
BAR repetition mode, the state
\textit
{
no signal detect
}
block
(
see Section~
\ref
{
sec:pulse
-
rep
}
)
is reflected in the FRONTFS bits of the LSR, effectively
showing if a cable is plugged in or not. While in TTL repetition mode, the FRONTFS bits in the LSR
are unused.
\begin
{
figure
}
[
h
]
\begin
{
figure
}
[
h
]
\centerline
{
\includegraphics
[
width
=
.
95
\textwidth
]
{
fig
/
line
-
stat
}}
\centerline
{
\includegraphics
[
width
=
.
95
\textwidth
]
{
fig
/
line
-
stat
}}
\caption
{
\label
{
fig:line
-
stat
}
Readout of line state at board input
}
\caption
{
\label
{
fig:line
-
stat
}
Readout of line state at board input
}
\end
{
figure
}
\end
{
figure
}
Note that while in TTL
-
BAR repetition mode, the state
\textit
{
no signal detect
}
block
(
see Section~
\ref
{
sec:pulse
-
rep
}
)
is reflected in the LSR, effectively showing if a
cable is plugged in or not. While in TTL repetition mode, the FRONTFS bits in the LSR
are unused.
%==============================================================================
%==============================================================================
% SEC: Remote reprog
% SEC: Remote reprog
%==============================================================================
%==============================================================================
...
@@ -1631,7 +1650,7 @@ tools.
...
@@ -1631,7 +1650,7 @@ tools.
There is also the possibility of obtaining raw bitstream files corresponding to the various
There is also the possibility of obtaining raw bitstream files corresponding to the various
versions of the FPGA gateware. The user can find the bitstream files by following the appropriate
versions of the FPGA gateware. The user can find the bitstream files by following the appropriate
link for the sought gateware version on the OHWR gateware releases webpage for the
link for the sought gateware version on the OHWR gateware releases webpage for the
CONV
-
TTL
-
BLO~
\cite
{
ctb
-
f
w
-
releases
}
.
CONV
-
TTL
-
BLO~
\cite
{
ctb
-
g
w
-
releases
}
.
%======================================================================================
%======================================================================================
% Appendices
% Appendices
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment