Commit 8cdeb506 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Update userguide with info about ring buffer and pulse rejection

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 27f89c97
\subsection{Converter board registers}
\label{app:conv-regs}
Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
Base address: 0x000
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
......@@ -67,7 +67,7 @@ gateware version, the state of the on-board switches and whether an RTM is plugg
\begin{itemize}
\item \begin{small}
{\bf
BITS
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424c4f
......@@ -86,7 +86,7 @@ Reset value: 0x54424c4f
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}PMISSE} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
......@@ -116,7 +116,7 @@ Leftmost nibble hex value is major release decimal value \\
SWITCHES
} [\emph{read-only}]: Status of on-board switches
\\
0 -- switch is ON \\ 1 -- switch is OFF \\ bit 0 -- SW1.1 \\ bit 1 -- SW1.2 \\ ... \\ bit 4 -- SW2.1 \\ ... \\ bit 7 -- SW2.4
0 -- switch is ON \\ 1 -- switch is OFF \\ bit 0 -- SW1.1 \\ ... \\ bit 4 -- SW2.1 \\ ... \\ bit 7 -- SW2.4
\end{small}
\item \begin{small}
{\bf
......@@ -140,6 +140,20 @@ WRPRES
1 -- White Rabbit present \\ 0 -- White Rabbit not present
\end{small}
\item \begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle
\end{small}
\item \begin{small}
{\bf
PMISSE
} [\emph{read/write}]: Pulse missed error
\\
1 -- input pulse rejected to safeguard blocking output stage \\ 0 -- idle
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
......
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......@@ -66,7 +66,7 @@
23-12-2013 & 1.05 & Added remote reprogramming support \\
10-01-2014 & 1.06 & Added SNMP access sub-section \\
06-03-2014 & 2.00 & Added support for diagnostics \\
26-03-2014 & 2.10 & Changed max. pulse repetition frequency, replaced the timetag FIFO for a
31-03-2014 & 2.10 & Changed max. pulse repetition frequency, replaced the timetag FIFO for a
ring buffer \\
\hline
\end{tabular}
......@@ -227,17 +227,21 @@ LEDs are \textit{off}.
\hline
\multicolumn{1}{c}{\textbf{LED}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{PW} & Power LED. Lights \textit{green} when a valid CONV-TTL-BLO gateware is loaded
to the FPGA. \\
\textit{ERR} & Error LED. Lights \textit{red} when no RTM board is present, \textit{off} if a
valid RTM is present. \\
\textit{TTL} & TTL status LED. Lights \textit{green} when TTL logic is selected
via the on-board selection switch, \textit{off} when TTL-BAR logic is selected. \\
\textit{I2C} & I$^2$C status LED. Flashes \textit{green} when an I$^2$C transfer is taking place.
Lights \textit{red} when a transfer error occurs, or when the CONV-TTL-BLO register
being addressed does not exist. After a transfer error, the LED will still flash
\textit{green} on transfer and return to a \textit{red} color after the transfer has
ended; it can only be turned back \textit{off} via a system reset.\\
\textit{PW} & Power LED \newline
-- \textbf{Green} when a valid CONV-TTL-BLO gateware is loaded
to the FPGA \\
\textit{ERR} & Error LED \newline
-- \textbf{Orange} when no RTM board is present \newline
-- \textbf{Red} when a system error occured \\ % (see Section~\ref{sec:diag-syserr) \\
\textit{TTL} & TTL status LED \newline
-- \textbf{Green} when TTL logic is selected via the on-board selection switch \newline
-- \textbf{Off} when TTL-BAR logic is selected. \\
\textit{I2C} & I$^2$C status LED \newline
-- \textbf{Flashes green} when an I$^2$C transfer takes places \newline
-- \textbf{Red} when an attempt is made to read/write an invalid register address \newline
-- After a transfer error, the LED will still \textbf{flash green} on transfer and return
to a \textbf{red} color after the transfer has ended \newline
-- The LED can only be turned back \textbf{off} via a system reset \\
\hline
\end{tabular}
}
......@@ -409,7 +413,7 @@ pulses.
$V_{OL}$ & Output pulse low-level amplitude & & 0 & 0.7 & V \\
$t_{p,i}$& Input pulse width & 100 & & & ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 600 & & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 241 & & & ${\mu}s$ \\
$t_r$ & Rise time & 1 & 3.2 & 4.9 & ns \\
$t_f$ & Fall time & 2 & 4 & 5.6 & ns \\
\hline
......@@ -440,7 +444,7 @@ by the FPGA gateware. \\
$V_{OL}$ & Output pulse low-level amplitude (2) & & 0 & & V \\
$t_{p,i}$& Input pulse width & 100 & & 3900& ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 600 & & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 241 & & & ${\mu}s$ \\
$t_r$ & Rise time & 75 & 140 & 225 & ns \\
$t_f$ & Fall time & 75 & 160 & 225 & ns \\
\hline
......@@ -507,8 +511,16 @@ plugged into a channel.
The pulse generator (PG) block in the FPGA generates $t_{p,o}$ wide (Table~\ref{tbl:pulse-def-ttl})
TTL pulses at its output on the rising edge of its input. It therefore expects TTL pulses at
its input. For more information about the implementation of the PG block, refer to the
CONV-TTL-BLO HDL Guide~\cite{ctb-hdlguide}.
its input. Once a TTL pulse arrives at the input of the PG block, it extends this pulse (or cuts it)
to $t_{p,o}$ and then enters a rejection state, where no more pulses are accepted on the input. The
basic operation of the PG block is shown in Figure~\ref{fig:pg-op}. For more information
about the implementation of the PG block, refer to the CONV-TTL-BLO HDL Guide~\cite{ctb-hdlguide}.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/pg-op}}
\caption{Pulse generator block operation}
\label{fig:pg-op}
\end{figure}
The rest of the logic external to the PG block is used to accommodate for TTL-BAR
and blocking pulses. First, the OR gates at the PG input indicate the condition for a pulse to
......@@ -603,14 +615,13 @@ signal lines and thus unwanted pulses on the output of the CONV-TTL-BLO. When th
environment is not so noisy, or when the 50~ns jitter is deemed to be an issue, SW1.1
can be left in the \textbf{OFF} position.
\pagebreak
\begin{figure}[h]
\centerline{\includegraphics[width=.6\textwidth,keepaspectratio]{fig/tpd-jit}}
\centerline{\includegraphics[width=\textwidth,keepaspectratio]{fig/tpd-jit}}
\caption{Output pulse delay and jitter}
\label{fig:tpd-jit}
\end{figure}
\pagebreak
\begin{table}[h]
\caption{Output pulse delay and jitter}
\label{tbl:pulse-tpd-jit}
......@@ -1220,6 +1231,45 @@ error is reported.
\label{fig:man-trig-fsm}
\end{figure}
%------------------------------------------------------------------------------
% SUBSEC: System Errors
%------------------------------------------------------------------------------
\subsection{System errors}
\label{sec:diag-syserr}
Various system errors are defined on converter boards. When such an error occurs,
the ERR LED on the front panel lights up in \textit{red}. At this point, the user
should connect to the converter board to see exactly what caused the system error.
The system errors defined for the CONV-TTL-BLO, together with the relevant bits
set when the error occurs, are shown in Table~\ref{tbl:syserr}.
\begin{table}[h]
\caption{System errors on the CONV-TTL-BLO}
\label{tbl:syserr}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l p{.5\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Error}} & \multicolumn{1}{c}{\textbf{Register}} &
\multicolumn{1}{c}{\textbf{Description}} \\
\hline
I$^2$C timeout & SR.I2C\_WDTO & The I$^2$C communication control contains a watchdog
timer which resets the I$^2$C communication in case
it takes too long to complete a transfer. If a transfer
is not completed within 24~ms, this error is thrown. \\
Missed pulse & SR.PMISS & As shown in Figure~\ref{fig:pg-op}, the PG block rejects
input pulses within a period of $T_{min}$. If any pulses
arrive within $T_{min}$ of another pulse, they are not
replicated on the output and this error is thrown. \newline
Use the \textbf{tsdiff.py} script to diagnose the channel
which caused this error. \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% SEC: Remote reprog
%==============================================================================
......@@ -1475,6 +1525,13 @@ contain the the most up-to-date information on the available test scripts. Other
the source c.ode in the test scripts themselves provide the documentation for these software
tools.
\subsection{Raw bitstream files}
There is also the possibility of obtaining raw bitstream files corresponding to the various
versions of the FPGA gateware. The user can find the bitstream files by following the appropriate
link for the sought gateware version on the OHWR gateware releases webpage for the
CONV-TTL-BLO~\cite{ctb-fw-releases}.
%======================================================================================
% Appendices
%======================================================================================
......
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