Commit 2904e984 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Update userguide to add ring buffer info

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 17a7bc21
\subsection{Converter board registers}
\label{app:conv-regs}
Base address: 0x000
Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.45\textwidth}}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name}
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
......@@ -15,27 +15,27 @@ Base address: 0x000
\endhead
\hline
\endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & Undefined (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0x00000000 & TVLR & Time Value Low Register\\
0x28 & 0x00000000 & TVHR & Time Value High Register\\
0x2c & 0x00000000 & TFMR & Tag FIFO Meta Register\\
0x30 & 0x00000000 & TFCYR & Tag FIFO Cycles Register \\
0x34 & 0x00000000 & TFTLR & Tag FIFO TAI Low Register \\
0x38 & 0x00000000 & TFTHR & Tag FIFO TAI High Register \\
0x3c & 0x00020000 & TFCSR & Tag FIFO Control and Status Register \\
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0x00000000 & TVLR & Time Value Low Register\\
0x28 & 0x00000000 & TVHR & Time Value High Register\\
0x2c & 0x00000000 & TBMR & Tag Buffer Meta Register\\
0x30 & 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
0x34 & 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
0x38 & 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
0x3c & 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
\end{longtable}
}
\noindent Note 1: The SR is undefined on startup due to the fact that the
gateware version, switches and RTM fields may have different values.
\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
......@@ -47,19 +47,19 @@ gateware version, switches and RTM fields may have different values.
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31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[7:0]}\\
\hline
\end{tabular}
}
......@@ -176,14 +176,14 @@ WRPRES
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 - Reset bit unlocked \\ 0 - Reset bit locked
1 -- Reset bit unlocked \\ 0 -- Reset bit locked
\end{small}
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit
\\
1 - initiate logic reset \\ 0 - no reset
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
\item \begin{small}
{\bf
......@@ -496,8 +496,9 @@ Writing this field resets the internal cycles counter.
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFMR -- Tag FIFO Meta Register}
\label{app:conv-regs-tfmr}
\vspace{11pt}
\subsubsection{TBMR -- Tag Buffer Meta Register}
\label{app:conv-regs-tbmr}
\vspace{11pt}
\noindent
......@@ -540,9 +541,13 @@ WRTAG
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\item \begin{small}
\textbf{A read from this register advances the buffer read pointer, if the ring buffer is not empty}
\end{small}
\end{itemize}
\subsubsection{TFCYR -- Tag FIFO Cycles Register}
\label{app:conv-regs-tfcyr}
\vspace{11pt}
\subsubsection{TBCYR -- Tag Buffer Cycles Register}
\label{app:conv-regs-tbcyr}
\vspace{11pt}
\noindent
......@@ -550,19 +555,19 @@ WRTAG
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31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CYC[27:24]}\\
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}TBCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[7:0]}\\
\hline
\end{tabular}
}
......@@ -570,7 +575,7 @@ WRTAG
\begin{itemize}
\item \begin{small}
{\bf
CYC
TBCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
......@@ -579,8 +584,9 @@ Value of the 8-ns cycles counter when time tag was taken.
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFTLR -- Tag FIFO TAI Low Register }
\label{app:conv-regs-tftlr}
\vspace{11pt}
\subsubsection{TBTLR -- Tag Buffer TAI Low Register}
\label{app:conv-regs-tbtlr}
\vspace{11pt}
\noindent
......@@ -588,19 +594,19 @@ Value of the 8-ns cycles counter when time tag was taken.
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31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[31:24]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[23:16]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[15:8]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[7:0]}\\
\hline
\end{tabular}
}
......@@ -608,7 +614,7 @@ Value of the 8-ns cycles counter when time tag was taken.
\begin{itemize}
\item \begin{small}
{\bf
TAI\_L
TBTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
......@@ -617,10 +623,11 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken.
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFTHR -- Tag FIFO TAI High Register}
\label{app:conv-regs-tfthr}
\vspace{11pt}
\subsubsection{TBTHR -- Tag Buffer TAI High Register}
\label{app:conv-regs-tbthr}
%\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -638,7 +645,7 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken.
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_H[7:0]}\\
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTHR[7:0]}\\
\hline
\end{tabular}
}
......@@ -646,7 +653,7 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken.
\begin{itemize}
\item \begin{small}
{\bf
TAI\_H
TBTHR
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
......@@ -655,8 +662,9 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken.
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{TFCSR -- Tag FIFO Control and Status Register }
\label{app:conv-regs-tfcsr}
\vspace{11pt}
\subsubsection{TBCSR -- Tag Buffer Control and Status Register}
\label{app:conv-regs-tbcsr}
\vspace{11pt}
\noindent
......@@ -668,7 +676,7 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken.
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CLEAR\_BUS} & \multicolumn{1}{|c|}{\cellcolor{gray!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
\multicolumn{1}{|c}{-} & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CLR} & \multicolumn{1}{|c|}{\cellcolor{gray!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
......@@ -684,33 +692,31 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken.
\begin{itemize}
\item \begin{small}
{\bf
FULL
} [\emph{read-only}]: FIFO full flag
USEDW
} [\emph{read-only}]: Buffer counter
\\
1: FIFO is full\\0: FIFO is not full
Number of samples in the ring buffer
\end{small}
\item \begin{small}
{\bf
EMPTY
} [\emph{read-only}]: FIFO empty flag
FULL
} [\emph{read-only}]: Buffer full
\\
1: FIFO is empty\\0: FIFO is not empty
1 -- buffer full \\ 0 -- buffer is not full
\end{small}
\item \begin{small}
{\bf
CLEAR\_BUS
} [\emph{write-only}]: FIFO clear
EMPTY
} [\emph{read-only}]: Buffer empty
\\
write 1: clears FIFO \\write 0: no effect\\
Note that a clear will not delete the data in the FIFO, just bring the
read and write pointers at the same position.\\
1 -- buffer empty\\ 0 -- buffer is not empty
\end{small}
\item \begin{small}
{\bf
USEDW
} [\emph{read-only}]: FIFO counter
CLR
} [\emph{write-only}]: Clear tag buffer
\\
Number of data records currently being stored in FIFO.
1 -- clear\\ 0 -- no effect
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
......
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sodipodi:role="line"
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xml:space="preserve"><tspan
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<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
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xml:space="preserve"><tspan
style="font-size:8px"
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style="font-size:8px"
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sodipodi:role="line">FULL = 0</tspan><tspan
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sodipodi:role="line">USEDW = 0</tspan></text>
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y="62.143356"
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xml:space="preserve"><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="62.143356"
x="44.29134"
sodipodi:role="line"
id="tspan4482">Before pulse arrival,</tspan><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="75.893356"
x="44.29134"
sodipodi:role="line"
id="tspan4489">or after buffer clear</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="44.29134"
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sodipodi:linespacing="125%"><tspan
id="tspan4495"
sodipodi:role="line"
x="44.29134"
y="185.18987"
style="font-size:11px;text-align:end;text-anchor:end">One pulse arrives,</tspan><tspan
sodipodi:role="line"
x="44.29134"
y="198.93987"
style="font-size:11px;text-align:end;text-anchor:end"
id="tspan4499">advancing write</tspan><tspan
sodipodi:role="line"
x="44.29134"
y="212.68987"
style="font-size:11px;text-align:end;text-anchor:end"
id="tspan4648">pointer</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4501"
y="309.20563"
x="30.024872"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
id="tspan4505"
style="font-size:11px;text-align:end;text-anchor:end"
y="309.20563"
x="30.024872"
sodipodi:role="line">Three more pulses</tspan><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="322.95563"
x="30.024872"
sodipodi:role="line"
id="tspan4509">arrive, filling up</tspan><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="336.70563"
x="30.024872"
sodipodi:role="line"
id="tspan4654">the ring buffer</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="-79.724411"
y="432.28345"
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sodipodi:linespacing="125%"><tspan
id="tspan4515"
sodipodi:role="line"
x="-79.724411"
y="432.28345"
style="font-size:10px;text-align:start;text-anchor:start" /></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="37.085419"
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sodipodi:linespacing="125%"><tspan
id="tspan4523"
sodipodi:role="line"
x="37.085419"
y="420.72137"
style="font-size:11px;text-align:end;text-anchor:end">One more pulse arrives,</tspan><tspan
sodipodi:role="line"
x="37.085419"
y="434.47137"
style="font-size:11px;text-align:end;text-anchor:end"
id="tspan4539">one timetag overwritten,</tspan><tspan
sodipodi:role="line"
x="37.085419"
y="448.22137"
style="font-size:11px;text-align:end;text-anchor:end"
id="tspan4541">read pointer advances</tspan><tspan
sodipodi:role="line"
x="37.085419"
y="461.97137"
style="font-size:11px;text-align:end;text-anchor:end"
id="tspan4668">with write pointer</tspan></text>
<text
sodipodi:linespacing="125%"
id="text4529"
y="178.93987"
x="434.05515"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="178.93987"
x="434.05515"
sodipodi:role="line"
id="tspan4533">Read from TBMR,</tspan><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="192.68987"
x="434.05515"
sodipodi:role="line"
id="tspan4690">advancing read</tspan><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="206.43987"
x="434.05515"
sodipodi:role="line"
id="tspan4694">pointer</tspan></text>
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xml:space="preserve"><tspan
style="font-size:8px"
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sodipodi:role="line">EMPTY = 0</tspan><tspan
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sodipodi:role="line">FULL = 1</tspan><tspan
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sodipodi:role="line">USEDW = 0</tspan></text>
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xml:space="preserve"><tspan
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style="font-size:11px;text-align:end;text-anchor:end"
y="55.893356"
x="435.87839"
sodipodi:role="line">Read from TBCYR, TBTLR,</tspan><tspan
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x="435.87839"
sodipodi:role="line"
id="tspan4590">or TBHR, read pointer</tspan><tspan
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x="435.87839"
sodipodi:role="line"
id="tspan4592">does not advance</tspan></text>
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sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="434.05515"
y="316.42487"
style="font-size:11px;text-align:end;text-anchor:end"
id="tspan4636">Two more TBMR reads</tspan></text>
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id="text4606"
y="414.47137"
x="434.05515"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="414.47137"
x="434.05515"
sodipodi:role="line"
id="tspan4610">One more TBMR read,</tspan><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="428.22137"
x="434.05515"
sodipodi:role="line"
id="tspan4704">emptying the buffer,</tspan><tspan
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x="434.05515"
sodipodi:role="line"
id="tspan4730">any more reads will</tspan><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="455.72137"
x="434.05515"
sodipodi:role="line"
id="tspan4734">not advance the</tspan><tspan
style="font-size:11px;text-align:end;text-anchor:end"
y="469.47137"
x="434.05515"
sodipodi:role="line"
id="tspan4738">read pointer</tspan></text>
<text
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y="71.226364"
x="-115.15748"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:18px;font-weight:bold;text-align:center;text-anchor:middle"
y="71.226364"
x="-115.15748"
id="tspan4614"
sodipodi:role="line">1.</tspan></text>
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="-115.15748"
y="195.36076"
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sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan4618"
x="-115.15748"
y="195.36076"
style="font-size:18px;font-weight:bold;text-align:center;text-anchor:middle">2.</tspan></text>
<text
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id="text4620"
y="319.37653"
x="-115.15748"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
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y="319.37653"
x="-115.15748"
id="tspan4622"
sodipodi:role="line">3.</tspan></text>
<text
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id="tspan4626"
x="-115.15748"
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style="font-size:18px;font-weight:bold;text-align:center;text-anchor:middle">4.</tspan></text>
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x="283.46457"
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y="195.36076"
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style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
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x="283.46457"
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sodipodi:role="line">6.</tspan></text>
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sodipodi:role="line">8.</tspan></text>
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......@@ -6,7 +6,7 @@ Base address: 0x040
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name}
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
......
......@@ -134,7 +134,7 @@ pulses (see Section~\ref{sec:pulse-def}). The main features of the board are:
\item unique board ID and temperature readout
\item state of on-board switches and RTM detection lines
\item input pulse counters
\item input pulse time-tagging
\item input pulse timetagging
\item manual pulse triggering
\item remotely reset the FPGA logic
\end{itemize}
......@@ -408,7 +408,7 @@ pulses.
$V_{OL}$ & Output pulse low-level amplitude & & 0 & 0.7 & V \\
$t_{p,i}$& Input pulse width & 100 & & & ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 6 & & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 600 & & & ${\mu}s$ \\
$t_r$ & Rise time & 1 & 3.2 & 4.9 & ns \\
$t_f$ & Fall time & 2 & 4 & 5.6 & ns \\
\hline
......@@ -439,7 +439,7 @@ by the FPGA gateware. \\
$V_{OL}$ & Output pulse low-level amplitude (2) & & 0 & & V \\
$t_{p,i}$& Input pulse width & 100 & & 3900& ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 6 & & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 600 & & & ${\mu}s$ \\
$t_r$ & Rise time & 75 & 140 & 225 & ns \\
$t_f$ & Fall time & 75 & 160 & 225 & ns \\
\hline
......@@ -546,7 +546,7 @@ rising edge is detected on the output of the OR gate between the two inputs type
details about the pulse counters can be found in Section~\ref{sec:diag-pulse-cnt}.
A rising edge on a pulse also triggers storing the value of a user-settable time tag to
a first-in-first-out (FIFO) memory. More details about the time-tagging of pulses
a first-in-first-out (FIFO) memory. More details about the timetagging of pulses
can be found in Section~\ref{sec:diag-pulse-timetag}.
The PG block can also be triggered by a "manual" pulse. More details about this feature
......@@ -764,7 +764,7 @@ password:**********
\label{sec:comm-snmp}
The second method to access the CONV-TTL-BLO board is via the Simple Network
Management Protocol (SNMP). ELMA crates offer an Management Information Base (MIB)
Management Protocol (SNMP). ELMA crates offer a Management Information Base (MIB)
which provide access to various information such as voltage and current sensor
readout, fan speeds and information about VME slots. Among the information about
the VME slots one can access register values for both read and write.
......@@ -1003,26 +1003,30 @@ The architecture of the time-tagging mechanism is shown in Figure~\ref{fig:timet
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/timetag-arch}}
\caption{Time-tag architecture}
\caption{Time-tagging architecture}
\label{fig:timetag-arch}
\end{figure}
Every time a pulse arrives on a channel, a time-tag sample is stored to a 128-deep
FIFO memory and the head of the FIFO advances. The head of the FIFO always points to the
last received pulse, as long as the FIFO is not full. When the FIFO is full, no more
time-tag samples are stored until the FIFO is read.
Every time a pulse arrives on a channel, a timetag sample is stored to a 128-deep
ring buffer. While this ring buffer is not entirely accessible in the addressing
space of the FPGA, it can be read sample by sample by reading the TBCYR, TBL/HR and
TBMR registers (see Appendix~\ref{app:conv-regs}).
Two time-tags are available on the CONV-TTL-BLO. These time-tags are listed in
%------------------------------------------------------------------------------
\subsubsection{Pulse timetags}
%------------------------------------------------------------------------------
Two timetags are available on the CONV-TTL-BLO. These timetags are listed in
Table~\ref{tbl:timetags}. When White-Rabbit (WR) is present, the precise centralized
and synchronized timing from the WR network is used. When WR is not present, the local
time tag is used. Note that due to the fact that this time-tag is unsynchronized,
time tag is used. Note that due to the fact that this timetag is unsynchronized,
it will differ slightly between two different boards in a crate.
Each time-tag sample consists of a cycles value, which counts 8~ns cycles, and a TAI seconds
Each timetag sample consists of a cycles value, which counts 8~ns cycles, and a TAI seconds
value.
\begin{table}[h]
\caption{Time tag types}
\caption{Timetag types}
\label{tbl:timetags}
\centerline
{
......@@ -1033,62 +1037,149 @@ value.
& \multicolumn{1}{c}{\textbf{Description}} \\
\hline
WR & 8~ns & \textbf{\textit{Currently not implemented}} \newline
Precise, centralized and synchronized time-tag \newline
Obtained and configurable via WR \newline
Resolution: \textbf{8~ns} \\
Local & 8~ns & Local, unsynchronized time-tag \newline
Precise, centralized and synchronized timetag \newline
Obtained and configurable via WR \\
Local & 8~ns & Local, unsynchronized timetag \newline
Obtained by counting the ticks of a 125~MHz clock signal \newline
Configurable by writing the TAI value registers (TVL/HR) \newline
Resolution: \textbf{8~ns} \\
Configurable by writing the TAI value registers (TVL/HR) \\
\hline
\end{tabular}
}
\end{table}
The FIFO memory is not entirely accessible in the addressing space,
instead the head of the FIFO is always accessible via the meta, cycle and TAI tag
FIFO registers in the converter board registers (TFMR, TFCYR, TFTL/HR -- see
Appendix~\ref{app:conv-regs}).
%------------------------------------------------------------------------------
\subsubsection{Timetag storage delay}
%------------------------------------------------------------------------------
The tag FIFO cycle and TAI registers (TFCYR, TFTL/HR) contain the actual time tag
values. The tag FIFO meta register (TFMR) completes these registers with information
about the current FIFO time-tag sample, such as the channel number that triggered
the storing of the current time tag and whether this time-tag was obtained via WR
or not.
Due to the internal logic of the FPGA, there is a delay of three to four 8~ns cycles
between the moment when a pulse arrives on the channel input and the moment when
a timetag is stored to the FIFO. This delay is shown in Figure~\ref{fig:timetag-delay}.
The control and status register (TFCSR -- see Appendix~\ref{app:conv-regs-tfcsr}) can
be used to check the status of the FIFO and clearing it. Note that clearing the FIFO
will not erase the memory, but simply bring the read and write pointers of the FIFO
to the same position.
\begin{figure}[h]
\centerline{\includegraphics[width=.8\textwidth]{fig/timetag-delay}}
\caption{Timetag storage delay}
\label{fig:timetag-delay}
\end{figure}
Also note that in order to properly read a time tag value in the FIFO and advance
the read pointer, a read from the TFMR is needed. If the user only reads one of the
other registers without reading the TFMR, the read pointer of the FIFO will not
advance. A full read cycle of a FIFO sample should look like this:
%------------------------------------------------------------------------------
\subsubsection{Reading the timetags}
%------------------------------------------------------------------------------
\begin{itemize}
\item read TFMR to obtain meta data about the tag FIFO sample and advance
the FIFO read pointer
\item read TFCYR to obtain the number of 8~ns cycles when the sample was stored
\item read TFTLR to obtain the lower part of the TAI counter
\item read TFTHR to obtain the upper part of the TAI counter
\end{itemize}
The TBCYR, TBTLR and TBTHR (see Appendix~\ref{app:conv-regs}) contain the actual
timetag values; the TBMR qualifies these timetag values with meta data such as
which channel triggered the timetag sample and whether a timestamp comes from WR
or from the local timer.
The E (empty) or F (full) bits of the TFCSR can be used to know when to stop reading
the FIFO. Of the two, it is recommended to use the E bit and read the FIFO while
this bit is cleared ('0'). When the FIFO is full of samples, the FPGA will not store
any more samples and the F bit will be set. Note that the USED field will indicate 0
samples stored at this time.
These registers always point to the oldest timetag in the ring buffer, and
reading them returns subsequent timetags in the buffer.
\begin{figure}[h]
\centerline{\includegraphics[width=.7\textwidth]{fig/timetag-delay}}
\caption{Time-tag storage delay}
\label{fig:timetag-delay}
In order to obtain the correct timetags from the ring buffer, the read sequence
shown in Table~\ref{tbl:timetag-rd-seq} should be performed. This sequence should be
performed as long as the buffer is not empty (the first step is true).
For more details on the ring buffer, see the next subsection.
\setcounter{rownr}{0}
\begin{table}[h]
\caption{Timetag read sequence}
\label{tbl:timetag-rd-seq}
\centerline {
\rowcolors{2}{white}{gray!25}
\begin{tabular}{c p{.8\textwidth}}
\hline
\textbf{Step} & \multicolumn{1}{c}{\textbf{Action}} \\
\hline
\rownumber & \textbf{Read the TBCSR} and make sure that the EMPTY bit is not '1' \\
\rownumber & \textbf{Read the TBCYR} to obtain the 8~ns cycles counter value \\
\rownumber & \textbf{Read the TBTLR} to obtain the lower part of the TAI seconds counter \\
\rownumber & \textbf{Read the TBTHR} to obtain the upper part of the TAI seconds counter \\
\rownumber & \textbf{Read the TBTMR} to obtain the meta data about the timetag sample and advance
the buffer read pointer \\
\hline
\end{tabular}
}
\end{table}
%------------------------------------------------------------------------------
\subsubsection{Ring buffer mechanics}
%------------------------------------------------------------------------------
The 128-deep ring buffer implemented in the FPGA gateware contains a read and a write
pointer, each of which advances on a read from and respectively a write to the buffer.
If the buffer is not empty, the read pointer points to the oldest timetag stored in the
buffer, while the write pointer points to the next buffer location to be written.
Figure~\ref{fig:timetag-buf-mech} shows the operation of the ring buffer.
\begin{figure}[t]
\centerline{\includegraphics[width=\textwidth]{fig/timetag-buf-mech}}
\caption{Ring buffer mechanics, example with four-sample-deep buffer}
\label{fig:timetag-buf-mech}
\end{figure}
Due to the internal logic of the FPGA, there is a delay of three to four 8~ns cycles
between the moment when a pulse arrives on the channel input and the moment when
a time-tag is stored to the FIFO. This delay is shown in Figure~\ref{fig:timetag-delay}.
Every time a pulse arrives on an input channel, a timetag is stored to the ring buffer
and the write pointer of the ring buffer is advanced.
When the write pointer reaches the read pointer, the buffer is full and subsequent writes
will overwrite previously written data, while the read pointer is advanced together with
the write pointer.
To read from the buffer, the user reads the TBCYR, TBTLR, TBTHR and TBMR (see Appendix~\ref{app:conv-regs}).
Reading the TBTMR register advances the read pointer of the buffer, if the buffer is not empty. If the
buffer is empty, the read pointer of the buffer is not advanced.
Note that due to the fact that a read from the TBMR advances the read pointer, the TBMR
should be the last register read in a read sequence. Otherwise, the read pointer is advanced
and the contents of the TBMR will correspond to one sample in the ring buffer, while
the contents of the TBCYR and TBH/LR will be that of another sample.
The TBCSR (see Appendix~\ref{app:conv-regs-tbcsr}) contains bits that allow to check the
status and clear the buffer. The USEDW field in this register contains the current number
of samples written to the buffer. When the buffer is full, the USEDW field is 0 and the
FULL bit is set. Setting the CLR bit of the TBCSR will bring the read and write pointers
to 0 and set the USEDW field to 0.
%The FIFO memory is not entirely accessible in the addressing space,
%instead the head of the FIFO is always accessible via the meta, cycle and TAI tag
%FIFO registers in the converter board registers (TFMR, TFCYR, TFTL/HR -- see
%Appendix~\ref{app:conv-regs}).
%
%The tag FIFO cycle and TAI registers (TFCYR, TFTL/HR) contain the actual time tag
%values. The tag FIFO meta register (TFMR) completes these registers with information
%about the current FIFO timetag sample, such as the channel number that triggered
%the storing of the current time tag and whether this timetag was obtained via WR
%or not.
%
%The control and status register (TFCSR -- see Appendix~\ref{app:conv-regs-tfcsr}) can
%be used to check the status of the FIFO and clearing it. Note that clearing the FIFO
%will not erase the memory, but simply bring the read and write pointers of the FIFO
%to the same position.
%
%Also note that in order to properly read a time tag value in the FIFO and advance
%the read pointer, a read from the TFMR is needed. If the user only reads one of the
%other registers without reading the TFMR, the read pointer of the FIFO will not
%advance. A full read cycle of a FIFO sample should look like this:
%
%\begin{itemize}
% \item read TFMR to obtain meta data about the tag FIFO sample and advance
% the FIFO read pointer
% \item read TFCYR to obtain the number of 8~ns cycles when the sample was stored
% \item read TFTLR to obtain the lower part of the TAI counter
% \item read TFTHR to obtain the upper part of the TAI counter
%\end{itemize}
%
%The E (empty) or F (full) bits of the TFCSR can be used to know when to stop reading
%the FIFO. Of the two, it is recommended to use the E bit and read the FIFO while
%this bit is cleared ('0'). When the FIFO is full of samples, the FPGA will not store
%any more samples and the F bit will be set. Note that the USED field will indicate 0
%samples stored at this time.
%
%\begin{figure}[h]
% \centerline{\includegraphics[width=.7\textwidth]{fig/timetag-delay}}
% \caption{timetag storage delay}
% \label{fig:timetag-delay}
%\end{figure}
%------------------------------------------------------------------------------
% SUBSEC: Remote reset
......
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