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Commit 1587f7d0 authored by Projects's avatar Projects
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test/pulse_rejection: test to check frequency limit error

parent 72ee1356
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software/tests/pulse_rejection.py
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......@@ -204,3 +204,55 @@ for test in tests:
print("waiting %d seconds of cool-down period" % cooldown_time)
time.sleep(cooldown_time)
###############################################################################
# test FLIM_MISSED bit (pulses with too high frequency)
pulses = 10000
freq = max_freq * 1.2
# clear counters
for ch in convttl.CHANNELS:
convttl.pulse_counter_set(ch, (0, 0))
# clear errors (including missed pulse flags)
convttl.error.error_reg = convttl.error.ERRORS_MASK
print("")
print("------")
print("")
print("TEST: reject pulses at too high frequency (FLIM_MISSED bit)")
print("Start the pulse burst generator (%d pulses at %d Hz" % (pulses, freq))
print(" ./pulsegen.py -c %d -f %F" % (pulses, freq))
print("")
test_run = True
while(test_run):
counters = convttl.pulse_counters
errors = convttl.error.error_reg
if(old_counters != counters):
print(counters)
old_counters = counters
for ch in convttl.CHANNELS:
if old_counters[ch - 1][0] != 0 and old_counters[ch - 1][1] != 0:
print("WARNING: Both pulse counters are increasing, check if it is ok")
pulse_count = max(old_counters[ch - 1])
# check if there were any pulses missed
if convttl.error.ERRORS_MASK_FLIM_MISSED(ch) & errors:
if convttl.error.ERRORS_MASK_FWDG_MISSED(ch) & errors:
print("WARNING: FLIM_WDG bit is set for channel %d" % (ch))
print("TEST PASSED: FLIM_MISSED flag set on channel %d" % (ch))
test_run = False
break
if(pulse_count >= pulses):
print("TEST FAILED: repeated %d pulses, FLIM_MISSED flag has not been set" % (pulse_count))
sys.exit(2)
print("ALL TESTS PASSED!")
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