Commit 031bfba1 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Update user guide with gw v2.1 information

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent e6cc7134
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill March 26, 2014
\hfill April 8, 2014
\vspace*{3cm}
......
......@@ -109,14 +109,14 @@ Reset value: 0x54424c4f
GWVERS
} [\emph{read-only}]: Gateware version
\\
Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x1e -- v1.14 \\ 0x20 -- v2.0
Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x2e -- v2.14
\end{small}
\item \begin{small}
{\bf
SWITCHES
} [\emph{read-only}]: Status of on-board switches
} [\emph{read-only}]: Status of on-board switches (see Section~\ref{sec:switches})
\\
0 -- switch is ON \\ 1 -- switch is OFF \\ bit 0 -- SW1.1 \\ ... \\ bit 4 -- SW2.1 \\ ... \\ bit 7 -- SW2.4
0 -- switch is ON \\ 1 -- switch is OFF
\end{small}
\item \begin{small}
{\bf
......@@ -144,14 +144,14 @@ WRPRES
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle
1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
PMISSE
} [\emph{read/write}]: Pulse missed error
\\
1 -- input pulse rejected to safeguard blocking output stage \\ 0 -- idle
1 -- input pulse rejected to safeguard blocking output stage \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
......
......@@ -9,8 +9,8 @@
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......@@ -66,7 +66,7 @@
23-12-2013 & 1.05 & Added remote reprogramming support \\
10-01-2014 & 1.06 & Added SNMP access sub-section \\
06-03-2014 & 2.00 & Added support for diagnostics \\
31-03-2014 & 2.10 & Changed max. pulse repetition frequency, replaced the timetag FIFO for a
08-04-2014 & 2.10 & Changed max. pulse repetition frequency, replaced the timetag FIFO for a
ring buffer \\
\hline
\end{tabular}
......@@ -231,17 +231,14 @@ LEDs are \textit{off}.
-- \textbf{Green} when a valid CONV-TTL-BLO gateware is loaded
to the FPGA \\
\textit{ERR} & Error LED \newline
-- \textbf{Orange} when no RTM board is present \newline
-- \textbf{Red} when a system error occured \\ % (see Section~\ref{sec:diag-syserr) \\
-- \textbf{Red} when a system error occured (see Section~\ref{sec:diag-syserr}) \newline
-- \textbf{Off} otherwise \\
\textit{TTL} & TTL status LED \newline
-- \textbf{Green} when TTL logic is selected via the on-board selection switch \newline
-- \textbf{Off} when TTL-BAR logic is selected. \\
\textit{I2C} & I$^2$C status LED \newline
-- \textbf{Flashes green} when an I$^2$C transfer takes places \newline
-- \textbf{Red} when an attempt is made to read/write an invalid register address \newline
-- After a transfer error, the LED will still \textbf{flash green} on transfer and return
to a \textbf{red} color after the transfer has ended \newline
-- The LED can only be turned back \textbf{off} via a system reset \\
-- \textbf{Off} otherwise \\
\hline
\end{tabular}
}
......@@ -328,11 +325,13 @@ When a pulse is repeated on the output connector of a channel, the pulse status
\label{sec:switches}
There are eight switches provided on-board the CONV-TTL-BLO, only two of which are
used. Figure~\ref{fig:switches} shows the switches and highlights the used ones;
the used switches are also listed in Table~\ref{tbl:switches}.
used. Figure~\ref{fig:switches} shows the switches and highlights the used ones, which
are also listed in Table~\ref{tbl:switches}. The status of all on-board switches can be
read from the board's status register (SR -- see Appendix~\ref{app:conv-regs-sr}.
Figure~\ref{fig:sr-switches} shows how the switches map to the SR.
\begin{figure}[htbp]
\centerline{\includegraphics[scale=.75]{fig/switches}}
\centerline{\includegraphics[scale=.65]{fig/switches}}
\caption{Switches on the CONV-TTL-BLO board}
\label{fig:switches}
\end{figure}
......@@ -358,6 +357,12 @@ the used switches are also listed in Table~\ref{tbl:switches}.
}
\end{table}
\begin{figure}[h]
\centerline{\includegraphics[width=.5\textwidth]{fig/sr-switches}}
\caption{Switch mapping to the SR}
\label{fig:sr-switches}
\end{figure}
Note that both switches in Table~\ref{tbl:switches} are board-wide switches; selecting
one position or the other yields a selection valid for all six pulse replication channels.
......@@ -1255,10 +1260,14 @@ set when the error occurs, are shown in Table~\ref{tbl:syserr}.
\multicolumn{1}{c}{\textbf{Error}} & \multicolumn{1}{c}{\textbf{Register}} &
\multicolumn{1}{c}{\textbf{Description}} \\
\hline
I$^2$C timeout & SR.I2C\_WDTO & The I$^2$C communication control contains a watchdog
I$^2$C timeout & SR.I2C\_WDTO & The I$^2$C communication controller contains a watchdog
timer which resets the I$^2$C communication in case
it takes too long to complete a transfer. If a transfer
is not completed within 24~ms, this error is thrown. \\
it takes too long to complete a transfer. The longest
I$^2$C transfer (using \textit{writemregs}) should take
no longer than approx. 4~ms. If a transfer is not completed
within 24~ms, this error is thrown. \\
I$^2$C error & SR.I2C\_ERR & This error is thrown in case a non-memory-mapped address
is accessed via I$^2$C. \\
Missed pulse & SR.PMISS & As shown in Figure~\ref{fig:pg-op}, the PG block rejects
input pulses within a period of $T_{min}$. If any pulses
arrive within $T_{min}$ of another pulse, they are not
......
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