diff --git a/doc/ug/cern-title.tex b/doc/ug/cern-title.tex
index 927b6ddd8ddcabb4dbf013b242d0876dd7cd84cb..5f6cd71a3ca599482f19296c68b12be3525b18cc 100644
--- a/doc/ug/cern-title.tex
+++ b/doc/ug/cern-title.tex
@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
-\hfill September 30, 2014
+\hfill February 09, 2017
\vspace*{3cm}
@@ -24,7 +24,8 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
-\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
+\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}\\
+\noindent { \textit{Last modified by Denia Bouhired-Ferrag (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
diff --git a/doc/ug/conv_regs.tex b/doc/ug/conv_regs.tex
new file mode 100644
index 0000000000000000000000000000000000000000..23074f99145162b03c34ed4bd07527c9bc144361
--- /dev/null
+++ b/doc/ug/conv_regs.tex
@@ -0,0 +1,1840 @@
+\subsection{Converter board registers}
+\label{app:conv-regs}
+
+Base address: 0x000
+{
+\rowcolors{2}{white}{gray!25}
+\begin{longtable}{l l l p{.5\textwidth}}
+\hline
+\textbf{Offset} & \textbf{Reset} & \textbf{Name}
+ & \textbf{Description} \\
+\hline
+\endfirsthead
+\hline
+\textbf{Offset} & \textbf{Reset} & \textbf{Name}
+ & \textbf{Description} \\
+\hline
+\endhead
+\hline
+\endfoot
+0x0& 0x54424c4f & BIDR & Board ID Register\\
+0x4& Note(1)& SR & Status Register\\
+0x8& 0x00000000 & ERR & Error Register\\
+0xc& 0x00000000 & CR & Control Register\\
+0x10& 0x00000000 & CH1TTLPCR & Channel 1 TTL Pulse Counter Register\\
+0x14& 0x00000000 & CH2TTLPCR & Channel 2 TTL Pulse Counter Register\\
+0x18& 0x00000000 & CH3TTLPCR & Channel 3 TTL Pulse Counter Register\\
+0x1c& 0x00000000 & CH4TTLPCR & Channel 4 TTL Pulse Counter Register\\
+0x20& 0x00000000 & CH5TTLPCR & Channel 5 TTL Pulse Counter Register\\
+0x24& 0x00000000 & CH6TTLPCR & Channel 6 TTL Pulse Counter Register\\
+0x28& 0x00000000 & CH1BLOPCR & Channel 1 BLO Pulse Counter Register\\
+0x2c& 0x00000000 & CH2BLOPCR & Channel 2 BLO Pulse Counter Register\\
+0x30& 0x00000000 & CH3BLOPCR & Channel 3 BLO Pulse Counter Register\\
+0x34& 0x00000000 & CH4BLOPCR & Channel 4 BLO Pulse Counter Register\\
+0x38& 0x00000000 & CH5BLOPCR & Channel 5 BLO Pulse Counter Register\\
+0x3c& 0x00000000 & CH6BLOPCR & Channel 6 BLO Pulse Counter Register\\
+0x40& 0x00000000 & TVLR & Time Value Low Register\\
+0x44& 0x00000000 & TVHR & Time Value High Register\\
+0x48& 0x00000000 & TBMR & Tag Buffer Meta Register\\
+0x4c& 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
+0x50& 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
+0x54& 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
+0x58& 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
+0x5c& 0x00000000 & CH1LTSCYR & Channel 1 Latest Timestamp Cycles Register\\
+0x60& 0x00000000 & CH1LTSTLR & Channel 1 Latest Timestamp TAI Low Register\\
+0x64& 0x00000000 & CH1LTSTHR & Channel 1 Latest Timestamp TAI High Register\\
+0x68& 0x00000000 & CH2LTSCYR & Channel 2 Latest Timestamp Cycles Register\\
+0x6c& 0x00000000 & CH2LTSTLR & Channel 2 Latest Timestamp TAI Low Register\\
+0x70& 0x00000000 & CH2LTSTHR & Channel 2 Latest Timestamp TAI High Register\\
+0x74& 0x00000000 & CH3LTSCYR & Channel 3 Latest Timestamp Cycles Register\\
+0x78& 0x00000000 & CH3LTSTLR & Channel 3 Latest Timestamp TAI Low Register\\
+0x7c& 0x00000000 & CH3LTSTHR & Channel 3 Latest Timestamp TAI High Register\\
+0x80& 0x00000000 & CH4LTSCYR & Channel 4 Latest Timestamp Cycles Register\\
+0x84& 0x00000000 & CH4LTSTLR & Channel 4 Latest Timestamp TAI Low Register\\
+0x88& 0x00000000 & CH4LTSTHR & Channel 4 Latest Timestamp TAI High Register\\
+0x8c& 0x00000000 & CH5LTSCYR & Channel 5 Latest Timestamp Cycles Register\\
+0x90& 0x00000000 & CH5LTSTLR & Channel 5 Latest Timestamp TAI Low Register\\
+0x94& 0x00000000 & CH5LTSTHR & Channel 5 Latest Timestamp TAI High Register\\
+0x98& 0x00000000 & CH6LTSCYR & Channel 6 Latest Timestamp Cycles Register\\
+0x9c& 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
+0xa0& 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
+0xa4& Note(2) & LSR & Line Status Register\\
+0xa8& 0x00000000 & OSWR & Other switch resistor\\
+0xac& Unique ID & UIDLR & Thermometer ID Low register\\
+0xb0& Unique ID & UIDHR & Thermometer ID High register\\
+0xb4& 0x00000000 & TEMPR & Board Temperature Register\\
+\hline
+\end{longtable}
+}
+
+\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
+gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
+
+
+
+\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
+is plugged into the channel or not.
+
+\vspace{11pt}
+\subsubsection{BIDR -- Board ID Register}
+\label{app:conv-regs-BIDR}
+
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+BIDR
+} [\emph{read-only}]: ID register bits
+\\
+Reset value: 0x54424c4f
+\end{small}
+\item \begin{small}
+\textbf{Unimplemented bits}: write as '0', read undefined
+\end{small}
+\end{itemize}
+\vspace{11pt}
+
+\subsubsection{SR -- Status Register}
+\label{app:conv-regs-SR}
+
+
+\vspace{11pt}
+
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{4}{|c|}{\cellcolor{gray!25}HWVERS[5:2]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{2}{|c|}{\cellcolor{gray!25}HWVERS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[7:0]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}GWVERS[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+GWVERS
+} [\emph{read-only}]: Gateware version
+\\
+Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x2e -- v2.14
+\end{small}
+\item \begin{small}
+{\bf
+SWITCHES
+} [\emph{read-only}]: Status of on-board general-purpose switches
+\\
+Eg: SW1.1-- SR.SWITCHES[0] \\ SW1.2-- SR.SWITCHES[1] \\ SW2.1-- SR.SWITCHES[4] \\ SW2.4-- SR.SWITCHES[7] \\ 1 -- switch is ON \\ 0 -- switch is OFF
+\end{small}
+\item \begin{small}
+{\bf
+RTM
+} [\emph{read-only}]: RTM detection lines cite{rtm-det}
+\\
+1 bit per RTM output channel \\ 1 -- line active \\ 0 -- line inactive
+\end{small}
+\item \begin{small}
+{\bf
+HWVERS
+} [\emph{read-only}]: Hardware version
+\\
+PCB version - Hardwired on the board \\ Only meaningful for HW v4.0 and over \\ Earlier versions show 0. The register \\ uses 4 bits for the version number and\\ 2 bits for the execution.\\ e.g. \\ 0x010001 -- hw v4.1 \\ 0x010111 -- hw v5.3 \\ 0x00-- hw v3 and earlier
+\end{small}
+\item \begin{small}
+{\bf
+WRPRES
+} [\emph{read-only}]: White Rabbit present
+\\
+1 -- White Rabbit present \\ 0 -- White Rabbit not present
+\end{small}
+\end{itemize}
+\subsubsection{ERR - Error Register}
+\label{app:conv-regs-ERR}
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}FWDG\_PMISSE[5:0]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{6}{|c|}{\cellcolor{gray!25}FLIM\_PMISSE[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+I2C\_WDTO
+} [\emph{read/write}]: I2C communication watchdog timeout error
+\\
+1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
+\end{small}
+\item \begin{small}
+{\bf
+I2C\_ERR
+} [\emph{read/write}]: I2C communication error
+\\
+1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
+\end{small}
+\item \begin{small}
+{\bf
+FLIM\_PMISSE
+} [\emph{read/write}]: Frequency error
+\\
+1 -- Input above maximum supported frequency \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
+\end{small}
+\item \begin{small}
+{\bf
+FWDG\_PMISSE
+} [\emph{read/write}]: Frequency watchdog error
+\\
+1 -- Pulse over maximum pulse count for given frequency' \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
+\end{small}
+\end{itemize}
+\subsubsection{CR - Control Register}
+\label{app:conv-regs-CR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{2}{|c|}{\cellcolor{gray!25}MPT[7:6]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{6}{|c|}{\cellcolor{gray!25}MPT[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+RST\_UNLOCK
+} [\emph{read/write}]: Reset unlock bit
+\\
+1 -- Reset bit unlocked \\ 0 -- Reset bit locked
+\end{small}
+\item \begin{small}
+{\bf
+RST
+} [\emph{read/write}]: Reset bit - active only if RST_UNLOCK is 1
+\\
+1 -- initiate logic reset \\ 0 -- no reset
+\end{small}
+\item \begin{small}
+{\bf
+MPT
+} [\emph{write-only}]: Manual Pulse Trigger
+\\
+Write the following sequence to trigger a pulse: \\ 0xde -- Byte 1 of magic sequence \\ 0xad -- Byte 2 of magic sequence \\ 0xbe -- Byte 3 of magic sequence \\ 0xef -- Byte 4 of magic sequence \\ Number in range 1..6 -- trigger a pulse
+\end{small}
+\item \begin{small}
+\textbf{Unimplemented bits}: write as '0', read undefined
+\end{small}
+\end{itemize}
+
+\subsubsection{CH1TTLPCR - Channel 1 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH1TTLPCR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH1TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+
+
+\subsubsection{CH2TTLPCR - Channel 2 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH2TTLPCR}
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH2TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{CH3TTLPCR - Channel 3 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH3TTLPCR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH3TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+
+
+\subsubsection{CH4TTLPCR - Channel 4 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH4TTLPCR}
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH4TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{CH5TTLPCR - Channel 5 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH5TTLPCR}
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH5TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{CH6TTLPCR - Channel 6 Pulse Counter Register for TTL pulses}
+\label{app:conv-regs-CH6TTLPCR}
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH6TTLPCR
+} [\emph{read/write}]: TTL pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{CH1BLOPCR - Channel 1 Pulse Counter Register for BLO pulses}
+\label{app:conv-regs-CH1BLOPCR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH1BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{CH2BLOPCR - Channel 2 Pulse Counter Register for BLO pulses}
+\label{app:conv-regs-CH2BLOPCR}
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH2BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{CH3BLOPCR - Channel 3 Pulse Counter Register for BLO pulses}
+\label{app:conv-regs-CH3BLOPCR}
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH3BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{CH4BLOPCR - Channel 4 Pulse Counter Register for BLO pulses}
+\label{app:conv-regs-CH4BLOPCR}
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH4BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{CH5BLOPCR - Channel 5 Pulse Counter Register for BLO pulses}
+\label{app:conv-regs-CH5BLOPCR}
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH5BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{CH6BLOPCR - Channel 6 Pulse Counter Register for BLO pulses}
+\label{app:conv-regs-CH6BLOPCR}
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH6BLOPCR
+} [\emph{read/write}]: BLO pulse counter value
+\end{small}
+\end{itemize}
+\subsubsection{TVLR - Time Value Low Register}
+\label{app:conv-regs-TVLR}
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TVLR
+} [\emph{read/write}]: TAI seconds counter bits 31..0
+\\
+Writing this field resets the internal cycles counter.
+\end{small}
+\end{itemize}
+\subsubsection{TVHR - Time Value High Register}
+\label{app:conv-regs-TVHR}
+
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TVHR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TVHR
+} [\emph{read/write}]: TAI seconds counter bits 39..32
+\\
+Writing this field resets the internal cycles counter.
+\end{small}
+\end{itemize}
+\subsubsection{TBMR - Tag Buffer Meta Register}
+\label{app:conv-regs-TBMR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}CHAN[5:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CHAN
+} [\emph{read-only}]: Channel mask
+\\
+Mask for the channel(s) that triggered time-tag storage: \\ bit 0 -- channel 1 \\ bit 1 -- channel 2 \\ ... \\ bit 5 -- channel 6
+\end{small}
+\item \begin{small}
+{\bf
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\subsubsection{TBCYR - Tag Buffer Cycles Register}
+\label{app:conv-regs-TBCYR}
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}TBCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TBCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{TBTLR - Tag Buffer TAI Low Register}
+\label{app:conv-regs-TBTLR}
+
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TBTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{TBTHR - Tag Buffer TAI High Register}
+\label{app:conv-regs-TBTHR}
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTHR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TBTHR
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{TBCSR - Tag Buffer Control and Status Register}
+\label{app:conv-regs-TBCSR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CLR} & \multicolumn{1}{|c|}{\cellcolor{gray!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{1}{|c}{-} & \multicolumn{7}{|c|}{\cellcolor{gray!25}USEDW[6:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+USEDW
+} [\emph{read-only}]: Buffer counter
+\\
+Number of samples in the ring buffer
+\end{small}
+\item \begin{small}
+{\bf
+FULL
+} [\emph{read-only}]: Buffer full
+\\
+1 -- buffer full \\ 0 -- buffer is not full
+\end{small}
+\item \begin{small}
+{\bf
+EMPTY
+} [\emph{read-only}]: Buffer empty
+\\
+1 -- buffer empty\\ 0 -- buffer is not empty
+\end{small}
+\item \begin{small}
+{\bf
+CLR
+} [\emph{read/write}]: Clear tag buffer
+\\
+1 -- clear\\ 0 -- no effect
+\end{small}
+\end{itemize}
+\subsubsection{CH1LTSCYR - Channel 1 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH1LTSCYR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH1LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH1LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH1LTSTLR - Channel 1 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH1LTSTLR}
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH1LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH1LTSTHR - Channel 1 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH1LTSTHR}
+
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\subsubsection{CH2LTSCYR - Channel 2 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH2LTSCYR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH2LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH2LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH2LTSTLR - Channel 2 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH2LTSTLR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH2LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH2LTSTHR - Channel 2 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH2LTSTHR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\subsubsection{CH3LTSCYR - Channel 3 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH3LTSCYR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH3LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH3LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH3LTSTLR - Channel 3 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH3LTSTLR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH3LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH3LTSTHR - Channel 3 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH3LTSTHR}
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\subsubsection{CH4LTSCYR - Channel 4 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH4LTSCYR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH4LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH4LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH4LTSTLR - Channel 4 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH4LTSTLR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH4LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH4LTSTHR - Channel 4 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH4LTSTHR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\subsubsection{CH5LTSCYR - Channel 5 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH5LTSCYR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH5LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH5LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH5LTSTLR - Channel 5 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH5LTSTLR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH5LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH5LTSTHR - Channel 5 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH5LTSTHR}
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\subsubsection{CH6LTSCYR - Channel 6 Latest Timestamp Cycles Register}
+\label{app:conv-regs-CH6LTSCYR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH6LTSCYR[27:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH6LTSCYR
+} [\emph{read-only}]: Cycles counter
+\\
+Value of the 8-ns cycles counter when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH6LTSTLR - Channel 6 Latest Timestamp TAI Low Register}
+\label{app:conv-regs-CH6LTSTLR}
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+CH6LTSTLR
+} [\emph{read-only}]: Lower part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 31..0 when time tag was taken.
+\end{small}
+\end{itemize}
+\subsubsection{CH6LTSTHR - Channel 6 Latest Timestamp TAI High Register}
+\label{app:conv-regs-CH6LTSTHR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TAI
+} [\emph{read-only}]: Upper part of TAI seconds counter
+\\
+Value of the TAI seconds counter bits 39..32 when time tag was taken.
+\end{small}
+\item \begin{small}
+{\bf
+WRTAG
+} [\emph{read-only}]: White Rabbit present
+\\
+1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
+\end{small}
+\end{itemize}
+\subsubsection{LSR - Line Status Register}
+\label{app:conv-regs-lsr}
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[3:2]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONTFS[5:0]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{6}{|c|}{\cellcolor{gray!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[3:2]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONT[5:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+FRONT
+} [\emph{read-only}]: Front panel channel input state
+\\
+Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
+\end{small}
+\item \begin{small}
+{\bf
+FRONTINV
+} [\emph{read-only}]: Front panel INV-TTL input state
+\\
+Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
+\end{small}
+\item \begin{small}
+{\bf
+REAR
+} [\emph{read-only}]: Rear panel input state
+\\
+Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
+\end{small}
+\item \begin{small}
+{\bf
+FRONTFS
+} [\emph{read-only}]: Front panel input failsafe state
+\\
+High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
+\end{small}
+\item \begin{small}
+{\bf
+FRONTINVFS
+} [\emph{read-only}]: Front panel inverter input failsafe state
+\\
+High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
+\end{small}
+\item \begin{small}
+{\bf
+REARFS
+} [\emph{read-only}]: Rear panel input failsafe state
+\\
+High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
+\end{small}
+\end{itemize}
+\subsubsection{OSWR - Other Switch Register}
+\label{app:conv-regs-OSWR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+SWITCHES
+} [\emph{read-only}]: Switch state
+\\
+1 -- switch is ON \\ 0 -- switch is OFF
+\end{small}
+\end{itemize}
+\subsubsection{UIDLR - 32 LS bits of 1-wire thermometer ID}
+\label{app:conv-regs-UIDLR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+UIDLR
+} [\emph{read-only}]: LS bits of 1-wire DS18B20U thermometer ID
+\end{small}
+\end{itemize}
+\subsubsection{UIDHR - 32 MS bits of 1-wire thermometer ID}
+\label{app:conv-regs-UIDHR}
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[31:24]}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[23:16]}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+UIDHR
+} [\emph{read-only}]: MS bits of 1-wire DS18B20U thermometer ID
+\end{small}
+\end{itemize}
+\subsubsection{TEMPR - Temperature Resgister }
+\label{app:conv-regs-TEMPR}
+Raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to ${}^{o}C$ as follows: Temp = register value / 16.0
+
+\vspace{11pt}
+\noindent
+\resizebox{\textwidth}{!}{
+\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
+31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
+\hline
+\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\hline
+15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TEMPR[15:8]}\\
+\hline
+7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
+\hline
+\multicolumn{8}{|c|}{\cellcolor{gray!25}TEMPR[7:0]}\\
+\hline
+\end{tabular}
+}
+
+\begin{itemize}
+\item \begin{small}
+{\bf
+TEMPR
+} [\emph{read-only}]: TEMP
+\\
+Current on-board temperature
+\end{small}
+\end{itemize}
+
+
+
diff --git a/doc/ug/fig/conv-freq-limit-short.png b/doc/ug/fig/conv-freq-limit-short.png
new file mode 100644
index 0000000000000000000000000000000000000000..e84c0c1d8ea8e794eb9f4ee12ee01aafb5b10c82
Binary files /dev/null and b/doc/ug/fig/conv-freq-limit-short.png differ
diff --git a/doc/ug/fig/conv-freq-limit.png b/doc/ug/fig/conv-freq-limit.png
new file mode 100644
index 0000000000000000000000000000000000000000..97e669173564a3dcc80fb9c80af2017aeaa4102e
Binary files /dev/null and b/doc/ug/fig/conv-freq-limit.png differ
diff --git a/doc/ug/fig/pulse-rep.svg b/doc/ug/fig/pulse-rep.svg
index 5f825ffd5772aef9f5695bd1eeef4ab0542d0189..13fa82fd110a779c27e68c6ac7b85eecf55ef1a3 100644
--- a/doc/ug/fig/pulse-rep.svg
+++ b/doc/ug/fig/pulse-rep.svg
@@ -9,11 +9,11 @@
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
- width="691.80365"
- height="373.37128"
+ width="712.15442"
+ height="381.71997"
id="svg2"
version="1.1"
- inkscape:version="0.92.0 r"
+ inkscape:version="0.92.1 r15371"
sodipodi:docname="pulse-rep.svg">
<defs
id="defs4">
@@ -55,23 +55,24 @@
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
- inkscape:zoom="5.6"
- inkscape:cx="321.81952"
- inkscape:cy="202.27254"
+ inkscape:zoom="1.4"
+ inkscape:cx="414.35863"
+ inkscape:cy="159.26571"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
inkscape:window-width="1920"
- inkscape:window-height="1143"
- inkscape:window-x="0"
- inkscape:window-y="0"
+ inkscape:window-height="1138"
+ inkscape:window-x="-8"
+ inkscape:window-y="-8"
inkscape:window-maximized="1"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0"
showguides="true"
- inkscape:guide-bbox="true">
+ inkscape:guide-bbox="true"
+ borderlayer="false">
<inkscape:grid
type="xygrid"
id="grid3765"
@@ -82,8 +83,8 @@
units="mm"
spacingx="1.8897638"
spacingy="1.8897638"
- originx="2.0398632"
- originy="-782.65192" />
+ originx="2.9929882"
+ originy="-774.30315" />
</sodipodi:namedview>
<metadata
id="metadata7">
@@ -93,7 +94,7 @@
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
- <dc:title />
+ <dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
@@ -101,7 +102,7 @@
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
- transform="translate(2.0398642,33.503491)">
+ transform="translate(2.9929892,33.503491)">
<path
style="fill:none;stroke:#000000;stroke-width:1.06666672px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 451.65354,139.84255 h -7.55906"
@@ -122,15 +123,16 @@
<path
inkscape:connector-curvature="0"
id="path9972"
- d="m 462.99213,166.29924 h -11.33858 v -60.47244 -3e-5"
- style="fill:none;stroke:#000000;stroke-width:1.06666672px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="m 472.44095,168.18899 h -20.7874 v -28.34645 -1e-5"
+ style="fill:none;stroke:#000000;stroke-width:0.98882633px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="cccc" />
<path
- style="fill:none;stroke:#000000;stroke-width:1.06666672px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
- d="m 434.64566,190.86618 h 17.00789 v -15.11812 h 13.22834"
+ style="fill:none;stroke:#000000;stroke-width:1.19256938px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="m 432.64567,192.75593 h 21.25987 v -15.11812 h 16.53541"
id="path9391"
inkscape:connector-curvature="0"
- sodipodi:nodetypes="cccc" />
+ sodipodi:nodetypes="cccc"
+ inkscape:transform-center-x="-2.5253814" />
<path
inkscape:connector-curvature="0"
id="path3908"
@@ -788,7 +790,7 @@
sodipodi:nodetypes="cccc"
inkscape:connector-curvature="0"
id="path9389"
- d="m 460.03569,162.79408 c 5.50467,7.33956 5.50467,11.00933 0,18.3489 12.84422,0 22.01868,0 27.52336,-9.17445 -5.50468,-9.17445 -14.67914,-9.17445 -27.52336,-9.17445 z"
+ d="m 468.44095,163.28891 c 5.50467,7.33956 5.50467,11.00933 0,18.3489 12.84422,0 22.01868,0 27.52336,-9.17445 -5.50468,-9.17445 -14.67914,-9.17445 -27.52336,-9.17445 z"
style="fill:#ffffff;fill-opacity:1;stroke:#000000;stroke-width:0.53333336;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" />
<g
id="g9940"
@@ -836,12 +838,12 @@
<circle
id="path3169"
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.53333336;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1"
- cx="451.65353"
- cy="105.82681"
+ cx="197.96826"
+ cy="128.35983"
r="1.8897637" />
<g
id="g5647"
- transform="translate(-37.789721,3.0485755)">
+ transform="translate(-122.84021,-6.400234)">
<rect
style="fill:none;stroke:#000000;stroke-width:0.6447947;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1"
id="rect3173"
@@ -954,7 +956,7 @@
</g>
<g
id="g4793"
- transform="translate(-178.27746,328.97569)">
+ transform="translate(18.900359,174.01984)">
<g
transform="matrix(1.1101827,0,0,1.0001417,-73.642548,-296.60296)"
id="g4720">
@@ -979,12 +981,12 @@
sodipodi:role="line"
id="tspan4714"
x="500.09079"
- y="197.05409"
+ y="197.07095"
style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:11.38815212px;line-height:15px;font-family:Sans;-inkscape-font-specification:'Sans, Bold';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;writing-mode:lr-tb;text-anchor:middle">Counter</tspan></text>
</g>
</g>
<g
- transform="matrix(0.95970453,0,0,1.0003743,-3.384771,19.088879)"
+ transform="matrix(0.95970453,0,0,1.0003743,193.83146,-141.54103)"
id="g4720-4">
<g
id="g4757"
@@ -1012,14 +1014,14 @@
sodipodi:role="line"
id="tspan4751"
x="471.88083"
- y="196.95934"
+ y="196.96614"
style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.2470417px;font-family:Sans;-inkscape-font-specification:'Sans, Bold';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;writing-mode:lr-tb;text-anchor:middle">Counter</tspan></text>
</g>
</g>
</g>
<g
id="g5789"
- transform="translate(-2.8496696,94.456201)"
+ transform="matrix(1,0,0,3.196604,-2.8496696,-59.914356)"
style="stroke-width:0.5;stroke-miterlimit:4;stroke-dasharray:none">
<rect
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1"
@@ -1029,20 +1031,22 @@
x="547.99933"
y="68.40213" />
<text
- transform="scale(1.0535774,0.94914716)"
+ transform="scale(1.6279361,0.61427473)"
xml:space="preserve"
- style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.64466572px;line-height:15.80590057px;font-family:Sans;-inkscape-font-specification:'Sans, Bold';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.5;stroke-miterlimit:4;stroke-dasharray:none"
- x="530.2951"
- y="84.455421"
+ style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:11.59900761px;line-height:14.49882221px;font-family:Sans;-inkscape-font-specification:'Sans, Bold';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.4586522;stroke-miterlimit:4;stroke-dasharray:none"
+ x="343.16177"
+ y="125.27641"
id="text9397-5-8"><tspan
sodipodi:role="line"
id="tspan5777"
- x="530.2951"
- y="84.455421">BC</tspan><tspan
+ x="343.16177"
+ y="125.27641"
+ style="font-size:5.47265196px;stroke-width:0.4586522">BC</tspan><tspan
sodipodi:role="line"
id="tspan5779"
- x="530.2951"
- y="100.26132"></tspan></text>
+ x="343.16177"
+ y="141.53552"
+ style="stroke-width:0.4586522" /></text>
</g>
<path
style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
@@ -1051,30 +1055,18 @@
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
- style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
- d="m 340.15749,262.67717 h 28.34645"
+ style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:0.63245565px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="m 451.65355,102.04725 h 11.33858"
id="path5613"
inkscape:connector-curvature="0" />
<path
- style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
- d="m 340.15749,215.43307 h 28.34645"
+ style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:0.63245565px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="m 451.65355,73.700797 h 11.33858"
id="path5615"
inkscape:connector-curvature="0" />
- <circle
- style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.53333336;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1"
- id="path4047-3"
- cx="368.54358"
- cy="215.43307"
- r="1.8897637" />
- <circle
- style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.53333336;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1"
- id="path4047-8"
- cx="368.60956"
- cy="262.67719"
- r="1.8897637" />
<path
- style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
- d="m 451.54332,104.04724 0.11023,-39.795272 h 11.33858"
+ style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.08187199px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="m 451.61501,139.84253 -0.0717,-71.590552 h -7.37711"
id="path5649"
inkscape:connector-curvature="0"
sodipodi:nodetypes="ccc" />
@@ -1114,5 +1106,74 @@
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.66666698px;font-family:Sans;-inkscape-font-specification:'Sans, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;writing-mode:lr-tb;text-anchor:start"
x="-1.1023616"
y="24.600677">BC: Burst Controller</tspan></text>
+ <path
+ style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="m 536.69292,64.251978 c 20.7874,0 20.7874,0 20.7874,0"
+ id="path4134"
+ inkscape:connector-curvature="0" />
+ <path
+ style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="m 536.69292,102.04725 h 39.68504 v -85.039367 0"
+ id="path4136"
+ inkscape:connector-curvature="0" />
+ <path
+ style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="m 557.48032,64.251978 h 9.44882 V 17.007883"
+ id="path4138"
+ inkscape:connector-curvature="0" />
+ <path
+ style="fill:none;stroke:#000000;stroke-width:0.97530484px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="M 566.92914,17.007883 H 198.4252 c 0,113.385827 0,113.385827 0,113.385827"
+ id="path4140"
+ inkscape:connector-curvature="0" />
+ <circle
+ id="path3169-1"
+ style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.53333336;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1"
+ cx="482.96826"
+ cy="258.35983"
+ r="0" />
+ <circle
+ id="path3169-8"
+ style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.53333336;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1"
+ cx="482.96826"
+ cy="258.35983"
+ r="0" />
+ <circle
+ id="path3169-19"
+ style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.53333336;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1"
+ cx="482.96826"
+ cy="258.35983"
+ r="0" />
+ <circle
+ id="path3169-0"
+ style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.53333336;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1"
+ cx="179.39684"
+ cy="319.07413"
+ r="1.8897637" />
+ <path
+ style="display:inline;fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="m 179.40546,320.96384 0.1221,26.75263"
+ id="path4222"
+ inkscape:connector-type="polyline"
+ inkscape:connector-curvature="0"
+ inkscape:connection-start="#path3169-0" />
+ <path
+ style="display:inline;fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="M 179.52756,347.71648 H 708.66142"
+ id="path4224"
+ inkscape:connector-type="polyline"
+ inkscape:connector-curvature="0" />
+ <path
+ style="display:inline;fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="M 708.66142,347.71648 V 17.00781"
+ id="path4226"
+ inkscape:connector-type="polyline"
+ inkscape:connector-curvature="0" />
+ <path
+ style="display:inline;fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
+ d="M 708.66142,17.00781 H 576.37796"
+ id="path4228"
+ inkscape:connector-type="polyline"
+ inkscape:connector-curvature="0" />
</g>
</svg>
diff --git a/doc/ug/ug-conv-ttl-blo.bib b/doc/ug/ug-conv-ttl-blo.bib
index ea0dfaa29b16e2d6f9eab682ed3944cde634a7bd..081d398a1bde365ce75b3b93d7c99db50ecd7cbb 100644
--- a/doc/ug/ug-conv-ttl-blo.bib
+++ b/doc/ug/ug-conv-ttl-blo.bib
@@ -49,7 +49,7 @@
@misc{sch,
title = {{CONV-TTL-BLO Schematics}},
- howpublished = {\url{https://edms.cern.ch/file/1278535/1/EDA-02446-V2-1_sch.pdf}}
+ howpublished = {\url{https://edms.cern.ch/file/1278535/1/EDA-02446-V4_sch.pdf}}
}
@misc{ctb-hwguide,
@@ -65,7 +65,7 @@
title = {{CONV-TTL-BLO HDL Guide}},
month = 07,
year = 2013,
- howpublished = {\url{http://www.ohwr.org/attachments/2326/hdlguide-conv-ttl-blo-v1.02.pdf}}
+ howpublished = {\url{http://www.ohwr.org/documents/290/hdlg-conv-ttl-blo-v4.0.pdf}}
}
@misc{gen-bitstream,
diff --git a/doc/ug/ug-conv-ttl-blo.tex b/doc/ug/ug-conv-ttl-blo.tex
index 705240c996a12831702de1bb3477dabe406f530d..e9166cc56a02210022633afe721f52ff14c84694 100644
--- a/doc/ug/ug-conv-ttl-blo.tex
+++ b/doc/ug/ug-conv-ttl-blo.tex
@@ -94,8 +94,7 @@ work, see \\
\textbf{Note: this version changes the memory mapping of various modules} \\
30-09-2014 & 3.01 & Added licensing information, made LSR.FRONTINV bits clearer (Appendix~\ref{app:conv-regs-lsr}),
added fallback to golden bitstream as system error (Section~\ref{sec:diag-syserr}) \\
- ??-01-2017 & 4.00 & FEDERICO EDITS \\
- 06-02-2017 & 4.00 & Added description of pulse-width select functionality, burst mode frequencies and PCB version read-out\\
+ 06-02-2017 & 4.00 & Added description of changes in v4, Eg: INV LEDs, pulse-width select functionality, burst mode opearation and PCB version read-out\\
\hline
\end{tabular}
}
@@ -151,9 +150,9 @@ pulses (see Section~\ref{sec:pulse-def}). The main features of the board are:
\item TTL to TTL
\item TTL-BAR to TTL-BAR
\end{itemize}
+ \item Four general-purpose inverter channels
\item Support for high frequency bursts
\item Selectable pulse width: 1.2 us for 50kHz-100kHz repetition frequencies, 250ns for 500kHz-2MHz repetition frequencies
- \item Four general-purpose inverter channels
\item Each input channel has 50~$\Omega$ input termination
\item Each channel capable of driving 50~$\Omega$ load
\item SFP connector
@@ -161,6 +160,7 @@ pulses (see Section~\ref{sec:pulse-def}). The main features of the board are:
\begin{itemize}
\item converter board ID
\item gateware version
+ \item hardware version
\item unique board ID and temperature readout
\item input line state readout
\item state of on-board switches and RTM detection lines
@@ -360,7 +360,7 @@ When a pulse is repeated on the output connector of a channel, the pulse status
There are eight switches provided on-board the CONV-TTL-BLO, only two of which are
used. Figure~\ref{fig:switches} shows the switches and highlights the used ones, which
are also listed in Table~\ref{tbl:switches}. The status of all on-board switches can be
-read from the board's status register (SR -- see Appendix~\ref{app:conv-regs-sr} and
+read from the board's status register (SR -- see Appendix~\ref{app:conv-regs-SR} and
Section~\ref{sec:diag-sw-rtmdet}).
\begin{figure}[htbp]
@@ -382,7 +382,7 @@ Section~\ref{sec:diag-sw-rtmdet}).
SW1.1 & Glitch filter enable (see Section~\ref{sec:pulse-jit}) \newline
\textbf{ON} -- glitch filter enabled, output jitter present \newline
\textbf{OFF} -- glitch filter disabled, no output jitter (default) \\
- SW1.2 & Pulse width \newline
+ SW1.2 & Pulse width select \newline
\textbf{ON} - short pulse width [250 ns] \newline
\textbf{OFF} - long pulse width [1.2 us] (default)\\
SW2.4 & TTL/TTL-BAR selection switch (see Section~\ref{sec:pulse-ttl-vs-ttlbar}) \newline
@@ -393,7 +393,7 @@ Section~\ref{sec:diag-sw-rtmdet}).
}
\end{table}
-Note that both switches in Table~\ref{tbl:switches} are board-wide switches; selecting
+Note that all switches in Table~\ref{tbl:switches} are board-wide switches; selecting
one position or the other yields a selection valid for all six pulse replication channels.
\textbf{\textit{It is recommended to not switch any of the switches while the board is plugged
@@ -532,9 +532,18 @@ before plugging the board into a crate.
%--------------------------------------------------------------------------------------
\subsection{Pulse repetition frequency}
\label{sec:pulse-rep-freq}
+
+\begin{figure}[htbp]
+ \centerline{\includegraphics[scale=.30]{fig/switch-vect-freq}}
+ \caption{Pulse width select switch}
+ \label{fig:switches-freq}
+\end{figure}
+
Version 2.1 and earlier of the CONV-TTL-BOARD supports continuous pulse repetition, restricting output
-pulse width to 1.2us and a maximum repetition frequency of 4.15 kHz.\\
-For boards v4 and later\footnote{Note that version 3 of the boards is a prototyping version with only 3 prototypes available. Although the hardware can support higher frequencies, the gateware release will not offer this feature on this version. This is due to these boards do not pffer the FPGA with the possibility of PCB version recognition (hardwired on V4 boards and later).}, the user is able to select the desired pulse width via a a dip switch as explained in section \cite{sec:switches}. This ability to select between long $1.2 \mu s$ pulses and short $250 ns$ pulses means that the board will be able to deliver higher repetition frequencies, but for a limited amount of time. This mode of operation is known as \textbf{Burst mode}. In this mode, the board allows the user to increase repetition frequencies but will start missing pulses once the pre-defined (Embedded in the FPGA) time has ellapsed. Table\cite{table:freq-table} below summaries the frequency ranges available. Figure \cite gives a graph of the supported frequencies in burst mode Vs the amount of time for which repetition is guaranteed. After this time has elapsed the board will start missing some pulses, by lowering its repetition frequency dynamically in order to protect the output circuitry from irreversible damage.
+pulse width to 1.2us and a maximum repetition frequency of 4.16 kHz.\\
+For boards v4 and later\footnote{Note that version 3 of the boards is a prototyping version with only 3 prototypes available. Although the hardware can support higher frequencies, the gateware release will not offer this feature on this version. This is because these boards do not have PCB or HW version recognition capability (hardwired on V4 boards and later), see Section \ref{sec:diag-pcbvers} of this document.}, the user is able to select the desired pulse width via a a dip switch as explained in Section \ref{sec:switches}. The switch is highlighted in in Fig.\ref{fig:switches-freq}. This ability to select between long $1.2 \mu s$ pulses and short $250 ns$ pulses means that the board will be able to deliver higher repetition frequencies if short pulses are selected.
+
+Moreover, for a given pulse width, the board is able to support higher frequencies for varying times, according to an internal thermal model that is designed to protect the board in the case of very high rate repetition. This mode of operation is known as the \textit{Burst mode}. In this mode, the board allows the user to increase repetition frequencies but will start missing pulses once the pre-defined (Embedded in the FPGA) times have ellapsed. Table~\ref{tbl:freq-table} below summaries the frequency ranges available. Figure~\ref{fig:BC-freq-lim} gives a graph of the supported frequencies in burst mode Vs the amount of time for which repetition is guaranteed. After this time has elapsed the board will start missing some pulses, by lowering its repetition frequency dynamically in order to protect the output circuitry from irreversible damage.
\begin{table}[h]
\caption{Maximum pulse repetition frequency}
@@ -544,17 +553,27 @@ For boards v4 and later\footnote{Note that version 3 of the boards is a prototyp
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l c c c c}
\hline
- \multicolumn{1}{c}{\textbf{Pulse width}} & \multicolumn{1}{c}{\textbf{Continuous mode}} &
+ \multicolumn{1}{c}{\textbf{Board version}} &\multicolumn{1}{c}{\textbf{Pulse width}} & \multicolumn{1}{c}{\textbf{Continuous mode}} &
\textbf{Burst mode} \\
\hline
- $250 ns$ & $555 kHz$ & $ 2MHz $ \\
+ v2.1-v3 & $1.2 \mu s$ & $4.16 kHz$ & N/A \\
\hline
- $1.2 \mu s$ & $50 kHz$ & $ 100kHz $ \\
+ v4.0 & $250 ns$ & $571 kHz$ & $ 2MHz $ \\
+ \hline
+ v4.0 & $1.2 \mu s$ & $52 kHz$ & $ 104kHz $ \\
\hline
\end{tabular}
}
\end{table}
+
+\begin{figure}[htbp]
+ \centerline{\includegraphics[width=.95\textwidth]{fig/conv-freq-limit}}
+
+ \centerline{\includegraphics[width=.95\textwidth]{fig/conv-freq-limit-short}}
+ \caption{High frequency repetition Vs time for available pulse widths}
+ \label{fig:BC-freq-lim}
+\end{figure}
%--------------------------------------------------------------------------------------
% SUBSEC: Rep details
%--------------------------------------------------------------------------------------
@@ -579,12 +598,36 @@ to $t_{p,o}$ and then enters a rejection state, where no more pulses are accepte
basic operation of the PG block is shown in Figure~\ref{fig:pg-op}. For more information
about the implementation of the PG block, refer to the CONV-TTL-BLO HDL Guide~\cite{ctb-hdlguide}.
+\begin{tabular}{p{.96\textwidth}}
+\hline
+\large \hspace*{22pt} Burst control block not activated for v3 boards and earlier \\
+\hline
+\end{tabular}
+After the PG block, a Burst Control (BC) block has been added for v4.0 boards (Corresponding
+to gateware release v4). For earlier versions of the board, this option is deactivated. The block
+implements a thermal model of the board. An internal counter
+emulates temperature rise when new pulses arrive, when the temperature counter reaches a pre-set
+maximum value (corresponding to maximum temperature), the burst controller starts missing
+pulses. This means that the board needs to \textit{cool off} between pulses and therefore
+implements rejection only as long as the temperature is above the maximum. As soon as recovery is
+achieved (temperature is again below maximum) the board starts repeating again.
+
+The time at which the rejection starts depends on the frequency of the pulses coming out of the
+PG block. For high frequencies, temperature will rise quickly and pulses are rejected earlier.
+The lower the frequency the longer are repetition times. Table \ref{tbl:freq-table}
+shows the maximum frequencies the block can handle. The continuous frequency limit represents the
+threshold at which the board can repeat frequencies continuously without requiring any \textit{
+cool-off} time, this means that the board is effectively not warming up at this particular rate
+of repetition. Figure \ref{fig:BC-freq-lim}, shows the supported frequencies as a function of the guaranteed
+repetition time limits. Error flags are raised when pulses are missed, Section \ref{sec:diag-syserr} discusses this in more detail.\\
+
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/pg-op}}
\caption{Pulse generator block operation}
\label{fig:pg-op}
\end{figure}
+
The rest of the logic external to the PG block is used to accommodate for TTL-BAR
and blocking pulses. First, the OR gates at the PG input indicate the condition for a pulse to
be regenerated. The conditions for pulse generation are either that pulse is manually triggered
@@ -594,8 +637,8 @@ as described in Section~\ref{sec:diag-man-trig}, or that a pulse arrives on eith
On the blocking side, the voltage level of blocking pulses arriving on the RTM is adapted
to a voltage level suitable for the FPGA by on-board circuitry external to the FPGA.
What ends up in the FPGA is a TTL type pulse, so this may be passed directly
-to the PG's input through the OR gate. The output of the PG block is passed to the FPGA
-output and to the three blocking pulse outputs of a channel, where the blocking-level
+to the PG's input through the OR gate. The output of the PG block is passed to the FPGA output, via the
+BC block in v4 boards, and to the three blocking pulse outputs of a channel, where the blocking-level
pulse is generated.
On the TTL side, pulse signals go through a Schmitt trigger inverter buffer to the FPGA.
@@ -617,9 +660,10 @@ After the two types of signals are ORed together to form a trigger to the PG blo
they can optionally be passed through a glitch filter (the GF block in Figure~\ref{fig:pulse-rep}).
More details about this glitch filter can be found in Section~\ref{sec:pulse-jit}.
-One pulse counter is implemented for each channel. This pulse counter increments when a
-rising edge is detected on the output of the OR gate between the two inputs types. More
-details about the pulse counters can be found in Section~\ref{sec:diag-pulse-cnt}.
+Two pulse counter is implemented for each channel, one for TTL/TTL-BAR pulses, one for BLO
+pulses. These pulse counters are incremented when a rising edge is detected on the output of the
+OR gate between the two inputs types. More details about the pulse counters can be found in
+Section~\ref{sec:diag-pulse-cnt}.
A rising edge on a pulse also triggers storing the value of a user-settable time tag to
a ring buffer memory. More details about the timetagging of pulses can be found in
@@ -716,17 +760,7 @@ can be left in the \textbf{OFF} position.
\noindent Note 1: If the glitch filter is enabled, it adds an extra 350~ns delay to $t_{PD}$. \\
\noindent Note 2: Measured visually using cursors on an oscilloscope.
-%--------------------------------------------------------------------------------------
-% SUBSEC: Pulse jitter and delay
-%--------------------------------------------------------------------------------------
-\subsection{Frequencies operation}
-\label{sec:freq-op}
-\begin{figure}[htbp]
- \centerline{\includegraphics[scale=.30]{fig/switch-vect-freq}}
- \caption{TTL/TTL-BAR selection switch}
- \label{fig:switches-ttl}
-\end{figure}
%======================================================================================
% SEC: Communicating to the CONV-TTL-BLO
@@ -794,7 +828,7 @@ data to the board. As names suggest, \textit{readreg} reads a board register, w
An example of retrieving the CONV-TTL-BLO ID of a CONV-TTL-BLO plugged into VME slot 2 of the crate
\textit{some-crate} is given below. The converter board ID can be retrieved from the board ID
-register at address \textbf{0x000} (BIDR -- see Appendix~\ref{app:conv-regs-bidr}),
+register at address \textbf{0x000} (BIDR -- see Appendix~\ref{app:conv-regs-BIDR}),
if the board is present in slot 2, the command should yield the ASCII string \textbf{TBLO}.
\begin{verbatim}
@@ -942,6 +976,7 @@ The following diagnostics features are implemented on the CONV-TTL-BLO:
\item converter board identification
\item reading the unique board ID and temperature
\item reading of the FPGA gateware version
+ \item reading of the PCB hardware version
\item reading the state of the on-board switches
\item reading the state of the RTM detection lines
\item input pulse counters
@@ -962,7 +997,7 @@ about the project repository.
\label{sec:diag-bid}
All converter boards have a board identification register (BIDR -- see
-Appendix~\ref{app:conv-regs-bidr}) at address \textbf{0x000}. This register is
+Appendix~\ref{app:conv-regs-BIDR}) at address \textbf{0x000}. This register is
a read-only 32-bit register containing the hex values for the ASCII code
describing the functionality of the converter board.
@@ -976,7 +1011,7 @@ for TTL-to-blocking converter.
\label{sec:diag-gwvers}
The gateware version can be read from the least significant eight bits of the
-status register (SR -- see Appendix~\ref{app:conv-regs-sr}). The gateware version
+status register (SR -- see Appendix~\ref{app:conv-regs-SR}). The gateware version
is split into major and minor version numbers. Both numbers are decimal numbers.
The major version number increments on major changes in the gateware, such as
the implementation of new blocks. The minor version increments on bug fixes.
@@ -986,14 +1021,20 @@ the implementation of new blocks. The minor version increments on bug fixes.
%------------------------------------------------------------------------------
\subsection{PCB version}
\label{sec:diag-pcbvers}
-The PCB version is necessary to the operation of the burst mode. Indeed the FPGA reads out the hardware version,
-and depending on whether the board is v4 and later or v3 earlier, will enable or disable this functionality accordingly.
-The PCB version is provided to the FPGA via a resistor network offering, 4 bits for the version number
- and 2 bits for potential revisions. The value is available in the SR register (SR -- see Appendix~\ref{app:conv-regs-sr})
-in two bytes.
-So for instance a v4.1 board will be given as "01000001", with the Least significant byte LSB providing the revision number,
-and the most significant byte MSB providing the version number. Note that the revision number is only 2 bits so the two most significant bits in the corresponding byte are just padding.\\
-Note also that PCB identification is not available in boards v3 and earlier, and therefore the HWVERS field in the SR register will read as all zeroes.
+The PCB version is necessary to the operation of the burst mode, see Section\ref{sec:pulse-rep-freq}.
+ Indeed the FPGA reads out the hardware version,
+and depending on whether the board is v4 and later or v3 earlier, will enable or disable this
+functionality accordingly.\\
+In v4 boards, the PCB version is provided to the FPGA via a resistor network implementing 4 bits
+for the version number
+ and 2 bits for potential revisions. The value is available in the SR register (SR -- see Appendix
+~\ref{app:conv-regs-SR})
+in 6 bits.
+So for instance a v4.1 board will be given as "010001", with the Least significant 2 bits
+providing the revision number,
+and the most significant byte providing the version number.\\
+Note also that PCB identification is not available in boards v3 and earlier, and therefore the
+HWVERS field in the SR register will read as all zeroes.
%------------------------------------------------------------------------------
% SUBSEC: Thermo, unique ID
%------------------------------------------------------------------------------
@@ -1012,34 +1053,8 @@ CONV-TTL-BLO boards contain a thermometer chip~\cite{ds18b20} which can be used
board temperature. This thermometer chip is also factory-programmed with a unique
ID which can be used to uniquely identify a CONV-TTL-BLO.
-To access this thermometer, the CONV-TTL-BLO uses a 1-wire interface~\cite{onewire-tech}.
-The thermometer is a one-wire slave and the FPGA on-board the CONV-TTL-BLO is
-a one-wire master in the communication (Appendix~\ref{app:memmap-thermo}).
-The FPGA on-board the CONV-TTL-BLO has also a driver for the thermometer chip
-which makes available the temperature and the unique ID values without accessing
-the 1-wire interface.
-
-Note that an example Python script is provided in the \textit{software/diag/} folder
-of the main project repository~\cite{ctb-repo}. Section~\ref{sec:repo-software}
-gives more details about the test scripts in the project repository.
-
-\begin{table}[h]
- \caption{Data from thermometer}
- \label{tbl:thermo-data}
- \centerline
- {
- \rowcolors{2}{white}{gray!25}
- \begin{tabular}{l l p{.7\textwidth}}
- \hline
- \multicolumn{1}{c}{\textbf{Data}} & \multicolumn{1}{c}{\textbf{Length}} &
- \multicolumn{1}{c}{\textbf{Description}} \\
- \hline
- ID & 48 bits & Unique ID, packed within 64 bits \\
- Temp. & 16 bits & Current temperature, multiple resolutions available \\
- \hline
- \end{tabular}
- }
-\end{table}
+The FPGA on-board the CONV-TTL-BLO makes available the temperature and the unique ID values available in
+3 registers accessible via I2C (See Appendix~\ref{app:memmap}).
%------------------------------------------------------------------------------
% SUBSEC: RTM lines and on-board switches
@@ -1048,7 +1063,7 @@ gives more details about the test scripts in the project repository.
\label{sec:diag-sw-rtmdet}
The state of the on-board switches and that of the RTM detection lines can
-also be read from the SR (see Appendix~\ref{app:conv-regs-sr}).
+also be read from the SR (see Appendix~\ref{app:conv-regs-SR}).
In the case of the switches, the raw state of the FPGA inputs is reflected on
the SR bits (Figure~\ref{fig:sr-switches}). Since an ON switch pulls the line to GND, a '0' value on one
@@ -1086,12 +1101,12 @@ state in the SR will be a logic '0'.
\vspace*{11pt}
-One channel is allocated on the input of each counter, after the OR gate preceding
+Each channel is assigned two counters after the OR gate preceding
the pulse generator. The input counter logic, which is repeated on each channel,
is shown in Figure~\ref{fig:pulse-cnt}. On a rising edge of a pulse from either a
-TTL or a blocking input, the pulse counter is incremented and stored to the channel's
-pulse counter register (CHxPCR -- see Appendix~\ref{app:conv-regs}). The CHxPCR is a
-read-write register that can be written at any time via I$^2$C with a user-defined value.
+TTL or a blocking input, the corresponding pulse counter is incremented and stored to one of the
+two channel pulse counter registers (CHxTTLPCR or CHxBLOPCR -- see Appendix~\ref{app:conv-regs}). The CHxPCR
+is a read-write register that can be written at any time via I$^2$C with a user-defined value.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
@@ -1249,7 +1264,7 @@ should be the last register read in a read sequence. Otherwise, the read pointer
and the contents of the TBMR will correspond to one sample in the ring buffer, while
the contents of the TBCYR and TBH/LR will be that of another sample.
-The TBCSR (see Appendix~\ref{app:conv-regs-tbcsr}) contains bits that allow to check the
+The TBCSR (see Appendix~\ref{app:conv-regs-TBCSR}) contains bits that allow to check the
status and clear the buffer. The USEDW field in this register contains the current number
of samples written to the buffer. When the buffer is full, the USEDW field is 0 and the
FULL bit is set. Setting the CLR bit of the TBCSR will bring the read and write pointers
@@ -1265,7 +1280,7 @@ can be useful when other channels fill up the ring buffer before a relevant time
is read.
The memory map contains further details about the contents of each register
-(see Appendix~\ref{app:conv-regs-ch1ltscyr} through~\ref{app:conv-regs-ch6ltsthr}).
+(see Appendix~\ref{app:conv-regs-CH1LTSCYR} through~\ref{app:conv-regs-CH6LTSCYR}).
%------------------------------------------------------------------------------
% SUBSEC: Remote reset
@@ -1274,7 +1289,7 @@ The memory map contains further details about the contents of each register
\label{sec:diag-remote-reset}
The user can remotely reset the FPGA logic inside the CONV-TTL-BLO by writing to
-the board's control register at address \textbf{0x008} (see Appendix~\ref{app:conv-regs-cr})
+the board's control register at address \textbf{0x008} (see Appendix~\ref{app:conv-regs-CR})
to first unlock the RST bit and then write it high to initiate the reset. When the
reset is initiated, a 100~ms reset pulse is applied to the logic.
@@ -1350,7 +1365,7 @@ triggering is password-protected.
\end{table}
In order to manually trigger a pulse, the user should write five bytes to the board's control
-register at address \textbf{0x008} (CR -- see Appendix~\ref{app:conv-regs-cr}), as shown in
+register at address \textbf{0x008} (CR -- see Appendix~\ref{app:conv-regs-CR}), as shown in
Table~\ref{tbl:man-trig}. The MPT field is dual-purpose, as shown in
Figure~\ref{fig:cr-mpt}. Until the magic sequence is input, it should be written with the
bytes in the magic sequence. After that, it should be written with the channel number.
@@ -1405,10 +1420,11 @@ set when the error occurs, are shown in Table~\ref{tbl:syserr}.
Fallback to golden bitstream & SR.GWVERS & Error when booting from application bitstream,
fallback to golden bitstream occured
(see Section~\ref{sec:reprog-bitstreams}) \\
- I$^2$C timeout & SR.I2C\_WDTO & An I$^2$C transfer is not completed
+ I$^2$C timeout & ERR.I2C\_WDTO & An I$^2$C transfer is not completed
within 24~ms (see Section~\ref{sec:comm-timeout}) \\
- I$^2$C error & SR.I2C\_ERR & Attempted to access a non-memory-mapped address via I$^2$C \\
- Missed pulse & SR.PMISSE & Input pulse rejected (see Figure~\ref{fig:pg-op}) \\
+ I$^2$C error & ERR.I2C\_ERR & Attempted to access a non-memory-mapped address via I$^2$C \\
+ FLIM missed pulse& ERR.FLIM\_PMISSE & Input pulse rejected because the pulse frequency is higher than the maximum of Table~\ref{tbl:freq-table} (Error set by the PG block in Fig.~\ref{fig:pulse-rep}) \\
+ FWDG missed pulse& ERR.FWDG\_PMISSE & Input pulse rejected because the board cannot sustain the input frequency beyond times in Fig.~\ref{fig:BC-freq-lim} (Error set by the BC block in Fig.~\ref{fig:pulse-rep}) \\
\hline
\end{tabular}
}
@@ -1560,7 +1576,7 @@ if a new application bitstream is correctly loaded to the CONV-TTL-BLO flash chi
a power-cycle will be needed to run this new bitstream.
To detect which bitstream is currently running, read the GWVERS field in the
-board's status register (SR -- see Appendix~\ref{app:conv-regs-sr}).
+board's status register (SR -- see Appendix~\ref{app:conv-regs-SR}).
%--------------------------------------------------------------------------------------
@@ -1668,8 +1684,9 @@ The folder structure of the repository is presented in Table~\ref{tbl:fold-struc
\multicolumn{1}{c}{\textbf{Folder}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{conv-ttl-blo-gw/} & \textit{git} subproject for the FPGA gateware \\
+ \textit{conv-ttl-blo-hw/} & Source files for the latest version of the CONV-TTL-BLO \\
+ \textit{conv-ttl-blo-tst/} & Source files the Production Test Suite (PTS) \\
\textit{doc/} & CONV-TTL-BLO board documentation, including this user guide \\
- \textit{pcb/} & Source files for the latest version of the CONV-TTL-BLO
printed circuit boards \\
\textit{software/} & Tools that can be used to communicate to the CONV-TTL-BLO
and perform various functionality \\
@@ -1723,6 +1740,16 @@ CONV-TTL-BLO~\cite{ctb-gw-releases}.
\item TTL pulses -- set the switch to the \textbf{ON} position (default)
\item TTL-BAR pulses -- set the switch to the \textbf{OFF} position
\end{itemize}
+
+ \item \label{enum:pwidth-select-switch}
+ \textit{If the board is v3 and earlier, this step is not applicable and may be skipped.}\\
+ Based on the desired pulse width desired at the output, and also based on the desired repetition frequencies, set the pulse-width selection switch
+ (SW1.2, see Section~\ref{sec:pulse-rep-freq}) to the appropriate position:
+ \begin{itemize}
+ \item Short $250 ns$ -- set the switch to the \textbf{ON} position
+ \item Long $1.2\mu s$ -- set the switch to the \textbf{OFF} position (default)
+ \end{itemize}
+
\item Set the glitch filter enable switch (SW1.1, see Section~\ref{sec:pulse-jit}) to
the appropriate position:
\begin{itemize}
@@ -1829,7 +1856,6 @@ $reg. index = \frac{addr}{4} + 1$
\hline
Board registers & 0x000 & 0x0ff & Converter board registers \\
MultiBoot & 0x100 & 0x01f & MultiBoot module \\
- Thermometer & 0x200 & 0x2ff & Thermometer chip \\
SDB descriptor & 0xf00 & 0xfff & SDB descriptor table (see~\cite{sdb}) \\
\hline
\end{tabular}
@@ -1839,7 +1865,7 @@ $reg. index = \frac{addr}{4} + 1$
%%------------------------------------------------------------------------------
%% SUBSEC: conv_regs
%%------------------------------------------------------------------------------
-\include{conv-regs}
+\include{conv_regs}
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
@@ -1849,34 +1875,34 @@ $reg. index = \frac{addr}{4} + 1$
%------------------------------------------------------------------------------
% SUBSEC: Thermo
%------------------------------------------------------------------------------
-\subsection{Thermometer module}
-\label{app:memmap-thermo}
-
-\indent Base address: 0x200
-
-\vspace*{11pt}
-
-\centerline
-{
- \rowcolors{2}{white}{gray!25}
- \begin{tabular}{l l l p{.5\textwidth}}
- \hline
- \textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
- \hline
- 0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
- 0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
- \hline
- \end{tabular}
-}
-
-\vspace*{11pt}
-
-For details on the bits of the thermometer module access registers, see the
-OneWire Master module's documentation~\cite{onewire-core}.
-
-Note that the OWCDR should be set accordingly for proper functioning of the
-one-wire timings. The value for the current version of the gateware is
-\verb-OWCDR = 0x00130063-.
+%\subsection{Thermometer module}
+%\label{app:memmap-thermo}
+%
+%\indent Base address: 0x200
+%
+%\vspace*{11pt}
+%
+%\centerline
+%{
+ %\rowcolors{2}{white}{gray!25}
+ %\begin{tabular}{l l l p{.5\textwidth}}
+ %\hline
+ %\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
+ %\hline
+ %0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
+ %0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
+ %\hline
+ %\end{tabular}
+%}
+%
+%\vspace*{11pt}
+%
+%For details on the bits of the thermometer module access registers, see the
+%OneWire Master module's documentation~\cite{onewire-core}.
+%
+%Note that the OWCDR should be set accordingly for proper functioning of the
+%one-wire timings. The value for the current version of the gateware is
+%\verb-OWCDR = 0x00130063-.
%------------------------------------------------------------------------------