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C
Conv TTL Blocking - Testing
Commit 94d1363d authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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fm/doc/hdlg/cern-title.tex
View file @ 94d1363d
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill December 11, 2014
\hfill October 26, 2017
\vspace*{3cm}
......@@ -24,7 +24,7 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent {\Large \textbf{CERN/BE-CO-HT}}
\noindent \rule{\textwidth}{.05cm}
......
fm/doc/hdlg/hdlg-pts-conv-ttl-blo.tex
View file @ 94d1363d
......@@ -73,6 +73,7 @@ work, see \\
11-12-2014 & 1.0 & Updated document according to converter board documentation template, added licensing
information, updated information according to changes in HDL, added memory map
as appendix, removed redundant information \\
26-10-2017 & 1.1 & Added Test hwvertest and updated wishbone regsiter maps\\
\hline
\end{tabular}
}
......@@ -183,6 +184,21 @@ for the gateware in Appendix~\ref{app:memmap}.
\section{Test logic}
\label{sec:test-logic}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 00
%--------------------------------------------------------------------------------------
\subsection{Test 00 -- PCB version test}
The PTS software verifies whether the version of the PCB is the one expected to
be tested with this PTS. Each PTS is prepared for a particular version of PCB
and it cannot be used to test other version of hardware.
The test reads the PCB version provided in an HWVERS register (see Annex~\ref{app:pts-regs-csr}).
If the provided version is different than the expected version, no further tests is
run and PTS is stopped.
\textbf{This test is required to pass for the PTS to run the remaining tests.}
%--------------------------------------------------------------------------------------
% SUBSEC: Test 01
%--------------------------------------------------------------------------------------
......
fm/doc/hdlg/pts_regs.tex
View file @ 94d1363d
\subsection{PTS control and status registers}
\label{app:pts-regs}
\label{app:pts-regs-csr}
Base address: 0x000
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{gray}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & BIDR & pts\_bidr & BIDR\\
0x4& REG & CSR & pts\_csr & CSR\\
0x8& REG & LSR & pts\_lsr & LSR\\
\hline
\endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & (1) & CSR & Control and Status Register\\
0x8 & (2) & LSR & Line Status Register\\
\end{longtable}
\end{tabular}
}
\noindent Note (1): The reset value of the status bits in the CSR cannot be specified, since it is based on the
the state of the on-board switches and whether an RTM is plugged in or not. Control bits in the CSR default to 0.
\subsubsection{Register description}
\paragraph*{BIDR}\vspace{12pt}
\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
is plugged into the channel or not.
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_bidr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & BIDR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\subsubsection{BIDR -- Board ID Register}
\label{app:pts-regs-bidr}
\vspace{12pt}
Board ID Register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -58,18 +57,22 @@ is plugged into the channel or not.
{\bf
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424c4f
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\paragraph*{CSR}\vspace{12pt}
\subsubsection{CSR -- Control and Status Register}
\label{app:pts-regs-csr}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_csr\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & CSR\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
Control and Status Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -83,7 +86,7 @@ Reset value: 0x54424c4f
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK} & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK} & \multicolumn{6}{|c|}{\cellcolor{gray!25}HWVERS[5:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
......@@ -130,6 +133,13 @@ REARPT
\end{small}
\item \begin{small}
{\bf
HWVERS
} [\emph{read-only}]: PCB version number
\\
6 bits representing HW/PCB version number \\ 4 MSB represent HW version number \\ 2 LSB represent number of execution \\ Eg: value 010010 represents PCB version 4.2
\end{small}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
......@@ -170,15 +180,21 @@ I2C\_WDTO
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{LSR -- Line Status Register}
\label{app:pts-regs-lsr}
\paragraph*{LSR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_lsr\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & LSR\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
Line Status Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -223,9 +239,6 @@ REAR
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
......
fm/doc/hdlg/pulse_cnt_wb.tex
View file @ 94d1363d
\subsection{Pulse counter registers}
\label{app:pulse-cnt}
Base address: 0xc00
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.35\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endhead
\hline
\endfoot
0x00 & 0x00000000 & TTLCH1OCR & TTL CH1 output counter register\\
0x04 & 0x00000000 & TTLCH1ICR & TTL CH1 input counter register\\
0x08 & 0x00000000 & TTLCH2OCR & TTL CH2 output counter register\\
0x0c & 0x00000000 & TTLCH2ICR & TTL CH2 input counter register\\
0x10 & 0x00000000 & TTLCH3OCR & TTL CH3 output counter register\\
0x14 & 0x00000000 & TTLCH3ICR & TTL CH3 input counter register\\
0x18 & 0x00000000 & TTLCH4OCR & TTL CH4 output counter register\\
0x1c & 0x00000000 & TTLCH4ICR & TTL CH4 input counter register\\
0x20 & 0x00000000 & TTLCH5OCR & TTL CH5 output counter register\\
0x24 & 0x00000000 & TTLCH5ICR & TTL CH5 input counter register\\
0x28 & 0x00000000 & TTLCH6OCR & TTL CH6 output counter register\\
0x2c & 0x00000000 & TTLCH6ICR & TTL CH6 input counter register\\
0x30 & 0x00000000 & INVTTLCHAOCR & INV-TTL CHA output counter register\\
0x34 & 0x00000000 & INVTTLCHAICR & INV-TTL CHA input counter register\\
0x38 & 0x00000000 & INVTTLCHBOCR & INV-TTL CHB output counter register\\
0x3c & 0x00000000 & INVTTLCHBICR & INV-TTL CHB input counter register\\
0x40 & 0x00000000 & INVTTLCHCOCR & INV-TTL CHC output counter register\\
0x44 & 0x00000000 & INVTTLCHCICR & INV-TTL CHC input counter register\\
0x48 & 0x00000000 & INVTTLCHDOCR & INV-TTL CHD output counter register\\
0x4c & 0x00000000 & INVTTLCHDICR & INV-TTL CHD input counter register\\
0x50 & 0x00000000 & REARCH1OCR & Rear CH1 output counter register\\
0x54 & 0x00000000 & REARCH1ICR & Rear CH1 input counter register\\
0x58 & 0x00000000 & REARCH2OCR & Rear CH2 output counter register\\
0x5c & 0x00000000 & REARCH2ICR & Rear CH2 input counter register\\
0x60 & 0x00000000 & REARCH3OCR & Rear CH3 output counter register\\
0x64 & 0x00000000 & REARCH3ICR & Rear CH3 input counter register\\
0x68 & 0x00000000 & REARCH4OCR & Rear CH4 output counter register\\
0x6c & 0x00000000 & REARCH4ICR & Rear CH4 input counter register\\
0x70 & 0x00000000 & REARCH5OCR & Rear CH5 output counter register\\
0x74 & 0x00000000 & REARCH5ICR & Rear CH5 input counter register\\
0x78 & 0x00000000 & REARCH6OCR & Rear CH6 output counter register\\
0x7c & 0x00000000 & REARCH6ICR & Rear CH6 input counter register\\
\end{longtable}
Registers containing the values for input and output generated pulses
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{gray}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & TTLCH1OCR & pulse\_cnt\_ttlch1o & TTLCH1O\\
0x4& REG & TTLCH1ICR & pulse\_cnt\_ttlch1i & TTLCH1I\\
0x8& REG & TTLCH2OCR & pulse\_cnt\_ttlch2o & TTLCH2O\\
0xc& REG & TTLCH2ICR & pulse\_cnt\_ttlch2i & TTLCH2I\\
0x10& REG & TTLCH3OCR & pulse\_cnt\_ttlch3o & TTLCH3O\\
0x14& REG & TTLCH3ICR & pulse\_cnt\_ttlch3i & TTLCH3I\\
0x18& REG & TTLCH4OCR & pulse\_cnt\_ttlch4o & TTLCH4O\\
0x1c& REG & TTLCH4ICR & pulse\_cnt\_ttlch4i & TTLCH4I\\
0x20& REG & TTLCH5OCR & pulse\_cnt\_ttlch5o & TTLCH5O\\
0x24& REG & TTLCH5ICR & pulse\_cnt\_ttlch5i & TTLCH5I\\
0x28& REG & TTLCH6OCR & pulse\_cnt\_ttlch6o & TTLCH6O\\
0x2c& REG & TTLCH6ICR & pulse\_cnt\_ttlch6i & TTLCH6I\\
0x30& REG & INVTTLCHAOCR & pulse\_cnt\_invttlchao & INVTTLCHAO\\
0x34& REG & INVTTLCHAICR & pulse\_cnt\_invttlchai & INVTTLCHAI\\
0x38& REG & INVTTLCHBOCR & pulse\_cnt\_invttlchbo & INVTTLCHBO\\
0x3c& REG & INVTTLCHBICR & pulse\_cnt\_invttlchbi & INVTTLCHBI\\
0x40& REG & INVTTLCHCOCR & pulse\_cnt\_invttlchco & INVTTLCHCO\\
0x44& REG & INVTTLCHCICR & pulse\_cnt\_invttlchci & INVTTLCHCI\\
0x48& REG & INVTTLCHDOCR & pulse\_cnt\_invttlchdo & INVTTLCHDO\\
0x4c& REG & INVTTLCHDICR & pulse\_cnt\_invttlchdi & INVTTLCHDI\\
0x50& REG & REARCH1OCR & pulse\_cnt\_rearch1o & REARCH1O\\
0x54& REG & REARCH1ICR & pulse\_cnt\_rearch1i & REARCH1I\\
0x58& REG & REARCH2OCR & pulse\_cnt\_rearch2o & REARCH2O\\
0x5c& REG & REARCH2ICR & pulse\_cnt\_rearch2i & REARCH2I\\
0x60& REG & REARCH3OCR & pulse\_cnt\_rearch3o & REARCH3O\\
0x64& REG & REARCH3ICR & pulse\_cnt\_rearch3i & REARCH3I\\
0x68& REG & REARCH4OCR & pulse\_cnt\_rearch4o & REARCH4O\\
0x6c& REG & REARCH4ICR & pulse\_cnt\_rearch4i & REARCH4I\\
0x70& REG & REARCH5OCR & pulse\_cnt\_rearch5o & REARCH5O\\
0x74& REG & REARCH5ICR & pulse\_cnt\_rearch5i & REARCH5I\\
0x78& REG & REARCH6OCR & pulse\_cnt\_rearch6o & REARCH6O\\
0x7c& REG & REARCH6ICR & pulse\_cnt\_rearch6i & REARCH6I\\
\hline
\end{tabular}
}
\vspace{11pt}
\subsubsection{TTLCH1OCR -- TTL CH1 output counter register}
\subsubsection{Register description}
\paragraph*{TTLCH1OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch1o\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & TTLCH1O\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
TTL CH1 output counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -83,14 +87,21 @@ Base address: 0xc00
TTLCH1O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH1ICR -- TTL CH1 input counter register}
\paragraph*{TTLCH1ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch1i\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & TTLCH1I\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
TTL CH1 input counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -119,14 +130,21 @@ TTLCH1O
TTLCH1I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH2OCR -- TTL CH2 output counter register}
\paragraph*{TTLCH2OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch2o\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & TTLCH2O\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
TTL CH2 output counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -155,14 +173,21 @@ TTLCH1I
TTLCH2O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH2ICR -- TTL CH2 input counter register}
\paragraph*{TTLCH2ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch2i\\
{\bf HW address:} & 0x3\\
{\bf SW prefix:} & TTLCH2I\\
{\bf SW offset:} & 0xc\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
TTL CH2 input counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -191,14 +216,21 @@ TTLCH2O
TTLCH2I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH3OCR -- TTL CH3 output counter register}
\paragraph*{TTLCH3OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch3o\\
{\bf HW address:} & 0x4\\
{\bf SW prefix:} & TTLCH3O\\
{\bf SW offset:} & 0x10\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
TTL CH3 output counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -227,14 +259,21 @@ TTLCH2I
TTLCH3O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH3ICR -- TTL CH3 input counter register}
\paragraph*{TTLCH3ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch3i\\
{\bf HW address:} & 0x5\\
{\bf SW prefix:} & TTLCH3I\\
{\bf SW offset:} & 0x14\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
TTL CH3 input counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -263,14 +302,21 @@ TTLCH3O
TTLCH3I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH4OCR -- TTL CH4 output counter register}
\paragraph*{TTLCH4OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch4o\\
{\bf HW address:} & 0x6\\
{\bf SW prefix:} & TTLCH4O\\
{\bf SW offset:} & 0x18\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
TTL CH4 output counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -299,14 +345,21 @@ TTLCH3I
TTLCH4O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH4ICR -- TTL CH4 input counter register}
\paragraph*{TTLCH4ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch4i\\
{\bf HW address:} & 0x7\\
{\bf SW prefix:} & TTLCH4I\\
{\bf SW offset:} & 0x1c\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
TTL CH4 input counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -335,14 +388,21 @@ TTLCH4O
TTLCH4I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH5OCR -- TTL CH5 output counter register}
\paragraph*{TTLCH5OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch5o\\
{\bf HW address:} & 0x8\\
{\bf SW prefix:} & TTLCH5O\\
{\bf SW offset:} & 0x20\\
\end{tabular}
\vspace{12pt}
TTL CH5 output counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -371,14 +431,21 @@ TTLCH4I
TTLCH5O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH5ICR -- TTL CH5 input counter register}
\paragraph*{TTLCH5ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch5i\\
{\bf HW address:} & 0x9\\
{\bf SW prefix:} & TTLCH5I\\
{\bf SW offset:} & 0x24\\
\end{tabular}
\vspace{12pt}
TTL CH5 input counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -407,14 +474,21 @@ TTLCH5O
TTLCH5I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH6OCR -- TTL CH6 output counter register}
\paragraph*{TTLCH6OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch6o\\
{\bf HW address:} & 0xa\\
{\bf SW prefix:} & TTLCH6O\\
{\bf SW offset:} & 0x28\\
\end{tabular}
\vspace{12pt}
TTL CH6 output counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -443,14 +517,21 @@ TTLCH5I
TTLCH6O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TTLCH6ICR -- TTL CH6 input counter register}
\paragraph*{TTLCH6ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_ttlch6i\\
{\bf HW address:} & 0xb\\
{\bf SW prefix:} & TTLCH6I\\
{\bf SW offset:} & 0x2c\\
\end{tabular}
\vspace{12pt}
TTL CH6 input counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -479,14 +560,21 @@ TTLCH6O
TTLCH6I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{INVTTLCHAOCR -- INV-TTL CHA output counter register}
\paragraph*{INVTTLCHAOCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_invttlchao\\
{\bf HW address:} & 0xc\\
{\bf SW prefix:} & INVTTLCHAO\\
{\bf SW offset:} & 0x30\\
\end{tabular}
\vspace{12pt}
INV-TTL CHA output counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -515,14 +603,21 @@ TTLCH6I
INVTTLCHAO
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{INVTTLCHAICR -- INV-TTL CHA input counter register}
\paragraph*{INVTTLCHAICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_invttlchai\\
{\bf HW address:} & 0xd\\
{\bf SW prefix:} & INVTTLCHAI\\
{\bf SW offset:} & 0x34\\
\end{tabular}
\vspace{12pt}
INV-TTL CHA input counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -551,14 +646,21 @@ INVTTLCHAO
INVTTLCHAI
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{INVTTLCHBOCR -- INV-TTL CHB output counter register}
\paragraph*{INVTTLCHBOCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_invttlchbo\\
{\bf HW address:} & 0xe\\
{\bf SW prefix:} & INVTTLCHBO\\
{\bf SW offset:} & 0x38\\
\end{tabular}
\vspace{12pt}
INV-TTL CHB output counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -587,14 +689,21 @@ INVTTLCHAI
INVTTLCHBO
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{INVTTLCHBICR -- INV-TTL CHB input counter register}
\paragraph*{INVTTLCHBICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_invttlchbi\\
{\bf HW address:} & 0xf\\
{\bf SW prefix:} & INVTTLCHBI\\
{\bf SW offset:} & 0x3c\\
\end{tabular}
\vspace{12pt}
INV-TTL CHB input counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -623,14 +732,21 @@ INVTTLCHBO
INVTTLCHBI
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{INVTTLCHCOCR -- INV-TTL CHC output counter register}
\paragraph*{INVTTLCHCOCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_invttlchco\\
{\bf HW address:} & 0x10\\
{\bf SW prefix:} & INVTTLCHCO\\
{\bf SW offset:} & 0x40\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
INV-TTL CHC output counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -659,14 +775,21 @@ INVTTLCHBI
INVTTLCHCO
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{INVTTLCHCICR -- INV-TTL CHC input counter register}
\paragraph*{INVTTLCHCICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_invttlchci\\
{\bf HW address:} & 0x11\\
{\bf SW prefix:} & INVTTLCHCI\\
{\bf SW offset:} & 0x44\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
INV-TTL CHC input counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -695,14 +818,21 @@ INVTTLCHCO
INVTTLCHCI
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{INVTTLCHDOCR -- INV-TTL CHD output counter register}
\paragraph*{INVTTLCHDOCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_invttlchdo\\
{\bf HW address:} & 0x12\\
{\bf SW prefix:} & INVTTLCHDO\\
{\bf SW offset:} & 0x48\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
INV-TTL CHD output counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -731,14 +861,21 @@ INVTTLCHCI
INVTTLCHDO
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{INVTTLCHDICR -- INV-TTL CHD input counter register}
\paragraph*{INVTTLCHDICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_invttlchdi\\
{\bf HW address:} & 0x13\\
{\bf SW prefix:} & INVTTLCHDI\\
{\bf SW offset:} & 0x4c\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
INV-TTL CHD input counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -767,14 +904,21 @@ INVTTLCHDO
INVTTLCHDI
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH1OCR -- Rear CH1 output counter register}
\paragraph*{REARCH1OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch1o\\
{\bf HW address:} & 0x14\\
{\bf SW prefix:} & REARCH1O\\
{\bf SW offset:} & 0x50\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
Rear CH1 output counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -803,14 +947,21 @@ INVTTLCHDI
REARCH1O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH1ICR -- Rear CH1 input counter register}
\paragraph*{REARCH1ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch1i\\
{\bf HW address:} & 0x15\\
{\bf SW prefix:} & REARCH1I\\
{\bf SW offset:} & 0x54\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
Rear CH1 input counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -839,14 +990,21 @@ REARCH1O
REARCH1I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH2OCR -- Rear CH2 output counter register}
\paragraph*{REARCH2OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch2o\\
{\bf HW address:} & 0x16\\
{\bf SW prefix:} & REARCH2O\\
{\bf SW offset:} & 0x58\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
Rear CH2 output counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -875,14 +1033,21 @@ REARCH1I
REARCH2O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH2ICR -- Rear CH2 input counter register}
\paragraph*{REARCH2ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch2i\\
{\bf HW address:} & 0x17\\
{\bf SW prefix:} & REARCH2I\\
{\bf SW offset:} & 0x5c\\
\end{tabular}
\vspace{11pt}
\vspace{12pt}
Rear CH2 input counter register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -911,14 +1076,21 @@ REARCH2O
REARCH2I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH3OCR -- Rear CH3 output counter register}
\paragraph*{REARCH3OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch3o\\
{\bf HW address:} & 0x18\\
{\bf SW prefix:} & REARCH3O\\
{\bf SW offset:} & 0x60\\
\end{tabular}
\vspace{12pt}
Rear CH3 output counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -947,14 +1119,21 @@ REARCH2I
REARCH3O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH3ICR -- Rear CH3 input counter register}
\paragraph*{REARCH3ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch3i\\
{\bf HW address:} & 0x19\\
{\bf SW prefix:} & REARCH3I\\
{\bf SW offset:} & 0x64\\
\end{tabular}
\vspace{12pt}
Rear CH3 input counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -983,14 +1162,21 @@ REARCH3O
REARCH3I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH4OCR -- Rear CH4 output counter register}
\paragraph*{REARCH4OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch4o\\
{\bf HW address:} & 0x1a\\
{\bf SW prefix:} & REARCH4O\\
{\bf SW offset:} & 0x68\\
\end{tabular}
\vspace{12pt}
Rear CH4 output counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -1019,14 +1205,21 @@ REARCH3I
REARCH4O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH4ICR -- Rear CH4 input counter register}
\paragraph*{REARCH4ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch4i\\
{\bf HW address:} & 0x1b\\
{\bf SW prefix:} & REARCH4I\\
{\bf SW offset:} & 0x6c\\
\end{tabular}
\vspace{12pt}
Rear CH4 input counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -1055,14 +1248,21 @@ REARCH4O
REARCH4I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH5OCR -- Rear CH5 output counter register}
\paragraph*{REARCH5OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch5o\\
{\bf HW address:} & 0x1c\\
{\bf SW prefix:} & REARCH5O\\
{\bf SW offset:} & 0x70\\
\end{tabular}
\vspace{12pt}
Rear CH5 output counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -1091,14 +1291,21 @@ REARCH4I
REARCH5O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH5ICR -- Rear CH5 input counter register}
\paragraph*{REARCH5ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch5i\\
{\bf HW address:} & 0x1d\\
{\bf SW prefix:} & REARCH5I\\
{\bf SW offset:} & 0x74\\
\end{tabular}
\vspace{12pt}
Rear CH5 input counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -1127,14 +1334,21 @@ REARCH5O
REARCH5I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH6OCR -- Rear CH6 output counter register}
\paragraph*{REARCH6OCR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch6o\\
{\bf HW address:} & 0x1e\\
{\bf SW prefix:} & REARCH6O\\
{\bf SW offset:} & 0x78\\
\end{tabular}
\vspace{12pt}
Rear CH6 output counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -1163,14 +1377,21 @@ REARCH5I
REARCH6O
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{REARCH6ICR -- Rear CH6 input counter register}
\paragraph*{REARCH6ICR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pulse\_cnt\_rearch6i\\
{\bf HW address:} & 0x1f\\
{\bf SW prefix:} & REARCH6I\\
{\bf SW offset:} & 0x7c\\
\end{tabular}
\vspace{12pt}
Rear CH6 input counter register
\vspace{11pt}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -1199,9 +1420,6 @@ REARCH6O
REARCH6I
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
......
fm/doc/setup/cern-title.tex
View file @ 94d1363d
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill January 15, 2015
\hfill July 13, 2018
\vspace*{3cm}
......@@ -24,7 +24,7 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent {\Large \textbf{CERN/BE-CO-HT}}
\noindent \rule{\textwidth}{.05cm}
......
fm/doc/setup/setup.tex
View file @ 94d1363d
......@@ -119,7 +119,7 @@ focuses on installing the test system (scripts, preparing shortcuts, etc.) on th
\label{sec:rack}
To setup the rack for the PTS system, we will need to insert an RTM Interface Tester
card to the back side of the ELMA crate placed inside the 19'' rack. You will need
card into the back of the ELMA crate placed inside the 19'' rack. You will need
an RTM Interface Tester card to set up the system, so this would be a good time to
obtain one.
......@@ -151,6 +151,9 @@ system to gain remote access to the laptop, the installation of the system can a
on the laptop directly. However, the steps related to network drivers and configuration
should be followed in order to have a properly working PTS system.
Also note that the admin account should be named \verb=pts-administrator=. This account
name is important as it is embedded in the PTS scripts (Password \verb=pts-admin=).
The guide should be followed until \textbf{step 17} of section \textbf{Set up the PTS user account}.
After this step, the guide is SVEC-related and need not be followed. We will continue with
the details in the next section to test our system and network was properly installed.
......@@ -171,7 +174,8 @@ the details in the next section to test our system and network was properly inst
Escape character is '^]'.
login:admin
password: ADMIN
%>
%>
$
\end{verbatim}
\vspace{11pt}
\item Make sure the ELMA crate has gateware version 2.31 or higher on it. In the SysMon Telnet prompt:
......@@ -220,12 +224,12 @@ We will detail here the simplest of the two, downloading the ready-made archive.
See Appendix~\ref{app:build} for details on the second.
\begin{enumerate}
\item Log in to the \verb=pts= user on the laptop
\item Log in to the \verb=pts-administrator= user on the laptop
\item Open up a terminal window, download the PTS folder structure tarball from OHWR
to the home folder of the \verb=pts= user and extract the archive:
\begin{verbatim}
cd ~
wget http://www.ohwr.org/attachments/download/3777/ubuntu.tar.gz
wget https://www.ohwr.org/attachments/5822/ubuntu.tar.gz
tar xzvf ubuntu.tar.gz
\end{verbatim}
Note that you can also copy the archive from a USB stick instead of downloading it from OHWR.
......@@ -259,7 +263,7 @@ See Appendix~\ref{app:build} for details on the second.
\begin{verbatim}
chmod a+w *
\end{verbatim}
\item Now we that have the test scripts on the system we can create a dedicated
\item Now that we have the test scripts on the system we can create a dedicated
user that will be used to run the PTS for the CONV-TTL-BLO. Open up Ubuntu's
\textbf{User Accounts} window (click the \verb=pts= user account name at the top-right
side of the screen), unlock this window by providing the \verb=pts= user account's
......@@ -286,9 +290,9 @@ See Appendix~\ref{app:build} for details on the second.
\begin{verbatim}
cd ~
cp .bashrc .bashrc.old
cp /home/pts/ubuntu/ttlbl/config/bashrc.pts .bashrc
cp /home/pts-administrator/ubuntu/ttlbl/config/bashrc.pts .bashrc
cd ~/Desktop/
cp /home/pts/ubuntu/ttlbl/config/*.desktop .
cp /home/pts-administrator/ubuntu/ttlbl/config/*.desktop .
\end{verbatim}
\item Right-click on the terminal icon in the launcher bar at the left and click \textbf{Lock to Launcher}
\item Close the terminal window
......@@ -298,7 +302,7 @@ See Appendix~\ref{app:build} for details on the second.
\begin{itemize}
\item on the Desktop, right-click and select \textbf{Change Desktop Background}
\item hit the \textbf{+} under Wallpapers
\item navigate to \verb=/home/pts/ubuntu/ttlbl/config/=
\item navigate to \verb=/home/pts-administrator/ubuntu/ttlbl/config/=
\item select \verb=ttlbl-background.png= as the background image
\item make sure the scaling of the image is set to \textbf{Zoom}
\end{itemize}
......@@ -355,12 +359,16 @@ In order to build a test system from scratch, follow these steps:
git clone git://ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-tst.git
\end{verbatim}
\end{small}
\item Run \verb=make= in the \verb=pts-fm/= folder, setting the options as appropriate
\item Run \verb=make= in the \verb=fm/pts/= folder, setting the options as appropriate
in your case:
\begin{verbatim}
cd conv-ttl-blo-tst/fm/
cd conv-ttl-blo-tst/fm/pts
make # ... set options here ...
\end{verbatim}
\item Copy the entire \verb=./ubuntu= folder to the \verb=pts-administrator= home directory. Type:
\begin{verbatim}
cp -r ./ubuntu /home/pts-administrator/
\end{verbatim}
\end{enumerate}
This will generate an archive similar to that downloaded in Section~\ref{sec:environment},
......
fm/hdl/modules/pts_regs.html 0 → 100644
View file @ 94d1363d
<HTML>
<HEAD>
<TITLE>pts_regs</TITLE>
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</HEAD>
<BODY>
<h1 class="heading">pts_regs</h1>
<h3>PTS control and status registers</h3>
<p></p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">BIDR</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">CSR</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">LSR</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#BIDR">BIDR</a>
</td>
<td class="td_code">
pts_bidr
</td>
<td class="td_code">
BIDR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#CSR">CSR</a>
</td>
<td class="td_code">
pts_csr
</td>
<td class="td_code">
CSR
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#LSR">LSR</a>
</td>
<td class="td_code">
pts_lsr
</td>
<td class="td_code">
LSR
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>BIDR:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_bidr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[1:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>CSR:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_chledt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_stledt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rledt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_ttlpt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rearpt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_hwvers_i[5:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_unlock_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_unlock_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_unlock_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_switch_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rtm_i[5:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_err_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_err_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_err_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_wdto_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_wdto_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_wdto_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>LSR:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_lsr_front_i[5:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_lsr_frontinv_i[3:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_lsr_rear_i[5:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="BIDR"></a>
<h3><a name="sect_3_1">3.1. BIDR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
pts_bidr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
BIDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
Board ID Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BIDR[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BIDR[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BIDR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BIDR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
BIDR
</b>[<i>read-only</i>]: ID register bits
</ul>
<a name="CSR"></a>
<h3><a name="sect_3_2">3.2. CSR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
pts_csr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CSR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
Control and Status Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
I2C_WDTO
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
I2C_ERR
</td>
<td style="border: solid 1px black;" colspan=6 class="td_field">
RTM[5:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SWITCH[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RST
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RST_UNLOCK
</td>
<td style="border: solid 1px black;" colspan=6 class="td_field">
HWVERS[5:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
REARPT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TTLPT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RLEDT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
STLEDT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
CHLEDT
</td>
</tr>
</table>
<ul>
<li><b>
CHLEDT
</b>[<i>read/write</i>]: Channel pulse LED enable
<br>1 -- Enable channel LED sequencing <br> 0 -- No effect
<li><b>
STLEDT
</b>[<i>read/write</i>]: Status LED enable
<br>1 -- Enable front panel bicolor LED sequencing <br> 0 -- No effect
<li><b>
RLEDT
</b>[<i>read/write</i>]: Rear pulse LED line
<br>1 -- Set LED lines high <br> 0 -- No effect
<li><b>
TTLPT
</b>[<i>read/write</i>]: TTL test enable
<br>1 -- Enable pulse generation from CH1 <br> 0 -- No effect
<li><b>
REARPT
</b>[<i>read/write</i>]: Rear pulse enable
<br>1 -- Enable rear panel pulse generation <br> 0 -- No effect
<li><b>
HWVERS
</b>[<i>read-only</i>]: PCB version number
<br>6 bits representing HW/PCB version number <br> 4 MSB represent HW version number <br> 2 LSB represent number of execution <br> Eg: value 010010 represents PCB version 4.2
<li><b>
RST_UNLOCK
</b>[<i>read/write</i>]: Reset unlock bit
<br>1 -- Reset bit unlocked <br> 0 -- Reset bit locked
<li><b>
RST
</b>[<i>read/write</i>]: Reset bit -- active only if RST_UNLOCK is 1
<br>1 -- initiate logic reset <br> 0 -- no reset
<li><b>
SWITCH
</b>[<i>read-only</i>]: switches
<br>1 - switch is ON <br> 0 - switch is OFF
<li><b>
RTM
</b>[<i>read-only</i>]: RTM detection lines
<br>1 - line active <br> 0 - line inactive
<li><b>
I2C_ERR
</b>[<i>read/write</i>]: I2C communication error
<br>1 -- attempted to address non-existing address <br> 0 -- idle <br> This bit can be cleared by writing a '1' to it
<li><b>
I2C_WDTO
</b>[<i>read/write</i>]: I2C communication watchdog timeout error
<br>1 -- timeout occured <br> 0 -- no timeout <br> This bit can be cleared by writing a '1' to it
</ul>
<a name="LSR"></a>
<h3><a name="sect_3_3">3.3. LSR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
pts_lsr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
LSR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<p>
Line Status Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=6 class="td_field">
REAR[5:0]
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
FRONTINV[3:2]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=2 class="td_field">
FRONTINV[1:0]
</td>
<td style="border: solid 1px black;" colspan=6 class="td_field">
FRONT[5:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FRONT
</b>[<i>read-only</i>]: Front panel channel input state
<br>Line state at board input<br> Bit 0 -- channel 1<br> Bit 1 -- channel 2<br> etc.
<li><b>
FRONTINV
</b>[<i>read-only</i>]: Front panel INV-TTL input state
<br>Line state at board input<br> Bit 0 -- channel 1<br> Bit 1 -- channel 2<br> etc.
<li><b>
REAR
</b>[<i>read-only</i>]: Rear panel input state
<br>Line state at board input<br> Bit 0 -- channel 1<br> Bit 1 -- channel 2<br> etc.
</ul>
</BODY>
</HTML>
fm/hdl/modules/pts_regs.tex 0 → 100644
View file @ 94d1363d
\subsection{PTS control and status registers}
\label{subsec:wbgen:pts}
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & BIDR & pts\_bidr & BIDR\\
0x4& REG & CSR & pts\_csr & CSR\\
0x8& REG & LSR & pts\_lsr & LSR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{BIDR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_bidr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & BIDR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{12pt}
Board ID Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BIDR
} [\emph{read-only}]: ID register bits
\end{small}
\end{itemize}
\paragraph*{CSR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_csr\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & CSR\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{12pt}
Control and Status Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_WDTO} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_ERR} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}RTM[5:0]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SWITCH[7:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST\_UNLOCK} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}HWVERS[5:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}REARPT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}TTLPT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RLEDT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}STLEDT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}CHLEDT}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CHLEDT
} [\emph{read/write}]: Channel pulse LED enable
\\
1 -- Enable channel LED sequencing \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
STLEDT
} [\emph{read/write}]: Status LED enable
\\
1 -- Enable front panel bicolor LED sequencing \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
RLEDT
} [\emph{read/write}]: Rear pulse LED line
\\
1 -- Set LED lines high \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
TTLPT
} [\emph{read/write}]: TTL test enable
\\
1 -- Enable pulse generation from CH1 \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
REARPT
} [\emph{read/write}]: Rear pulse enable
\\
1 -- Enable rear panel pulse generation \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
HWVERS
} [\emph{read-only}]: PCB version number
\\
6 bits representing HW/PCB version number \\ 4 MSB represent HW version number \\ 2 LSB represent number of execution \\ Eg: value 010010 represents PCB version 4.2
\end{small}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 -- Reset bit unlocked \\ 0 -- Reset bit locked
\end{small}
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit -- active only if RST_UNLOCK is 1
\\
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
\item \begin{small}
{\bf
SWITCH
} [\emph{read-only}]: switches
\\
1 - switch is ON \\ 0 - switch is OFF
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM detection lines
\\
1 - line active \\ 0 - line inactive
\end{small}
\item \begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\end{itemize}
\paragraph*{LSR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_lsr\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & LSR\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{12pt}
Line Status Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[3:2]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}FRONT[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FRONT
} [\emph{read-only}]: Front panel channel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTINV
} [\emph{read-only}]: Front panel INV-TTL input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REAR
} [\emph{read-only}]: Rear panel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\end{itemize}
fm/hdl/modules/pts_regs.vhd
View file @ 94d1363d
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : .\pts_regs.vhd
-- Author : auto-generated by wbgen2 from .\pts_regs.wb
-- Created : 06/19/17 17:23:25
-- Created : 10/27/17 10:49:32
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\pts_regs.wb
......
fm/hdl/syn/pts.xise
View file @ 94d1363d
......@@ -49,7 +49,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
......
fm/hdl/top/pts.vhd
View file @ 94d1363d
......@@ -154,10 +154,9 @@ entity pts is
-- Switches
sw_gp_n_i : in std_logic_vector(7 downto 0);
sw_multicast_n_i : in std_logic_vector(3 downto 0);
-- PCB version recognition
pcbrev_i : in std_logic_vector(5 downto 0);
pcbrev_i : in std_logic_vector(5 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
......@@ -1900,9 +1899,11 @@ end generate gen_rear_test_logic;
end if;
end if;
end process p_led_seq;
max_led_seq <= to_unsigned(30,5) when pulse_led_en = '1' else to_unsigned(24,5); -- cycle 24 times for status leds
-- 30 times for pulse leds
-- cycle 24 times for status leds
-- 30 times for pulse leds
max_led_seq <= to_unsigned(30,5) when pulse_led_en = '1' else to_unsigned(24,5);
-- Sequence the front-panel LEDs based on the sequence counter
front_led_seq <= "0000000001" when (pulse_led_en = '1') and (led_seq = 1) else
"0000000010" when (pulse_led_en = '1') and (led_seq = 2) else
......
fm/pts/Makefile
View file @ 94d1363d
......@@ -20,6 +20,7 @@ all:
cp ubuntu/$(BOARD)/pyts/pts.py ubuntu/$(BOARD)/pts
cp ubuntu/$(BOARD)/pyts/jpts.py ubuntu/$(BOARD)/jpts
cp ubuntu/$(BOARD)/pyts/one.py ubuntu/$(BOARD)/one
ln -s pyts/hwvertest.py ubuntu/$(BOARD)/hwvertest.py
ln -s pyts/dac_vcxo_pll.py ubuntu/$(BOARD)/test01.py
ln -s pyts/leds.py ubuntu/$(BOARD)/test02.py
ln -s pyts/ttl_pulse_switch.py ubuntu/$(BOARD)/test03.py
......@@ -32,9 +33,9 @@ all:
mkdir -p ubuntu/$(BOARD)/boot
mv ubuntu/$(BOARD)/shell/program ubuntu/$(BOARD)/boot
mv ubuntu/$(BOARD)/shell/flash ubuntu/$(BOARD)/boot
wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/download/3696/pts.bit
wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/5468/pts-v4.bit
wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/download/3710/flash_load.bit
wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/download/3515/golden-v0.2_release-v3.0.bin
wget -P ubuntu/$(BOARD)/boot http://www.ohwr.org/attachments/5788/golden-v0.3_release-v4.1.bin
chmod a+x ubuntu/$(BOARD)/shell/*
chmod a+x ubuntu/$(BOARD)/boot/*
......
fm/pts/config/ExpertTools/copy-to-usb.desktop
View file @ 94d1363d
......@@ -3,7 +3,7 @@
Version=1.0
Name=Copy Log to USB
Comment=Copy log and info files to USB key
Exec=gnome-terminal --title "Copy to USB Key" -e "bash -c 'cp /home/pts/ubuntu/ttlbl/log/ttlbl* /media/pts/log'"
Exec=gnome-terminal --title "Copy to USB Key" -e "bash -c 'cp /home/pts-administrator/ubuntu/ttlbl/log/ttlbl* /media/pts-administrator/log'"
Icon=/usr/share/icons/Humanity/apps/48/gnome-session-switch.svg
Terminal=false
Type=Application
......
fm/pts/config/ExpertTools/men-off.desktop
View file @ 94d1363d
......@@ -3,7 +3,7 @@
Version=1.0
Name=VME OFF
Comment=Switch off crate
Exec=/home/pts/ubuntu/ttlbl/shell/men-off
Exec=/home/pts-administrator/ubuntu/ttlbl/shell/men-off
Icon=/usr/share/icons/LoginIcons/apps/48/system-shutdown.svg
Terminal=true
Type=Application
......
fm/pts/config/ExpertTools/men-on.desktop
View file @ 94d1363d
......@@ -3,7 +3,7 @@
Version=1.0
Name=VME ON
Comment=Switch on crate
Exec=/home/pts/ubuntu/ttlbl/shell/men-on
Exec=/home/pts-administrator/ubuntu/ttlbl/shell/men-on
Icon=/usr/share/icons/LoginIcons/apps/48/view-refresh.svg
Terminal=true
Type=Application
......
fm/pts/config/ExpertTools/run-one-pts.desktop
View file @ 94d1363d
......@@ -3,8 +3,8 @@
Version=1.0
Name=Run One PTS CONV-TTL-BLO Test
Comment=Automated testing for the CONV-TTL-BLO board
Exec=gnome-terminal --geometry 81x32+0+0 --title "PTS Run One Window" -e "bash -c 'cd /home/pts/ubuntu/ttlbl/;./one'"
Icon=/home/pts/ubuntu/ttlbl/config/pts-ico-2.png
Exec=gnome-terminal --geometry 81x32+0+0 --title "PTS Run One Window" -e "bash -c 'cd /home/pts-administrator/ubuntu/ttlbl/;./one'"
Icon=/home/pts-administrator/ubuntu/ttlbl/config/pts-ico-2.png
Terminal=false
Type=Application
Categories=Utility;Application;
......
fm/pts/config/ExpertTools/tar-log.desktop
View file @ 94d1363d
......@@ -3,7 +3,7 @@
Version=1.0
Name=Make log.tar.gz USB zip
Comment=Make tarball from log data on USB key
Exec=/home/pts/ubuntu/ttlbl/shell/tar-log
Exec=/home/pts-administrator/ubuntu/ttlbl/shell/tar-log
Icon=/usr/share/icons/Humanity/devices/48/gnome-dev-zipdisk.svg
Terminal=true
Type=Application
......
fm/pts/config/expert-tools.desktop
View file @ 94d1363d
......@@ -3,7 +3,7 @@
Version=1.0
Name=PTS Expert Tools
Comment=PTS Utilities
Exec=/usr/bin/nautilus /home/pts/ubuntu/ttlbl/config/ExpertTools/
Exec=/usr/bin/nautilus /home/pts-administrator/ubuntu/ttlbl/config/ExpertTools/
Icon=/usr/share/icons/Humanity/apps/48/gconf-editor.svg
Terminal=false
Type=Application
......
fm/pts/config/run-pts.desktop
View file @ 94d1363d
......@@ -3,8 +3,8 @@
Version=1.0
Name=Run PTS CONV-TTL-BLO
Comment=Automated testing for the CONV-TTL-BLO board
Exec=gnome-terminal --geometry 81x32+0+0 --title "PTS Main Window" -e "bash -c 'cd /home/pts/ubuntu/ttlbl/; ./pts'"
Icon=/home/pts/ubuntu/ttlbl/config/pts-ico-2.png
Exec=gnome-terminal --geometry 81x32+0+0 --title "PTS Main Window" -e "bash -c 'cd /home/pts-administrator/ubuntu/ttlbl/; ./pts'"
Icon=/home/pts-administrator/ubuntu/ttlbl/config/pts-ico-2.png
Terminal=false
Type=Application
Categories=Utility;Application;
......
fm/pts/config/show-info.desktop
View file @ 94d1363d
......@@ -3,7 +3,7 @@
Version=1.0
Name=Show PTS Info
Comment=Show PTS info
Exec=bash -c "cd /home/pts/ubuntu/ttlbl/shell/; ./show-info"
Exec=bash -c "cd /home/pts-administrator/ubuntu/ttlbl/shell/; ./show-info"
Icon=/usr/share/icons/Humanity/apps/48/xfce-system-info.svg
Terminal=false
Type=Application
......
fm/pts/config/show-log.desktop
View file @ 94d1363d
......@@ -3,7 +3,7 @@
Version=1.0
Name=Show PTS Log
Comment=Show PTS log
Exec=bash -c "cd /home/pts/ubuntu/ttlbl/shell/; ./show-log"
Exec=bash -c "cd /home/pts-administrator/ubuntu/ttlbl/shell/; ./show-log"
Icon=/usr/share/icons/Humanity/apps/48/xfce-man.svg
Terminal=false
Type=Application
......
fm/pts/python/flashtest.py
View file @ 94d1363d
......@@ -66,11 +66,11 @@ def main(bus,tname,inf,log):
"""
tests : Flash chip IC20
uses : golden-v0.2_release-v3.0.bin and flashtest.py
uses : golden-v0.3_release-v4.1.bin and flashtest.py
"""
GWVERS_RELEASE = 3.0
GWVERS_GOLDEN = 0.2
GWVERS_RELEASE = 4.1
GWVERS_GOLDEN = 0.3
# Set the precision of gateware versions based on the number of digits the
# fractional part thereof has; this is done to avoid exceptions in the
......
fm/pts/python/hwvertest.py 0 → 100755
View file @ 94d1363d
##_______________________________________________________________________________________________
##
## CONV-TTL-BLO PTS
##
## CERN,BE/CO-HT
##_______________________________________________________________________________________________
##
##-----------------------------------------------------------------------------------------------
##
## CONV-TTL-BLO pcb version
##
##-----------------------------------------------------------------------------------------------
##
## Description Test whether the version of PCB is the expected one
##
##
## Authors Maciej Lipinski (maciej.lipinski@cern.ch)
## Website http://www.ohwr.org/projects/pts
## Date 17/08/2017
##-----------------------------------------------------------------------------------------------
##
##------------------------------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
## ------------------------------------
## This source file is free software; you can redistribute it and/or modify it under the terms of
## the GNU Lesser General Public License as published by the Free Software Foundation; either
## version 2.1 of the License, or (at your option) any later version.
## This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
## without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details.
## You should have received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-------------------------------------------------------------------------------------------------
##-------------------------------------------------------------------------------------------------
## Import
##-------------------------------------------------------------------------------------------------
# Import system modules
import sys
sys.path.append("log/")
import time
import os, errno, re, sys, struct
import os.path
import traceback
import glob
import binascii
# Import common modules
from ctypes import *
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## main --
##-------------------------------------------------------------------------------------------------
def main(bus,tname,inf,log):
"""
tests : Hardware version
uses : pts.bit and hwvertest.py
"""
HWVERS = 4.1
pel = PTS_ERROR_LOGGER(inf,log)
try:
# Read PCB version: a 6 bits representing HW/PCB version number
# 4 MSB represent HW version number (major)
# 2 LSB represent number of execution (minor)
# Eg: value 010010 represents PCB version 4.2
hwvers = (bus.vv_read(CSR) & 0x3F00) >> CSR_HWVERS_OFS
maj = int(hwvers >> 2)
min = float(hwvers & 0x03)
min /= 10
hwvers = maj + min
# and now check if appropriate
if (hwvers == HWVERS):
msg = "HW/PCB version correct: %2.1f\n" % (hwvers)
inf.write(msg)
else:
msg = "ERROR: HW/PCBe version (%2.1f) incorrect - expected %2.1f" % (hwvers, HWVERS)
pel.set(msg)
print "-->%s" % msg
return pel.get()
except BusException, e:
raise PtsError("SKT Exception: %s" % (e))
except BusWarning, e:
raise PtsError("SKT Warning: %s" % (e))
fm/pts/python/jpts.py
View file @ 94d1363d
......@@ -193,65 +193,99 @@ if __name__ == '__main__':
except BusWarning, e:
print "Warning:Bus Exception: %s" % (e)
# Start running the tests.
for t in tns:
# Test version of HW/PCB before running any other tests
tname = "hwvertest"
try:
# First load a firmware and read back a register to confirm correct load.
if bus.vv_load() == 0:
msg = "INFO: Found CONV-TTL-BLO board in slot %d\n" % (lun)
inf.write(msg + '\n')
# The test is passed the test name, the log and info files and the
# bus object. The test program returns the number of errors that
# occured. If no errors occur, the test PASSes, otherwise it FAILs.
cc = run_test(tname,bus,inf,log)
if cc == 0:
msg = "PASS: %s" % (tname)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
else:
msg = "FAIL: %s->%s" % (tname, lnk_ptr(tname))
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
tname = "test%02d" % t[0]
pyt = "%s/%s.py" % (dir, tname)
except Exception, e:
if options.debug:
print e
traceback.print_exc()
if path.exists(pyt) and path.isfile(pyt) and access(pyt, R_OK):
msg = "FAIL: %s->%s (%s)" % (tname, lnk_ptr(tname), e)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
for n in range(t[1]):
# Start running the tests, only if the HW/PCB version is OK
if cc == 0:
for t in tns:
if n == 10:
msg = "Printing suppresses after 10 runs"
print msg
log.write('\n' + msg + '\n')
inf.write('\n' + msg + '\n')
tname = "test%02d" % t[0]
pyt = "%s/%s.py" % (dir, tname)
if n < 10:
msg = "Run:%d Begin:%s" % (n+1,tname)
print msg
log.write('\n' + msg + '\n')
inf.write('\n' + msg + '\n')
if path.exists(pyt) and path.isfile(pyt) and access(pyt, R_OK):
try:
# First load a firmware and read back a register to confirm correct load.
if bus.vv_load() == 0:
msg = "INFO: Found CONV-TTL-BLO board in slot %d\n" % (lun)
inf.write(msg + '\n')
for n in range(t[1]):
# Each test is passed the test name, the log and info files and the
# bus object. The test program is expected to return the number of
# errors that occured. If no errors occur, the test PASSes, otherwise
# it FAILs.
cc = run_test(tname,bus,inf,log)
if cc == 0:
msg = "PASS: %s" % (tname)
log.write(msg + '\n')
inf.write(msg + '\n')
if n == 10:
msg = "Printing suppresses after 10 runs"
print msg
log.write('\n' + msg + '\n')
inf.write('\n' + msg + '\n')
if n < 10:
msg = "Run:%d Begin:%s" % (n+1,tname)
print msg
else:
msg = "FAIL: %s->%s" % (tname, lnk_ptr(tname))
log.write('\n' + msg + '\n')
inf.write('\n' + msg + '\n')
try:
# First load a firmware and read back a register to confirm correct load.
if bus.vv_load() == 0:
msg = "INFO: Found CONV-TTL-BLO board in slot %d\n" % (lun)
inf.write(msg + '\n')
# Each test is passed the test name, the log and info files and the
# bus object. The test program is expected to return the number of
# errors that occured. If no errors occur, the test PASSes, otherwise
# it FAILs.
cc = run_test(tname,bus,inf,log)
if cc == 0:
msg = "PASS: %s" % (tname)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
else:
msg = "FAIL: %s->%s" % (tname, lnk_ptr(tname))
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
except Exception, e:
if options.debug:
print e
traceback.print_exc()
msg = "FAIL: %s->%s (%s)" % (tname, lnk_ptr(tname), e)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
except Exception, e:
if options.debug:
print e
traceback.print_exc()
msg = "FAIL: %s->%s (%s)" % (tname, lnk_ptr(tname), e)
log.write(msg + '\n')
inf.write(msg + '\n')
print msg
if n < 10:
msg = "Run:%d End:%s\n" % (n+1,tname)
print msg
log.write(msg + '\n')
inf.write(msg + '\n')
if n < 10:
msg = "Run:%d End:%s\n" % (n+1,tname)
print msg
log.write(msg + '\n')
inf.write(msg + '\n')
# Close the bus and the files
bus.vv_close()
......
fm/pts/python/pts.py
View file @ 94d1363d
......@@ -63,9 +63,13 @@ import re
sys.path.append('.')
sys.path.append("pyts/")
# Import here ptsdefine.py, to avoid "uncaught" exceptions later on
from ptsexcept import *
from vv_pts import *
from ptsdefine import *
##-------------------------------------------------------------------------------------------------
## Method to turn on the VME crate.
##-------------------------------------------------------------------------------------------------
......@@ -104,6 +108,7 @@ if __name__ == '__main__':
# Turn off the VME crate
men_off()
bus = SKT(ELMASLOT)
# Scan the first barcode
while True:
sn1 = raw_input("--> Scan the 1st barcode: ")
......@@ -168,7 +173,7 @@ if __name__ == '__main__':
time.sleep(1)
# ... power-cycle the crate
print "VME Crate power-cycle..."
print "VME crate power-cycle..."
men_off()
time.sleep(5)
men_on()
......@@ -184,16 +189,59 @@ if __name__ == '__main__':
subprocess.call("grep PASS log/*.log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("grep FAIL log/*.log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
# Save results on USB key...
print "\nSaving test results on USB key"
# Save results on local folder...
print "\nSaving test results in /home/pts-administrator/pts/log/tblo"
try:
subprocess.call("mkdir -p /media/pts/log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("cp log/*.log /media/pts/log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("cp log/*.inf /media/pts/log", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("mkdir -p /home/pts-administrator/pts/log/tblo", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("cp log/*.log /home/pts-administrator/pts/log/tblo", shell=True, stdout=sys.stdout, stderr=sys.stderr)
subprocess.call("cp log/*.inf /home/pts-administrator/pts/log/tblo", shell=True, stdout=sys.stdout, stderr=sys.stderr)
except e:
print "ERROR: No access to USB key at /media/pts"
print "ERROR: No access to directory /home/pts-administrator/pts/tblo"
print e
#-------------------------------------------------------------------------------
# Reading board unique ID and storing to separate log file
#-------------------------------------------------------------------------------
# ... power-cycle the crate
print "VME Crate power-cycle..."
men_off()
time.sleep(3)
men_on()
time.sleep(10)
#Read unique board ID
IDMS = bus.vv_read(UIDREGMS)
IDLS = bus.vv_read(UIDREGLS)
#Generate log file
# Generate output file named according to current time
fname = time.strftime("serial-num-CTDAH-%Y-%m-%d", time.localtime()) + ".txt"
ret = subprocess.call(["ls /home/pts-administrator/pts/log/tblo | grep " + fname], shell=True, stdout=None, stderr=None)
#print ("%d" % ret)
if (ret != 0):
f = open("/home/pts-administrator/pts/log/tblo/" + fname, "w")
print(" File not found ... Create new one \n ")
f.write("\n")
f.write("CONV-TTL-BLO Upgrade log created on %s \n" % time.strftime("%Y-%m-%d-%Hh%Mm%Ss", time.localtime()))
f.write("--------------------------------------------------------------------------------- \n")
f.write("Barcode 1 | Barcode 2 | PCB ID |\n")
f.write("--------------------------------------------------------------------------------- \n")
f.close()
print("Upgrade log can be found in /home/pts-administrator/pts/log/tblo/%s \n" % fname)
print ("Board unique ID can be found in /home/pts-administrator/pts/log/tblo/%s \n" % fname)
f = open("/home/pts-administrator/pts/log/tblo/" + fname, "a")
f.write("%s \t %s \t %x%x\n" % (sn1, sn2, IDMS, IDLS) )
f.close()
#-------------------------------------------------------------------------------
# We're done, turn off the VME crate
print "\nTesting completed!"
men_off()
......
fm/pts/python/ptsdefine.py
View file @ 94d1363d
......@@ -58,10 +58,7 @@ CSR_STLEDT_OFS = 1
CSR_RLEDT_OFS = 2
CSR_TTLPT_OFS = 3
CSR_REARPT_OFS = 4
CSR_TSTCVCC_OFS = 5
CSR_TSTCMUXEN_OFS = 6
CSR_TSTCS0_OFS = 7
CSR_TSTCS1_OFS = 8
CSR_HWVERS_OFS = 8
CSR_RST_UNLOCK_OFS = 14
CSR_RST_OFS = 15
CSR_SWITCH_OFS = 16
......@@ -74,11 +71,16 @@ LSR = 0x008
LSR_FRONT_OFS = 0
LSR_FRONTINV_OFS = 6
LSR_REAR_OFS = 10
LSR_REARFS_OFS = 26
# 1-Wire base address, used in therm_id.py
TEMP_1WIRE_BASE = 0x010
# 1-Wire unique ID
UIDREGLS = 0xac # 1-wire chip Unique ID - LSB
UIDREGMS = 0xb0 # 1-wire chip Unique ID - MSB
# DAC and clock info registers and offsets, used in dac_vcxo_pll.py
PLL_DAC_BASE = 0X020
VCXO_DAC_BASE = 0x080
......
fm/pts/python/ttl_pulse_switch.py
View file @ 94d1363d
......@@ -153,6 +153,20 @@ def main(bus, tname, inf, log):
chans = ['1', '2', '3', '4', '5', '6', 'A', 'B', 'C', 'D']
try:
# Ask the user to make the daisy-chain
print("Please plug in the patch board for front panel daisy-chaining:\n")
reply = raw_input("Is the patch board plugged-in? (yes/no) ")
while True:
if "yes" in reply.lower():
break
if "no" in reply.lower():
msg = "ERROR: No daisy-chain on front panel"
pel.set(msg)
return pel.get()
else:
reply = raw_input('Please type "yes" or "no" to continue: ')
# Initialize a pulse counter object
pc = CPulseCounter(bus, PULSE_CNT_BASE)
......
fm/pts/shell/flash
View file @ 94d1363d
#!/bin/bash
xc3sprog -c xpc flash_load.bit
xc3sprog -c xpc -I golden-v0.2_release-v3.0.bin:w:0:bin
xc3sprog -c xpc -I golden-v0.3_release-v4.1.bin:w:0:bin
fm/pts/shell/program
View file @ 94d1363d
#!/bin/bash
xc3sprog -c xpc pts.bit
xc3sprog -c xpc pts-v4.bit
fm/pts/shell/tar-log
View file @ 94d1363d
#!/bin/bash
cd
cd /media/pts
cd /media/pts-administrator
rm -f log.tar.gz
tar cvzf log.tar.gz log
cd
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