Maximum pulse repetition frequency for blocking channels
The thermal properties of the BSH103 power MOSFET and their limiting
values, are directly responsible for the achievable repetition frequency
on the CONV-TTL-BLO. This has been discussed in depth as part of the
blocking output circuit protection
In V3 boards and above, current limitation and pulse width-liming
trigger circuit (maximum 8us) have been implemented to provide more
adequate hardware protection.
However, the FPGA gateware will still be responsible for implementing
ceilings on frequency repetition and fixed pulse width values.
Aim of stress tests
Two modes of operation are foreseen for the new version of the
CONV-TTL-BLO board. It will in fact be able to operate short 250ns
pulses and long ones at 1.2us. The aim of these tests will be to
identify the operating frequencies in these two modes, in the following
Continuous: Pulses can be repeated continuously. For higher
input rates, pulses will be missed on the output and a flag will be
> Aim of tests: Identify maximum pulse frequency supported by the
blocking output stage for continuous operation for both pulse
Fast: The CONV-TTL-BLO board will can support higher frequencies
(greater than that of continuous mode), provided it is for a limited
amount of time. This mode of operation is also known as burst
> Aim of tests: Identify the maximum repetition frequency that can
be achieved and how long before this frequency can cause
irreversible damage to the board.
The outcome of these tests can take a number of forms:
The amount of time the board can sustain maximum rate of repetition,
without being damaged.
A target average frequency over a time period.
A relationship between repetition frequencies and the time for which
the board can sustain it safely.
Minimal pulse definition:
Pulse width: It shall be specified as 1.2us for the long pulse
definition and 250ns for the short pulse definition. The short 250ns
pulse is long enough to match exisisting CERN pulse repeaters (Fast
versions), and short enough to cause as little temperature rise in
the power MOSFET as manageable. The short pulse mode should
therefore achieve the highest frequency rates, foreseen at around
Maximum allowable frequency: This is equivalent to the maximum
duty cycle allowed for 250ns pulses. An initial maximum 12.5% duty
cycle will be assumed. This corresponds to maximum 500kHz pulses.
> This Duty cycle might be increased during further tests to 50%
corresponding to 2MHz frequency to see how much it impacts on
Test procedure and requirements
The diagram below summarises the test
Figure 1: Diagram describing the test system components and the flow of
control and output data.
CONV-TTL-BLO V3 (Note 1) and RTM (Rear Transition Module) board
plugged on VME64x ELMA crate and reachable via telnet.
Oscilloscope to check for pulse shape one channel at a time.
Temperature probe To check MOSFET temperature.
Computer on same network as ELMA crate and running the necessary
software (Python) scripts.
Lemo cables and appropriate termination to be used to connect the
Gateware & Software
The on-board FPGA will be programmed with the
bitsream, a special gateware release for long-term testing. It
provides the user with the possibility of setting pulse repetition
parameters, by writing into a set of registers, via I2C. The
gateware offers the following functionality:
Set pulse width, repetition frequency and delay.
Read Input counters.
Read Output counters.
Software script to write into board registers and set the output for
a particular channel to the desired parameters.
Log files will be saved with test parameters and final counter
In the Elma crate, plug in one CONV-TTL-BLO Front module board and
one RTM module.
There are six available channels on the board with equal
performance. Two channels will be used, as shown in Figure 1, above:
A Channel under tests (CUD): This channel output circuit
will be tested for performance with incrementally increasing
repetition frequency, until it is irreversibly damaged. Since
irreversible damage is an extreme point to reach, the tests are
stopped when temperature reaches a high value of 70Deg (Note 2).
The point at which this occurs needs to be recorded and used as
a time to failure figure. If the same test is repeated on
multiple channels than a mean time to failure figure may
also be calculated.
A monitoring channel (MC): This can be any one of the other
5 remaining channels that are left on the board. The blocking
output pulse of the CUT is fed to the blocking input of the MC.
This channel will be used for counting pulses at its input and
not for repetition.
Set pulse width.
Each test will run a chosen repetition frequency, from list, Eg:
1kHz, 5kHz, 10kHz, 50kHz, 100kHz, 150kHz, 200kHz, 300kHz,
The test must be stopped when the blocking output is considered
"too hot". This is detected when:
The temperature probe indicates 70deg or higher.
The blocking output pulse disappears from the Oscilloscope
screen (Or when the damage to blocking output is seen... or
smelt). The test must be stopped.
The Python scripts should be able to detect this by
comparing the read out from the MC channel counter, with
that of the CUT. If the MC count is smaller than the CUT
count, or the MC count stops incrementing, then the blocking
output must be damaged.
The outcome of tests will be recorded on a log sheet, that can
be found in the files section below.
Tests have been carried out and the results are shown in the following
two diagrams for long and short
Figure 2: Approximate frequency Vs time-to-failure (70deg C) for 250ns
Figure 2: Approximate frequency Vs time-to-failure (70deg C) for 1.2us
These tests should be carried out for the characterisation of blocking
output stage resilience to high temperatures. Should new MOSFETs be used
in future version of the conv-ttl-blo board, then such tests should be
carried out to identify achievable frequencies.
The tests could of course be improved if more precise temperature
measurment devices are used, with a direct link to software for precise
time-to-failure measurements. However, since the results shown in
figures 2 and 3 must be heavily derated for safety, then precise
measurements will not add considerable value to these tests.
Note 1: As a minor bug has been identified in V3 boards, which has been
described in issue #1404. The V3 prototypes used in these stress tests
will have the missing resistor manually added, before being permanently
added in V4 boards.
Note 2: Tests are run in worst case conditions, with a crate that is not