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Conv TTL Blocking - Hardware
Commit 6b4982a0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Added simulation files

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sim/README 0 → 100644
View file @ 6b4982a0
This folder contains simulation files for the CONV-TTL-BLO TTL input stage and
blocking output stage.
Load the .asc files into LTSpice to run the simulations.
sim/blo-output.asc 0 → 100644
View file @ 6b4982a0
Version 4
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TEXT -1872 -2224 Left 2 !K1 L1 L2 1
TEXT -1872 -2192 Left 2 !K2 L3 L4 1
TEXT -1872 -2128 Left 2 !.tran 0 10u 0 1u
TEXT -1872 -2160 Left 2 !.inc BSH103.lib
sim/ttl-input.asc 0 → 100644
View file @ 6b4982a0
Version 4
SHEET 1 880 680
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TEXT -588 216 Left 2 !.tran 100u
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