Commit 2d08a26c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Updated hardware guide to v1.1

parent 6b4982a0
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill January 21, 2015
\hfill January 27, 2015
\vspace*{3cm}
......
......@@ -72,6 +72,8 @@ work, see \\
26-07-2013 & 0.2 & Second draft \\
21-01-2015 & 1.0 & First release, adding blocking output max. pulse duty cycle calculation and several extra information
about the blocking output stage \\
27-01-2015 & 1.1 & Added (in Appendix~\ref{app:blo-max-freq}) a specification of why the pulse period was selected as it
is in the user guide \\
\hline
\end{tabular}
}
......@@ -945,16 +947,29 @@ duty cycle divided by 10,
{\delta}_{max, final} = \frac{{\delta}_{max}}{10} \cong 0.005
\end{equation}
This yields to the final minimum period stated in the CONV-TTL-BLO User Guide \cite{ctb-ug},
This yields to a minimum period of,
\begin{equation}
T_{min, final} = \frac{T_{pulse}}{{\delta}_{max, final}} = \frac{1.2{\mu}s}{0.005} = 240{\mu}s
T_{min} = \frac{T_{pulse}}{{\delta}_{max, final}} = \frac{1.2{\mu}s}{0.005} = 240{\mu}s
\end{equation}
\noindent and the maximum pulse frequency,
The value stated in the CONV-TTL-BLO User Guide~\cite{ctb-ug} is 1~$\mu$s more than
this value, due to the fact that the FPGA logic~\cite{ctb-hdlguide} contains a pulse
repeater module which enters in a rejection period after a pulse arrives at the input.
Since this logic is sampled, if there is jitter on input pulses arriving at a frequency
of 4166 Hz, which corresponds to the 1/200 duty cycle of the pulses, the logic may still
be in the rejection state counting the rejection period. This in turn may lead to a pulse
being missed and not replicated at the output. To avoid any pulses being missed, the
minimum period stated in the CONV-TTL-BLO User Guide~\cite{ctb-ug} is,
\begin{equation}
f_{max, final} = \frac{1}{T_{min, final}} = 4.166kHz
T_{min, final} = 241 {\mu}s
\end{equation}
\noindent and respectively, the maximum pulse frequency,
\begin{equation}
f_{max, final} = \frac{1}{T_{min, final}} = 4150 Hz
\end{equation}
%==============================================================================
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