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Conv TTL Blocking - Hardware
Commit 07dbd46f authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Modifications to reflect changes in v4 boards

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doc/hwg/cern-title.aux 0 → 100644
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doc/hwg/cern-title.tex
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......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill January 27, 2015
\hfill February 6, 2017
\vspace*{3cm}
......@@ -24,7 +24,8 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}\\
\\textit{Last edited by {\textbf{Denia Bouhired-Ferrag (CERN/BE-CO-HT)}}}
\noindent \rule{\textwidth}{.05cm}
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doc/hwg/hwg-conv-ttl-blo.bib
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......@@ -15,6 +15,20 @@
howpublished = {\url{http://www.ohwr.org/documents/290}}
}
@misc{blo-out-protect,
author = "Denia Bouhired",
title = {{CONV-TTL-BLO: Improving reliability and performance of the blocking output}},
month = 09,
year = 2016,
howpublished = {\url{http://www.ohwr.org/documents/493}}
}
@misc{hotswap-issue,
title = {Hot plugging blows main board ({MOSFETs}), http://www.ohwr.org/issues/1104},
Date = {July 2015}
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
......
doc/hwg/hwg-conv-ttl-blo.blg 0 → 100644
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This is BibTeX, Version 0.99dThe top-level auxiliary file: hwg-conv-ttl-blo.aux
A level-1 auxiliary file: cern-title.aux
I found no \bibdata command---while reading file hwg-conv-ttl-blo.aux
I found no \bibstyle command---while reading file hwg-conv-ttl-blo.aux
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\BOOKMARK [1][-]{Doc-Start}{Licensing information}{}% 1
\BOOKMARK [1][-]{section*.2}{Revision history}{}% 2
\BOOKMARK [1][-]{toc.1}{Contents}{}% 3
\BOOKMARK [1][-]{section*.6}{List of abbreviations}{}% 4
\BOOKMARK [1][-]{section.1}{Introduction}{}% 5
\BOOKMARK [2][-]{subsection.1.1}{Additional documentation}{section.1}% 6
\BOOKMARK [1][-]{section.2}{Front module}{}% 7
\BOOKMARK [2][-]{subsection.2.1}{VME connector}{section.2}% 8
\BOOKMARK [2][-]{subsection.2.2}{Power supplies}{section.2}% 9
\BOOKMARK [2][-]{subsection.2.3}{Clock circuits}{section.2}% 10
\BOOKMARK [2][-]{subsection.2.4}{FPGA}{section.2}% 11
\BOOKMARK [2][-]{subsection.2.5}{TTL pulse repetition}{section.2}% 12
\BOOKMARK [3][-]{subsubsection.2.5.1}{TTL input stage}{subsection.2.5}% 13
\BOOKMARK [3][-]{subsubsection.2.5.2}{TTL output stage}{subsection.2.5}% 14
\BOOKMARK [2][-]{subsection.2.6}{Blocking pulse repetition}{section.2}% 15
\BOOKMARK [3][-]{subsubsection.2.6.1}{Blocking input stage}{subsection.2.6}% 16
\BOOKMARK [3][-]{subsubsection.2.6.2}{Blocking output stage}{subsection.2.6}% 17
\BOOKMARK [2][-]{subsection.2.7}{SFP connector}{section.2}% 18
\BOOKMARK [2][-]{subsection.2.8}{Thermometer and flash chip}{section.2}% 19
\BOOKMARK [2][-]{subsection.2.9}{RTM detection}{section.2}% 20
\BOOKMARK [2][-]{subsection.2.10}{Status and pulse LEDs}{section.2}% 21
doc/hwg/hwg-conv-ttl-blo.ps 0 → 100644
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doc/hwg/hwg-conv-ttl-blo.tex
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......@@ -74,6 +74,7 @@ work, see \\
about the blocking output stage \\
27-01-2015 & 1.1 & Added (in Appendix~\ref{app:blo-max-freq}) a specification of why the pulse period was selected as it
is in the user guide \\
06-02-2017 & 4.0 & Added description of blocking output circuit protection and PCB version circuit\\
\hline
\end{tabular}
}
......@@ -467,22 +468,30 @@ The maximum 24~V pulse duty cycle that can be safely sustained by the input stag
\noindent The blocking output stage is a flyback converter design with a 1:1 conversion
ratio, shown in Figure~\ref{fig:blo-outp-cap}. The core part of the output stage is
the flyback transformer assuring galvanic isolation at the output. The transformer is
driven straight from the 24~V blocking supply and controlled via the BSH103 power MOSFET.
the flyback transformer assuring galvanic isolation at the output. This part of the board has been subject to a review a redesign for v3 boards and later, this is desicussed in detail in~\cite{bib:blo-out-protect}.
In previous versions of the board (v2.1 and earlier) the transformer was driven straight from the 24~V blocking supply and controlled via the BSH103 power MOSFET.
This however exposed the transformer and MOSFET to potential damage, due to uncontrolled current flow from the power supply. For this reason in boards v3 and later, a current limiting resistor is added between the transformer primary and the 24 V rail as shown in fig.\ref{fig:blo-outp-v4}. The presence of the resistor between the decoupling capacitor
and power supply, causes the capacitor to charge at power on. When a pulse comes through from the FPGA, the voltage across the inductor changes and current starts to flow from the capacitor and resistor through to the transformer.\\
The snubber circuit next to the transformer formed by the BAR66 diode and the Zener diode
provides a means to dissipate the energy stored in the leakage inductance of the transformer
when the MOSFET is on.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/blo-outp-cap}}
\caption{Blocking output stage}
\label{fig:blo-outp-cap}
\caption{Blocking output stage- v2.1 and earlier.}
\label{fig:blo-outp-cap-v2-1}
\end{figure}
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/blo-outp-v4}}
\caption{Blocking output stage- v3 and later.}
\label{fig:blo-outp-v4}
\end{figure}
Upstream of the MOSFET's grid pin is a circuit similar to that in the TTL output stage.
This circuit is shown in Figure~\ref{fig:blo-outp-tristate}. The tri-state buffers'
outputs are high-impedance on startup, thus avoidiing spurious signals on blocking outputs.
The pull-down resistors at the outputs ensure a low-level signal on the MOSFET's grid
inputs are pulled-down on startup, thus avoiding spurious signals on blocking outputs. Though these were left in tri-state at startup in v2.1 boards, it was seen that this can cause irreversible damage to the board in some circumstances such as hot-swaps \cite{bib:hotswap-issue}.
The extra pull-down resistors at the outputs ensure a low-level signal on the MOSFET's grid
on startup.
The tri-state buffers are enabled by means of two signals from the FPGA: the output enable
......@@ -492,20 +501,22 @@ not drive either of these signals, the output enable input of the buffers is kep
the pull-up resistor.
\begin{figure}[h]
\centerline{\includegraphics[scale=1]{fig/blo-outp-tristate}}
\centerline{\includegraphics[scale=1]{fig/blo-outp-tristate-v4}}
\caption{Blocking output tri-state buffers}
\label{fig:blo-outp-tristate}
\end{figure}
The maximum pulse duty cycle that can be sustained without damaging the MOSFET
In order to further protect the blocking output stage MOSFET, a pulse width limitation circuit is added on v3 board and later. This circuit can be seen in Fig. \ref{fig:blo-outp-v4} at the gate of the BSH103. It consists of a differentiator RC circuit}, capable of detecting rising pulse edges. The $\tau=RC$ time constant will determine how long the MOSFET is left ON following the rising edge of a pulse. The gate voltage will reach the threshold gate trigger value after $\approx 8\mu s$ to make sure that the gate voltage remains well above threshold during the $1.2\mu s$ window (longest output pulse length) (See~\cite{bib:blo-out-protect} for more details).
In board versions 2.1 and earlier, the maximum pulse duty cycle that can be sustained without damaging the MOSFET
considering nominal blocking pulse widths~\cite{blo-std} of 1.2~$\mu$s, is approximately 4160~Hz
(see Appendix~\ref{app:blo-max-freq}).
(see Appendix~\ref{app:blo-max-freq}). However, by implementing the blocking output stage protection techniques mentioned earlier and outlined in~\cite{bib:blo-out-protect}, these duty cycles can be significantly improved upon. In fact, to achieve very high repetition frequencies, the CONv-TTL-BLO board now offers a pulse-width selection feature, that allows for frequencies of up to 2MHz to be reached, when using narrow pulses ($250ns$). These high repetition frequencies are possible as part of a burst mode functionality, which allows the board to operate at higher frequencies but for a limited amount of time (see~\cite{bib:blo-out-protect} and~\cite{bib:ctb-ug} for more details on operation in this mode).
The blocking output stage is susceptible to common-impedance coupling, due to the high inter-winding
capacitance of the selected transformer. The solution to this problem is provided in the form of the
100~nF capacitor placed between pin 4 of the transformer and the common reference (GND) network. Note
that this capacitor is either straddled on top of the RTM TVS diodes, or placed directly on the RTMP in
newer board versions. This is shown in Figure~\ref{fig:blo-outp-cap} and in Section~\ref{sec:rtm}.
newer board versions. This is shown in Figure~\ref{fig:blo-outp-cap-v2-1} and in Section~\ref{sec:rtm}.
For more details about this common-impedance coupling event, see~\cite{crosstalk}.
\vspace{11pt}
......@@ -609,11 +620,31 @@ for buffering the VME signals. The control and data lines of the chip are driven
by logic within the FPGA, which controls lighting of each of the LEDs. An example
of how the LEDs can be driven using the FPGA is given in Section~5 of~\cite{ctb-hdlguide}.
TTL (front panel) and blocking (rear panel) pulse LEDs are driven by the FPGA
TTL (front panel), INV channels and blocking (rear panel) pulse LEDs are driven by the FPGA
via a SN7414 Schmitt trigger. In the case of the blocking LEDs, the output of
the Schmitt trigger is connected directly to the VME P2 connector and through
the RTM to the piggyback, where the current-limiting resistor and the LEDare located.
%------------------------------------------------------------------------------
% SEC: PCB version
%------------------------------------------------------------------------------
\subsection{PCB version}
\label{sec:diag-pcbvers}
The PCB version is necessary to the operation of the burst mode. Indeed the FPGA reads out the hardware version,
and depending on whether the board is v4 and later or v3 earlier, will enable or disable this functionality accordingly.
The PCB version is provided to the FPGA via a resistor network offering 4 bits for the version number
and 2 bits for potential revisions. The circuit is shown in Fig.~\ref{fig:pcb-version}.
\begin{figure}[h]
\centering
\includegraphics\includegraphics[scale=0.5]{fig/pcb-version.png}
\label{fig:pcb-version}
\end{figure}
Board version can be read as 4 bits, 1s when the resistors are pulled up, 0s when they are pulled down. Board revision is available in 2-bits, read-out in the same way. For example, Fig.~\ref{fig:pcb-version} shows a v4.0 board.
Note that PCB identification is not available in boards v3 and earlier, and therefore will be read as all zeroes in the FPGA.
%==============================================================================
% SEC: RTM, RTMP
%==============================================================================
......
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