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Conv TTL Blocking - Gateware

Release 4 1

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CONV-TTL-BLO gateware version 4.1 and release v4.0

_Release 4.1 barely renames memory mapped registers and bring no functional changes to version 4.0. Therefore the following description that was written for v4.0 originally, still applies.
Note however that though only minor changes with no functional consequence have been added to v4.1, these have only been tested in the lab using existing scripts. V4.0 on the other
hand has been tested in operations for 6 months with no major issues. The sources for version 4.0 are therefore left on this page._

Release notes

  • CHANGES MEMORY MAP FROM PREVIOUS VERSIONS
    • Error bits are moved from SR to a dedicated register ERR
    • Added hardware version bits & changed WRPRES bit location in SR
    • Added failsafe state bits to LSR
    • Separate counters for TTL & blocking
    • New registers:
      • OSWR (Other switch)
      • UIDLR & UIDHR (Thermometer UID)
      • TEMPR (Board Temperature Register)
  • Enables high-frequency operation and support for burst mode in hardware v4 boards.
  • Backward-compatible with v3 boards and earlier, while bringing in some additional features.

Features available in all hardware versions of the board:*

  • PCB version recognition available at the FPGA as 6 bits (4 bits for the version number and 2 bits for the revision) and for diagnostics via the status register SR. For older boards (v3 and below), SR register will indicate 0, as there are no resistors to indicate the PCB version.
  • One-wire thermometer no longer accessible via one-wire master, instead:
    • Temperature is available in single register as 16-bit value. Temperature = 0d(TEMPR)/16.
    • One-wire chip unique 64-bit ID stored in two 32-bit registers, readable from registers UIDLR and UIDHR.
  • Separate pulse counters for TTL and for BLOCKING inputs, therefore two pulse counters per channel, CHxTTLPCR and CHxBLOPCR.
  • Error data moved from SR (status register) to own ERR register.

Features available in v4 only of the board:*

  • Pulse width selection switch, assigned to dip switch SW1.1.
    • LONG: Pulses are 1.2us long.
    • SHORT: Pulses are 250ns long.
  • Continuous repetition:
    • LONG pulses: maximum continuous repetition frequency 52kHz corresponds to 1/16 duty cycle (19.2us period).
    • SHORT pulses: maximum continuous repetition frequency 571kHz corresponds to 1/7 duty cycle (1.75us period).
  • High frequency Burst repetition: Higher frequencies can be accepted, but for a limited amount of time.
    • LONG pulses: maximum burst frequency 104kHz corresponds to 1/8 duty cycle (8.6us period). Sustained for 1s maximum.
    • SHORT pulses: maximum burst frequency 2MHZ corresponds to 1/2 duty cycle (0.5us period). Sustained for 1s maximum.

Maximum pulse repetition frequency table:

Board version Pulse width Continuous mode Burst mode (1 s pulse bursts)
v2.1-v3 1.2µs 4.16kHz N/A
v4.0 250ns 571kHz 2MHz
v4.0 1.2µs 52kHz 104kHz

Maximum pulse frequency in function of pulse burst time:


Important

The constants used to calibrate the burst mode, and define the frequency cutoff times as shown in the graphs above, can be generated using a spreadsheet attached to this project.

Binary files

Release v4.1

Release v4.0

Sources

Documentation

HDL guide
Generating VHDL constants for burst mode calibration

Denia Bouhired, Maciej Suminski, 23 August 2018