Golden release gateware v0.0
Release notes
- Pulse repetition with max. frequency of 4150 Hz
- 1.2us pulse on output
- duty cycle of 1/200
- input pulses with duty cycle of more than 1/200 are rejected
- I2C to Wishbone bridge following the protocol defined together with ELMA
- Dedicated CONV-TTL-BLO registers (see full memory map in the HDL
guide):
- Board ID register
- CSR
- remote logic reset
- gateware version
- state of on-board switches
- state of RTM detection lines
- state of I2C watchdog timer
- Pulse and status LED control
- Remote reprogramming
Binary files
Sources
- tag v0.0 in repository
- Golden gateware HDL files can be found under the golden branch.
Documentation
- The block diagram of the logic is shown below.
* For information on the implementation of each block, consult the HDL guide:
-
compile from source
git clone -b golden git:https://www.ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-gw.git cd conv-ttl-blo-gw git checkout v0.0 cd doc/hdlguide/ make
Theodor-Adrian Stana, May 2014