Conv TTL Blocking - Gateware tagshttps://ohwr.org/project/conv-ttl-blo-gw/tagshttps://ohwr.org/project/conv-ttl-blo-gw/tags/golden-v0.3-release-v4.1golden-v0.3-release-v4.1Denia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/v4.1v4.1Denia Bouhired-Ferragdenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/Golden-v0.3Golden-v0.3Denia Bouhired-Ferragdenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/v4.0v4.0Denia Bouhireddenia.bouhired@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/v3.0v3.0CONV-TTL-BLO gateware release v3.0
- uses conv-common-gw project
- changes memory map
- per-channel latest timestamp readout from dedicated registers
- line state readoutTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/v0.2v0.2Golden gateware v0.2
- uses conv-common-gw
- changes memory map, in particular, the placement of the MultiBoot module
- adds LSR
- fallback to a golden gateware is now a system error (the ERR LED is lit RED
when the golden gateware is booted from)Theodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/v0.1v0.1Golden gateware v0.1
- adds glitch filter to the logicTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/v0.0v0.0Version 0.0 of golden gateware
- basic pulse repetition without glitch filtering, 1/200 duty cycle
- wb_xil_multiboot module to enable loading a new bitstream to the flashTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/v2.2v2.2Gateware v2.2
Fixes the issue about the first pulse inhibit mechanism not working.
When the first pulse inhibit mechanism was first implemented, the
FSM of the ctblo_pulse_gen module was triggering one clock cycle earlier
than it actually is, due to the trig_gf_on_r_edge_p signal now triggering
said FSM. This meant that the inhibit signal was "de-inhibiting" one clock
cycle too early, thus yielding in a pulse still being generated after reset.
This issue was fixed by introducing a delay into the inhibit signal and checking
for the state of this delayed signal before triggering.Theodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/v2.1v2.1Gateware v2.1
- Tag FIFO is now a rolling tag ring buffer
- Pull down pulse repeater max. duty cycle to 1/200
- Remove rtm_detector and the lighting of the ERR LED when an
RTM is not present
- System errors now light the ERR LED; the errors can be consulted
from the board's SRTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/v2.0v2.0Release version 2.0
Apart from the features in the previous release version, this version adds
support for remote diagnostics via the I2C protocol on the VME backplanes
in ELMA crates.
The main diagnostics features added from the previous version are:
- unique board ID and temperature readout
- input pulse counters
- input pulse time-tagging
- manual pulse triggeringTheodor Stanat.stana@cern.chhttps://ohwr.org/project/conv-ttl-blo-gw/tags/v1.0v1.0Release version 1.0
- basic pulse repetition with limitation to 1/5 duty cycle
- pulse converter general-purpose registers with
-- board ID
-- firmware version
-- state of on-board switches
-- state of RTM detection lines
-- communication watchdog timeout status
-- remote reset with unlock mechanism
- wb_xil_multiboot module for remote reprogrammingTheodor Stanat.stana@cern.ch