--============================================================================== -- CERN (BE-CO-HT) -- Testbench for CONV-TTL-BLO design --============================================================================== -- -- author: Theodor Stana (t.stana@cern.ch) -- -- date of creation: 2014-02-18 -- -- version: 1.0 -- -- description: -- Design-wide simulation testbench for the CONV-TTL-BLO gateware. Currently -- simulated features include: -- - pulse triggering -- -- dependencies: -- None. -- --============================================================================== -- GNU LESSER GENERAL PUBLIC LICENSE --============================================================================== -- This source file is free software; you can redistribute it and/or modify it -- under the terms of the GNU Lesser General Public License as published by the -- Free Software Foundation; either version 2.1 of the License, or (at your -- option) any later version. This source is distributed in the hope that it -- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty -- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -- See the GNU Lesser General Public License for more details. You should have -- received a copy of the GNU Lesser General Public License along with this -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html --============================================================================== -- last changes: -- 2014-02-18 Theodor Stana File created -- 2016-08-01 Denia Bouhired Based on original testbench.vhd by T. Stana -- Modified to test all pulse channels and LEDs -- In addition to the new inv-ttl LEDs -- 2016-01-25 Denia Bouhired Add PCB version input to FPGA --============================================================================== -- TODO: - --============================================================================== library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.gencores_pkg.all; use work.wishbone_pkg.all; use work.conv_common_gw_pkg.all; use ieee.math_real.all; entity testbench is end entity testbench; architecture behav of testbench is --============================================================================ -- Type declarations --============================================================================ type t_state_i2c_mst is ( IDLE, I2C_ADDR, I2C_ADDR_ACK, WB_ADDR_B0, WB_ADDR_B0_ACK, WB_ADDR_B1, WB_ADDR_B1_ACK, ST_OP, RD_RESTART, RD_RESTART_ACK, RD, RD_ACK, WR, WR_ACK, STO, SUCCESS, ERR ); --============================================================================ -- Constant declarations --============================================================================ -- Clock periods constant c_clk_20_per : time := 50 ns; constant c_clk_125_per : time := 8 ns; -- Number of I2C masters and slaves for the I2C bus model constant c_nr_masters : positive := 1; constant c_nr_slaves : positive := 1; --Activate randomly spaced input pulses constant random_intervals : boolean := false; --fixed interval when false, random interval when true. --============================================================================ -- Component declarations --============================================================================ component conv_ttl_blo is port ( -- Clocks clk_20_i : in std_logic; clk_125_p_i : in std_logic; clk_125_n_i : in std_logic; -- Active-low reset for blocking power supply mr_n_o : out std_logic; -- I2C interface scl_i : in std_logic; scl_o : out std_logic; scl_en_o : out std_logic; sda_i : in std_logic; sda_o : out std_logic; sda_en_o : out std_logic; -- VME interface vme_sysreset_n_i : in std_logic; vme_ga_i : in std_logic_vector(4 downto 0); vme_gap_i : in std_logic; -- PCB version recognition pcbrev_i : in std_logic_vector(5 downto 0); -- Channel enable global_oen_o : out std_logic; ttl_oen_o : out std_logic; inv_oen_o : out std_logic; blo_oen_o : out std_logic; -- Front panel channels ttl_n_i : in std_logic_vector(5 downto 0); ttl_o : out std_logic_vector(5 downto 0); inv_n_i : in std_logic_vector(3 downto 0); inv_o : out std_logic_vector(3 downto 0); -- Rear panel channels blo_i : in std_logic_vector(5 downto 0); blo_o : out std_logic_vector(5 downto 0); -- Channel leds led_front_n_o : out std_logic_vector(5 downto 0); led_front_inv_n_o : out std_logic_vector(3 downto 0); led_rear_n_o : out std_logic_vector(5 downto 0); -- SPI interface to on-board flash chip flash_cs_n_o : out std_logic; flash_sclk_o : out std_logic; flash_mosi_o : out std_logic; flash_miso_i : in std_logic; -- PLL DACs -- 20 MHz VCXO control dac20_din_o : out std_logic; dac20_sclk_o : out std_logic; dac20_sync_n_o : out std_logic; -- 125 MHz clock generator control dac125_din_o : out std_logic; dac125_sclk_o : out std_logic; dac125_sync_n_o : out std_logic; -- SFP lines sfp_los_i : in std_logic; sfp_mod_def0_i : in std_logic; sfp_rate_select_o : out std_logic; sfp_mod_def1_b : inout std_logic; sfp_mod_def2_b : inout std_logic; sfp_tx_disable_o : out std_logic; sfp_tx_fault_i : in std_logic; -- Thermometer data port thermometer_b : inout std_logic; -- Switches sw_gp_n_i : in std_logic_vector(7 downto 0); -- RTM lines rtmm_i : in std_logic_vector(2 downto 0); rtmp_i : in std_logic_vector(2 downto 0); -- Front panel bicolor LEDs led_ctrl0_o : out std_logic; led_ctrl0_oen_o : out std_logic; led_ctrl1_o : out std_logic; led_ctrl1_oen_o : out std_logic; led_multicast_2_0_o : out std_logic; led_multicast_3_1_o : out std_logic; led_wr_gmt_ttl_ttln_o : out std_logic; led_wr_link_syserror_o : out std_logic; led_wr_ok_syspw_o : out std_logic; led_wr_ownaddr_i2c_o : out std_logic ); end component conv_ttl_blo; -- I2C bus model component i2c_bus_model is generic ( g_nr_masters : positive := 1; g_nr_slaves : positive := 1 ); port ( -- Input ports from master lines mscl_i : in std_logic_vector(g_nr_masters-1 downto 0); msda_i : in std_logic_vector(g_nr_masters-1 downto 0); -- Input ports from slave lines sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0); ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0); -- SCL and SDA line outputs scl_o : out std_logic; sda_o : out std_logic ); end component i2c_bus_model; -- I2C master component i2c_master_byte_ctrl is port ( clk : in std_logic; rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) ena : in std_logic; -- core enable signal clk_cnt : in unsigned(15 downto 0); -- 4x SCL -- input signals start, stop, read, write, ack_in : std_logic; din : in std_logic_vector(7 downto 0); -- output signals cmd_ack : out std_logic; -- command done ack_out : out std_logic; i2c_busy : out std_logic; -- arbitration lost i2c_al : out std_logic; -- i2c bus busy dout : out std_logic_vector(7 downto 0); -- i2c lines scl_i : in std_logic; -- i2c clock line input scl_o : out std_logic; -- i2c clock line output scl_oen : out std_logic; -- i2c clock line output enable, active low sda_i : in std_logic; -- i2c data line input sda_o : out std_logic; -- i2c data line output sda_oen : out std_logic -- i2c data line output enable, active low ); end component i2c_master_byte_ctrl; --============================================================================ -- Signal declarations --============================================================================ signal clk_20, clk_125 : std_logic; signal clk_125_p, clk_125_n : std_logic; signal rst_n, rst : std_logic; signal pulse_led_front_n : std_logic_vector(6 downto 1); signal pulse_led_front : std_logic_vector(6 downto 1); signal pulse_led_inv_n : std_logic_vector(4 downto 1); signal pulse_led_inv : std_logic_vector(4 downto 1); signal pulse_led_rear_n : std_logic_vector(6 downto 1); signal pulse_led_rear : std_logic_vector(6 downto 1); signal ttl_inp_n, ttl_outp : std_logic_vector(6 downto 1); signal ttl_pulse : std_logic_vector(6 downto 1); signal inv_inp, inv_inp_n, inv_outp : std_logic_vector(4 downto 1); signal inv_pulse : std_logic_vector(4 downto 1); signal blo_inp, blo_outp : std_logic_vector(6 downto 1); signal blo_pulse : std_logic_vector(6 downto 1); signal oe, blo_oe, ttl_oe, inv_oe : std_logic; signal switches_n : std_logic_vector(7 downto 0); signal pcbversn : std_logic_vector(5 downto 0); -- I2C signals signal state_i2c_mst : t_state_i2c_mst; signal mst_fsm_op : std_logic; signal mst_fsm_start : std_logic; signal stim_cnt : unsigned(31 downto 0); signal cnt : unsigned(2 downto 0); signal buf_byte_cnt : integer; signal once : boolean; signal byte_cnt : unsigned(1 downto 0); signal rcvd : std_logic_vector(31 downto 0); signal send : std_logic_vector(31 downto 0); signal send_val : std_logic_vector(31 downto 0); signal wrote : std_logic; signal slv_addr : std_logic_vector(6 downto 0); signal adr : std_logic_vector(31 downto 0); signal mst_sta : std_logic; signal mst_sto : std_logic; signal mst_rd : std_logic; signal mst_wr : std_logic; signal mst_ack : std_logic; signal mst_dat_in : std_logic_vector(7 downto 0); signal mst_dat_out : std_logic_vector(7 downto 0); signal mst_cmd_ack : std_logic; signal ack_fr_slv : std_logic; signal mscl, msda : std_logic_vector(c_nr_masters-1 downto 0); signal sscl, ssda : std_logic_vector(c_nr_slaves-1 downto 0); signal scl, sda : std_logic; signal scl_fr_mst : std_logic; signal scl_en_mst : std_logic; signal sda_fr_mst : std_logic; signal sda_en_mst : std_logic; signal scl_fr_slv : std_logic; signal scl_en_slv : std_logic; signal sda_fr_slv : std_logic; signal sda_en_slv : std_logic; signal inv_flag_n : boolean; signal rand_num : integer := 0; signal j : integer := 0; --============================================================================== -- architecture begin --============================================================================== begin --============================================================================ -- Generate clock signals --============================================================================ p_clk_20 : process begin clk_20 <= '1'; wait for c_clk_20_per/2; clk_20 <= '0'; wait for c_clk_20_per/2; end process; p_clk_125 : process begin clk_125 <= '0'; wait for c_clk_125_per/2; clk_125 <= '1'; wait for c_clk_125_per/2; end process; clk_125_p <= clk_125; clk_125_n <= not clk_125; --============================================================================ -- Instantiate the DUT --============================================================================ cmp_dut : conv_ttl_blo port map ( -- Clocks -- 20 MHz from VCXO clk_20_i => clk_20, -- 125 MHz from clock generator clk_125_p_i => clk_125_p, clk_125_n_i => clk_125_n, -- Blocking power supply reset line mr_n_o => rst_n, -- Lines for the i2c_slave scl_i => scl, scl_o => scl_fr_slv, scl_en_o => scl_en_slv, sda_i => sda, sda_o => sda_fr_slv, sda_en_o => sda_en_slv, -- VME interface vme_sysreset_n_i => '1', vme_ga_i => "11110", vme_gap_i => '0', pcbrev_i => pcbversn, -- Output enable lines global_oen_o => oe, ttl_oen_o => ttl_oe, inv_oen_o => inv_oe, blo_oen_o => blo_oe, -- I/Os for pulses ttl_n_i => ttl_inp_n, ttl_o => ttl_outp, inv_n_i => inv_inp_n, inv_o => inv_outp, blo_i => blo_inp, blo_o => blo_outp, led_front_n_o => pulse_led_front_n, led_front_inv_n_o => pulse_led_inv_n, led_rear_n_o => pulse_led_rear_n, -- Flash memory lines flash_sclk_o => open, flash_cs_n_o => open, flash_mosi_o => open, flash_miso_i => 'Z', -- PLL DACs -- DAC1: 20 MHz VCXO control dac20_din_o => open, dac20_sclk_o => open, dac20_sync_n_o => open, -- DAC2: 125 MHz clock generator control dac125_din_o => open, dac125_sclk_o => open, dac125_sync_n_o => open, -- SFP lines sfp_los_i => '1', sfp_mod_def0_i => '1', sfp_rate_select_o => open, sfp_mod_def1_b => open, sfp_mod_def2_b => open, sfp_tx_disable_o => open, sfp_tx_fault_i => '1', -- Thermometer line thermometer_b => open, --TTL/INV_TTL_N --ttl_switch_n_i => ttl_switch_n, sw_gp_n_i => switches_n,-- & ttl_switch_n, -- RTM identifiers, should match with the expected values rtmm_i => (others => '0'), rtmp_i => (others => '0'), -- LEDs led_ctrl0_o => open, led_ctrl0_oen_o => open, led_ctrl1_o => open, led_ctrl1_oen_o => open, led_multicast_2_0_o => open, led_multicast_3_1_o => open, led_wr_gmt_ttl_ttln_o => open, led_wr_link_syserror_o => open, led_wr_ok_syspw_o => open, led_wr_ownaddr_i2c_o => open ); -- Tri-state buffers on the I2C lines sscl(0) <= scl_fr_slv when (scl_en_slv = '1') else '1'; ssda(0) <= sda_fr_slv when (sda_en_slv = '1') else '1'; -- Active-high reset rst <= not rst_n; --============================================================================ -- Pulse outputs assignment based on OE signals --============================================================================ ttl_pulse <= ttl_outp when (oe = '1') and (ttl_oe = '1') else (others => '0'); blo_pulse <= blo_outp when (oe = '1') and (blo_oe = '1') else (others => '0'); inv_pulse <= inv_outp when (oe = '1') and (inv_oe = '1') else (others => '0'); --============================================================================ --PCB version --============================================================================ pcbversn (5 downto 0) <= "010000"; --For version 4 --pcbversn (5 downto 0) <= "001100"; --For version 3 --============================================================================ -- Switches --============================================================================ -- TTL --ttl_switch_n <= '0'; switches_n(7) <= '0'; -- GF switches_n(0) <= '1'; --1 is off 0 is on --burst mode is 0 for short pulses and 1 for long pulses switches_n(1) <= '0'; -- other switches_n(6 downto 2) <= (others => '0');--set switched to all 1s for v3 testing -- end process p_set_sw; --============================================================================ -- Pulse LEDs --============================================================================ pulse_led_front <= not pulse_led_front_n; pulse_led_inv <= not pulse_led_inv_n; pulse_led_rear <= not pulse_led_rear_n; --============================================================================ -- Random number generator --============================================================================ p_ran_gen : process variable seed1, seed2: positive := 1; -- seed values for random generator variable rand: real; -- random real-number value in range 0 to 1.0 variable range_of_rand : real := 10000.0; -- the range of random values created will be 0 to +1000. begin uniform(seed1, seed2, rand); -- generate random number rand_num <= integer(rand*range_of_rand); -- rescale to 0..1000, convert integer part wait for 1000 ns; end process p_ran_gen; --============================================================================ -- Pulse stimuli --============================================================================ --blo_inp(6) <= '0'; -- gen_pulse_chain : for i in 6 downto 2 generate -- blo_inp(i) <= blo_outp(i); -- end generate gen_pulse_chain; inv_inp_n <= not inv_inp; --This line is to recover from the inverting buffer which exists on the board blo_inp(1) <= blo_outp(2); ttl_inp_n(1) <= '1'; p_stim_pulse : process variable interval : time;-- := 1000 ns; variable period : time := 450 ns;--changes pulse frequency --variable period2 : time := 20000 ns;--changes pulse frequency variable pwidth : time := 250 ns; begin ttl_inp_n(6 downto 2) <= (others => '1'); inv_inp (4 downto 1) <= (others => '0'); blo_inp(6 downto 2) <= (others => '0'); --wait until inv_flag_n = true; while true loop --while (inv_flag_n = true) loop if random_intervals then interval := rand_num * 1 ns; if interval < 250 ns then interval := 250 ns; end if; else interval := period - pwidth;--changes pulse frequency end if; --Activate for loop if all channels should be testfed j<=0; while j <99 loop --change loop counter range to change number of channels to be tested ttl_inp_n(2) <= '1'; --testing only channel 1 wait for interval; ttl_inp_n(2) <= '0'; wait for pwidth; ttl_inp_n(2) <= '1'; if ttl_outp(2) /= '1' then assert false report "ttl_outp not '1'" severity warning; end if; if blo_outp(2) /= '1' then assert false report "blo_outp not '1'" severity warning; end if; --blo_inp(j) <= '0'; --wait for 10 us; --blo_inp(j) <= '1'; --wait for 1 us; --blo_inp(j) <= '0'; if ttl_outp(2) /= '1' then assert false report "ttl_outp not '1'" severity warning; end if; --if blo_outp(j) /= '1' then -- assert false report "blo_outp not '1'" severity warning; --end if; j<=j+1; end loop; wait for 1 us; -- while (inv_flag_n = false) loop -- for j in 4 downto 1 loop -- inv_inp(j) <= '0'; -- wait for 240 us; -- inv_inp(j) <= '1'; -- wait for 450 ns; -- if inv_outp(j) /= '1' then -- assert false report "inv_ttl_outp not '1'" severity warning; -- end if; -- wait for 50 ns; -- inv_inp(j) <= '0'; -- if blo_outp(6) /= '1' then -- assert false report "blo_outp not '1'" severity warning; -- end if; -- end loop; -- end loop; end loop; end process p_stim_pulse; -- process -- begin -- inv_flag_n <= true; -- wait for 50 ms; -- inv_flag_n <= false; -- wait for 50 ms; -- inv_flag_n <= true; -- wait for 10 ms; -- inv_flag_n <= false; -- wait; -- end process; -- ============================================================================ -- I2C master -- ============================================================================ -------------------------------------------------------------------------- -- First, the component instantiation -------------------------------------------------------------------------- -- cmp_master : i2c_master_byte_ctrl -- port map -- ( -- clk => clk_20, -- rst => rst, -- nReset => rst_n, -- ena => '1', -- clk_cnt => x"0027", -- -- input signals -- start => mst_sta, -- stop => mst_sto, -- read => mst_rd, -- write => mst_wr, -- ack_in => mst_ack, -- din => mst_dat_in, -- -- output signals -- cmd_ack => mst_cmd_ack, -- ack_out => ack_fr_slv, -- i2c_busy => open, -- i2c_al => open, -- dout => mst_dat_out, -- -- i2c lines -- scl_i => scl, -- scl_o => scl_fr_mst, -- scl_oen => scl_en_mst, -- sda_i => sda, -- sda_o => sda_fr_mst, -- sda_oen => sda_en_mst -- ); -- -- Then, the tri-state_i2c_mst buffers on the line -- mscl(0) <= scl_fr_mst when (scl_en_mst = '0') else -- '1'; -- msda(0) <= sda_fr_mst when (sda_en_mst = '0') else -- '1'; -- -------------------------------------------------------------------------- -- -- Bus model instantiation and connection to master and slaves -- -------------------------------------------------------------------------- -- cmp_i2c_bus : i2c_bus_model -- generic map -- ( -- g_nr_masters => c_nr_masters, -- g_nr_slaves => c_nr_slaves -- ) -- port map -- ( -- mscl_i => mscl, -- msda_i => msda, -- sscl_i => sscl, -- ssda_i => ssda, -- scl_o => scl, -- sda_o => sda -- ); -- -------------------------------------------------------------------------- -- -- This FSM controls the signals to the master component to implement the I2C -- -- protocol defined together with ELMA. The FSM is controlled by the -- -- stimuli process below -- -------------------------------------------------------------------------- -- p_mst_fsm : process (clk_20) is -- begin -- if rising_edge(clk_20) then -- if (rst_n = '0') then -- state_i2c_mst <= IDLE; -- mst_sta <= '0'; -- mst_wr <= '0'; -- mst_sto <= '0'; -- mst_rd <= '0'; -- mst_dat_in <= (others => '0'); -- mst_ack <= '0'; -- cnt <= (others => '0'); -- once <= true; -- byte_cnt <= (others => '0'); -- rcvd <= (others => '0'); -- send <= (others => '0'); -- else -- case state_i2c_mst is -- when IDLE => -- if (mst_fsm_start = '1') then -- state_i2c_mst <= I2C_ADDR; -- send <= std_logic_vector(send_val); -- end if; -- when I2C_ADDR => -- mst_sta <= '1'; -- mst_wr <= '1'; -- mst_dat_in <= slv_addr & '0'; -- if (mst_cmd_ack = '1') then -- mst_sta <= '0'; -- mst_wr <= '0'; -- state_i2c_mst <= I2C_ADDR_ACK; -- end if; -- when I2C_ADDR_ACK => -- cnt <= cnt + 1; -- if (cnt = 7) then -- if (ack_fr_slv = '0') then -- state_i2c_mst <= WB_ADDR_B0; -- else -- state_i2c_mst <= ERR; -- end if; -- end if; -- when WB_ADDR_B0 => -- mst_wr <= '1'; -- mst_dat_in <= adr(15 downto 8); -- if (mst_cmd_ack = '1') then -- mst_wr <= '0'; -- state_i2c_mst <= WB_ADDR_B0_ACK; -- end if; -- when WB_ADDR_B0_ACK => -- cnt <= cnt + 1; -- if (cnt = 7) then -- if (ack_fr_slv = '0') then -- state_i2c_mst <= WB_ADDR_B1; -- else -- state_i2c_mst <= ERR; -- end if; -- end if; -- when WB_ADDR_B1 => -- mst_wr <= '1'; -- mst_dat_in <= adr(7 downto 0); -- if (mst_cmd_ack = '1') then -- mst_wr <= '0'; -- state_i2c_mst <= WB_ADDR_B1_ACK; -- end if; -- when WB_ADDR_B1_ACK => -- cnt <= cnt + 1; -- if (cnt = 7) then -- if (ack_fr_slv = '0') then -- state_i2c_mst <= ST_OP; -- else -- state_i2c_mst <= ERR; -- end if; -- end if; -- when ST_OP => -- if (mst_fsm_op = '1') then -- state_i2c_mst <= RD_RESTART; -- else -- state_i2c_mst <= WR; -- end if; -- when RD_RESTART => -- mst_wr <= '1'; -- mst_dat_in <= slv_addr & '1'; -- mst_sta <= '1'; -- if (mst_cmd_ack = '1') then -- mst_sta <= '0'; -- mst_wr <= '0'; -- state_i2c_mst <= RD_RESTART_ACK; -- end if; -- when RD_RESTART_ACK => -- cnt <= cnt + 1; -- if (cnt = 7) then -- if (ack_fr_slv = '0') then -- state_i2c_mst <= RD; -- else -- state_i2c_mst <= ERR; -- end if; -- end if; -- when RD => -- mst_rd <= '1'; -- mst_ack <= '0'; -- if (byte_cnt = 3) then -- mst_ack <= '1'; -- end if; -- if (mst_cmd_ack = '1') then -- mst_rd <= '0'; -- byte_cnt <= byte_cnt + 1; -- rcvd <= mst_dat_out & rcvd(31 downto 8); -- mst_ack <= '0'; -- state_i2c_mst <= RD; -- if (byte_cnt = 3) then -- state_i2c_mst <= STO; -- end if; -- end if; -- when RD_ACK => -- cnt <= cnt + 1; -- if (cnt = 7) then -- byte_cnt <= byte_cnt + 1; -- rcvd <= mst_dat_out & rcvd(31 downto 8); -- mst_ack <= '0'; -- state_i2c_mst <= RD; -- if (byte_cnt = 3) then -- state_i2c_mst <= STO; -- end if; -- end if; -- when WR => -- mst_wr <= '1'; -- mst_dat_in <= send(7 downto 0); -- if (mst_cmd_ack = '1') then -- mst_wr <= '0'; -- state_i2c_mst <= WR_ACK; -- end if; -- when WR_ACK => -- cnt <= cnt + 1; -- if (cnt = 7) then -- if (ack_fr_slv = '0') then -- byte_cnt <= byte_cnt + 1; -- send <= x"00" & send(31 downto 8); -- state_i2c_mst <= WR; -- if (byte_cnt = 3) then -- state_i2c_mst <= STO; -- end if; -- else -- state_i2c_mst <= ERR; -- end if; -- end if; -- when STO => -- mst_sto <= '1'; -- if (mst_cmd_ack = '1') then -- mst_sto <= '0'; -- state_i2c_mst <= IDLE; -- end if; -- when ERR => -- if (once) then -- report("Error!"); -- once <= false; -- end if; -- when others => -- state_i2c_mst <= ERR; -- end case; -- end if; -- end if; -- end process p_mst_fsm; -- -------------------------------------------------------------------------- -- -- Process to "stimulate" the master FSM above -- -------------------------------------------------------------------------- -- p_stim_mst_fsm : process (rst_n, inv_flag_n, state_i2c_mst) -- begin -- if (rst_n = '0') then -- mst_fsm_start <= '0'; -- mst_fsm_op <= '0'; -- slv_addr <= "1011110"; -- adr <= (others => '0'); -- buf_byte_cnt <= 0; -- elsif (not inv_flag_n) and (state_i2c_mst = IDLE) then -- mst_fsm_start <= '1'; -- mst_fsm_op <= '1'; -- buf_byte_cnt <= buf_byte_cnt + 1; -- case buf_byte_cnt is -- when 0 => -- adr(11 downto 0) <= x"030"; -- when 1 => -- adr(11 downto 0) <= x"034"; -- when 2 => -- adr(11 downto 0) <= x"038"; -- when 3 => -- adr(11 downto 0) <= x"02c"; -- buf_byte_cnt <= 0; -- when others => -- buf_byte_cnt <= 0; -- end case; -- else -- mst_fsm_start <= '0'; -- end if; -- end process p_stim_mst_fsm; end architecture behav; --============================================================================== -- architecture end --==============================================================================