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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
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Missed pulses in long term tests
#16
· opened
Oct 10, 2013
by
Theodor-Adrian Stana
bug
CLOSED
1
updated
Feb 12, 2019
Make ip_cores submodule to project
#15
· opened
Oct 31, 2013
by
Theodor-Adrian Stana
bug
CLOSED
1
updated
Feb 12, 2019
[gw-v2.0] Timetag logic -- change FIFO memory for ring buffer
#14
· opened
Mar 28, 2014
by
Theodor-Adrian Stana
feature
CLOSED
1
updated
Feb 12, 2019
[gw-v2.0] Adjust max. pulse duty cycle
#13
· opened
Mar 28, 2014
by
Theodor-Adrian Stana
feature
CLOSED
6
updated
Feb 12, 2019
[gw-v2.0] Integrate the max. pulse duty cycle over time
#12
· opened
Mar 28, 2014
by
Theodor-Adrian Stana
feature
CLOSED
7
updated
Feb 12, 2019
[gw-v2.0] Implement simple error handler
#11
· opened
Mar 28, 2014
by
Theodor-Adrian Stana
feature
CLOSED
1
updated
Feb 12, 2019
Add PMISSE bit for each channel in SR
#10
· opened
May 07, 2014
by
Theodor-Adrian Stana
feature
CLOSED
1
updated
Feb 12, 2019
Power supply current limitation
#9
· opened
May 15, 2014
by
Theodor-Adrian Stana
feature
CLOSED
4
updated
Feb 12, 2019
Latest timestamps per channel in dedicated registers
#8
· opened
Jun 05, 2014
by
Theodor-Adrian Stana
feature
CLOSED
1
updated
Feb 12, 2019
[gw-v2.2] Connect VME_SYSRESET_N signal
#7
· opened
Aug 14, 2014
by
Theodor-Adrian Stana
feature
CLOSED
1
updated
Feb 12, 2019
Implement separate pulse counters for TTL and BLO inputs
#6
· opened
Apr 26, 2016
by
Erik van der Bij
feature
CLOSED
2
updated
Feb 12, 2019
Add support for INV TTL LEDs
#5
· opened
Jul 22, 2016
by
Denia Bouhired-Ferrag
feature
CLOSED
3
updated
Feb 12, 2019
Pulse_err output incorrect for GF OFF setup
#4
· opened
Oct 12, 2016
by
Denia Bouhired-Ferrag
bug
CLOSED
1
updated
Feb 12, 2019
Add support for HW version recognition
#3
· opened
Jan 18, 2017
by
Denia Bouhired-Ferrag
feature
CLOSED
5
updated
Feb 12, 2019
1-wire temperature register not available in register
#2
· opened
Jan 25, 2017
by
Denia Bouhired-Ferrag
feature
CLOSED
1
updated
Feb 12, 2019
