1. 12 Apr, 2017 1 commit
  2. 08 Mar, 2017 2 commits
  3. 07 Mar, 2017 1 commit
  4. 03 Mar, 2017 2 commits
  5. 13 Feb, 2017 1 commit
  6. 07 Feb, 2017 1 commit
  7. 01 Feb, 2017 1 commit
  8. 25 Jan, 2017 2 commits
  9. 24 Jan, 2017 2 commits
  10. 16 Dec, 2016 2 commits
  11. 13 Dec, 2016 1 commit
  12. 10 Nov, 2016 1 commit
  13. 06 Sep, 2016 2 commits
  14. 23 Jan, 2015 1 commit
  15. 26 Sep, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Fixed inhibit first pulse and added FRONTFS and FRONTINVFS bits in LSR · 1b4de266
      Theodor-Adrian Stana authored
      The issue with the first pulse inhibit mechanism was (again) that it needs
      to be disabled one clock cycle after the TTL-BAR no signal detect block is disabled,
      otherwise the no signal detect block has no effect on the conv-common-gw block, due
      to sub-modules still being in a reset state.
      A one-clock-cycle delayed version of inhibit_first_pulse is now used to enable passing
      the pulse signals to the conv-common-gw block.
      In addition to this modification, the FRONTFS and FRONTINVFS bits were added
      to the LSR inside conv-common-gw. The necessary additions were made here to
      account for the changes in the conv-common-gw interface.
  16. 25 Sep, 2014 1 commit
  17. 22 Aug, 2014 2 commits
  18. 21 Aug, 2014 3 commits
  19. 15 Apr, 2014 1 commit
  20. 08 Apr, 2014 1 commit
  21. 07 Apr, 2014 2 commits
  22. 28 Mar, 2014 1 commit
  23. 26 Mar, 2014 1 commit
  24. 25 Mar, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Work on release v2.1 · 0dd7106c
      Theodor-Adrian Stana authored
      - substitute FIFO for ring buffer
      - change pulse repetition duty cycle to 1/500
      - renamed some files to make "generic" naming
      - release: add I2C simulation capabilities
      - conv_pulse_gen: change testbench.vhd for simulating 1/500 duty cycle
      - update project file with new files
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
  25. 06 Mar, 2014 2 commits
  26. 19 Feb, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Pre-version 2.0 commit · 64f1a255
      Theodor-Adrian Stana authored
      - added pulse time tagging core (pulse_timetag.vhd)
      - added FIFO via the conv_regs.wb file
      - to make the FIFO read work properly, I needed to change the
      wb_i2c_bridge component (general-cores submodule)
      - updated top-level to connect the FIFO to conv_regs component
      - moved the pulse generator glitch filter to outside the pulse
      - changed the conv_pulse_gen block to be able to properly reject
      pulses up to only 1/5 duty cycle, not more (I realized by simulation
      that when the glitch filter was enabled, it needed one extra cycle,
      thus the duty cycle of the pulse was not 1/5, but 1/5 + one clock cycle)
      - updated synthesis files for the Release project to add the new files,
      and the regtest and pulsetest due to the I2C bridge changes
      Simulation files:
      - conv_pulse_gen: changes for the aforementioned change test
      - added pulse_timetag sim files
      - added release top-level simulation, which at the moment does
      not contain a lot of stuff (only pulse rep test), but can be used as a
      starter to verify the design works appropriately
      - updated memory map with cute wbgen-ized memory map
      - added time-tagging core information
      - updated the Getting Around the Code section
      - added and updated figures
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
  27. 05 Feb, 2014 1 commit
  28. 03 Feb, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      hdl: Fixed a problem with the pulse counters · 5dcc4b58
      Theodor-Adrian Stana authored
      When the TTL selection switch is set for TTL-BAR signals, the pulse counters
      were starting from the value 1. This was because the input channel is
      first sent through a synchronizer FF chain, which was reset by the
      same reset signal as the rest of the logic.
      Due to the reset pulse inside the logic and the fact that when the TTL switch
      is set to TTL-BAR, a non-existing signal represents a high level, this
      high level was detected (due to the sync FF chain) only after the reset pulse.
      This resulted in a rising edge on the trigger signal, which resulted in the
      pulse counters incrementing to '1' on every reset.
      This problem has been solved by not resetting the sync FF chain.
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
  29. 30 Jan, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      hdl: Made manual pulse trigger work properly · c74ddcd8
      Theodor-Adrian Stana authored
      Prior to this commit, manual pulse triggering did not work when the glitch
      filter was enabled. Now, this was fixed by extending the trigger pulse the
      conv_man_trig module generates. This accounts for the situation where the
      pulse generator has the glitch filter enabled.
      I also fixed a bug in conv_pulse_gen; this fix was commited two commits ago.
      The bug consisted of the gf_off part of the pulse generator triggering even
      when the glitch filter was enabled. This resulted in a continuous high pulse
      generated on the output when the glitch filter was switched from on to off.
      Granted, such a situation should not occur in operation, since a board needs
      to be removed from the crate in order to flip a switch. Nonetheless, it was a
      but, so I've fixed it by making sure the gf_off part of the design only triggers
      when the glitch filter is disabled:
      if (en_i = '1') and (gf_en_n_i = '1') then
        pulse_gf_off <= '1';
      end if;
      A warning will be placed in the docs for release versions 1.0 and 0.0 (golden).
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>