Signed-off-by: Theodor Stana <t.stana@cern.ch>

hdl:
- substitute FIFO for ring buffer
- change pulse repetition duty cycle to 1/500
- renamed some files to make "generic" naming

sim:
- release: add I2C simulation capabilities
- conv_pulse_gen: change testbench.vhd for simulating 1/500 duty cycle

syn:
- update project file with new files
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Apart from the .do files which were updated after simulation, the main
change is the addition within the main testbench file of a daisy-chain
loop on the channel and a couple of assert statements to see if any
pulses are missed.
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Changes:

HDL:

- added pulse time tagging core (pulse_timetag.vhd)
- added FIFO via the conv_regs.wb file
- to make the FIFO read work properly, I needed to change the
wb_i2c_bridge component (general-cores submodule)
- updated top-level to connect the FIFO to conv_regs component
- moved the pulse generator glitch filter to outside the pulse
generator
- changed the conv_pulse_gen block to be able to properly reject
pulses up to only 1/5 duty cycle, not more (I realized by simulation
that when the glitch filter was enabled, it needed one extra cycle,
thus the duty cycle of the pulse was not 1/5, but 1/5 + one clock cycle)
- updated synthesis files for the Release project to add the new files,
and the regtest and pulsetest due to the I2C bridge changes

Simulation files:
- conv_pulse_gen: changes for the aforementioned change test
- added pulse_timetag sim files
- added release top-level simulation, which at the moment does
not contain a lot of stuff (only pulse rep test), but can be used as a
starter to verify the design works appropriately

Doc:
- updated memory map with cute wbgen-ized memory map
- added time-tagging core information
- updated the Getting Around the Code section
- added and updated figures
Signed-off-by: Theodor Stana <t.stana@cern.ch>