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  5. 20 Feb, 2017 1 commit
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  11. 30 Sep, 2014 1 commit
  12. 29 Sep, 2014 2 commits
  13. 26 Sep, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Updated hdl guide · a91367c3
      Theodor-Adrian Stana authored
      The following sections were updated:
      - 3.1 TTL input logic -- added reflection of no signal detect state in LSR
      - 3.2 First pulse inhibit -- added delay before enabling the line to conv-common-gw
      - 3.3 Line input logic -- added reflection of no signal detect state in LSR
      - 3.4 Switches -- made figure more compact
      a91367c3
  14. 25 Sep, 2014 3 commits
  15. 02 May, 2014 1 commit
  16. 25 Apr, 2014 1 commit
  17. 08 Apr, 2014 1 commit
  18. 07 Apr, 2014 1 commit
  19. 26 Mar, 2014 1 commit
  20. 06 Mar, 2014 1 commit
  21. 19 Feb, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Pre-version 2.0 commit · 64f1a255
      Theodor-Adrian Stana authored
      Changes:
      
      HDL:
      
      - added pulse time tagging core (pulse_timetag.vhd)
      - added FIFO via the conv_regs.wb file
      - to make the FIFO read work properly, I needed to change the
      wb_i2c_bridge component (general-cores submodule)
      - updated top-level to connect the FIFO to conv_regs component
      - moved the pulse generator glitch filter to outside the pulse
      generator
      - changed the conv_pulse_gen block to be able to properly reject
      pulses up to only 1/5 duty cycle, not more (I realized by simulation
      that when the glitch filter was enabled, it needed one extra cycle,
      thus the duty cycle of the pulse was not 1/5, but 1/5 + one clock cycle)
      - updated synthesis files for the Release project to add the new files,
      and the regtest and pulsetest due to the I2C bridge changes
      
      Simulation files:
      - conv_pulse_gen: changes for the aforementioned change test
      - added pulse_timetag sim files
      - added release top-level simulation, which at the moment does
      not contain a lot of stuff (only pulse rep test), but can be used as a
      starter to verify the design works appropriately
      
      Doc:
      - updated memory map with cute wbgen-ized memory map
      - added time-tagging core information
      - updated the Getting Around the Code section
      - added and updated figures
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
      64f1a255