The following sections were updated:
- 3.1 TTL input logic -- added reflection of no signal detect state in LSR
- 3.2 First pulse inhibit -- added delay before enabling the line to conv-common-gw
- 3.3 Line input logic -- added reflection of no signal detect state in LSR
- 3.4 Switches -- made figure more compact

Also updated ISE project file to test that nothing went wrong when these
modules were deleted.

The issue with the first pulse inhibit mechanism was (again) that it needs
to be disabled one clock cycle after the TTL-BAR no signal detect block is disabled,
otherwise the no signal detect block has no effect on the conv-common-gw block, due
to sub-modules still being in a reset state.

A one-clock-cycle delayed version of inhibit_first_pulse is now used to enable passing
the pulse signals to the conv-common-gw block.

In addition to this modification, the FRONTFS and FRONTINVFS bits were added
to the LSR inside conv-common-gw. The necessary additions were made here to
account for the changes in the conv-common-gw interface.

Also prepared the ISE project file for v3.0 release

This is done by lighting the LED red when the upper four bits of the gateeware
version are "0000".

This means we're close to g/w v2.3 (only lacking the documentation)

general-cores is a submodule of conv-common-gw, and it is from there that all
general-cores modules used on top-level are imported

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

gencores-suproj: fix bug in wb_i2c_slave
ctblo_pulse_gen.vhd: add pulse_err_o to signal when a pulse is rejected
conv_regs.vhd: add PMISSE and I2C_ERR bits
top-level: implement PMISSE and I2C_ERR bits and change error LED logic
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

hdl:
- substitute FIFO for ring buffer
- change pulse repetition duty cycle to 1/500
- renamed some files to make "generic" naming

sim:
- release: add I2C simulation capabilities
- conv_pulse_gen: change testbench.vhd for simulating 1/500 duty cycle

syn:
- update project file with new files
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Apart from the .do files which were updated after simulation, the main
change is the addition within the main testbench file of a daisy-chain
loop on the channel and a couple of assert statements to see if any
pulses are missed.
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Changes:

HDL:

- added pulse time tagging core (pulse_timetag.vhd)
- added FIFO via the conv_regs.wb file
- to make the FIFO read work properly, I needed to change the
wb_i2c_bridge component (general-cores submodule)
- updated top-level to connect the FIFO to conv_regs component
- moved the pulse generator glitch filter to outside the pulse
generator
- changed the conv_pulse_gen block to be able to properly reject
pulses up to only 1/5 duty cycle, not more (I realized by simulation
that when the glitch filter was enabled, it needed one extra cycle,
thus the duty cycle of the pulse was not 1/5, but 1/5 + one clock cycle)
- updated synthesis files for the Release project to add the new files,
and the regtest and pulsetest due to the I2C bridge changes

Simulation files:
- conv_pulse_gen: changes for the aforementioned change test
- added pulse_timetag sim files
- added release top-level simulation, which at the moment does
not contain a lot of stuff (only pulse rep test), but can be used as a
starter to verify the design works appropriately

Doc:
- updated memory map with cute wbgen-ized memory map
- added time-tagging core information
- updated the Getting Around the Code section
- added and updated figures
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Also updated hdlguide to reflect this
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

When the TTL selection switch is set for TTL-BAR signals, the pulse counters
were starting from the value 1. This was because the input channel is
first sent through a synchronizer FF chain, which was reset by the
same reset signal as the rest of the logic.

Due to the reset pulse inside the logic and the fact that when the TTL switch
is set to TTL-BAR, a non-existing signal represents a high level, this
high level was detected (due to the sync FF chain) only after the reset pulse.
This resulted in a rising edge on the trigger signal, which resulted in the
pulse counters incrementing to '1' on every reset.

This problem has been solved by not resetting the sync FF chain.
Signed-off-by: Theodor Stana <t.stana@cern.ch>