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  17. 26 Sep, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Fixed inhibit first pulse and added FRONTFS and FRONTINVFS bits in LSR · 1b4de266
      Theodor-Adrian Stana authored
      The issue with the first pulse inhibit mechanism was (again) that it needs
      to be disabled one clock cycle after the TTL-BAR no signal detect block is disabled,
      otherwise the no signal detect block has no effect on the conv-common-gw block, due
      to sub-modules still being in a reset state.
      
      A one-clock-cycle delayed version of inhibit_first_pulse is now used to enable passing
      the pulse signals to the conv-common-gw block.
      
      In addition to this modification, the FRONTFS and FRONTINVFS bits were added
      to the LSR inside conv-common-gw. The necessary additions were made here to
      account for the changes in the conv-common-gw interface.
      1b4de266
  18. 25 Sep, 2014 1 commit
  19. 28 Aug, 2014 1 commit
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  26. 19 Feb, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Pre-version 2.0 commit · 64f1a255
      Theodor-Adrian Stana authored
      Changes:
      
      HDL:
      
      - added pulse time tagging core (pulse_timetag.vhd)
      - added FIFO via the conv_regs.wb file
      - to make the FIFO read work properly, I needed to change the
      wb_i2c_bridge component (general-cores submodule)
      - updated top-level to connect the FIFO to conv_regs component
      - moved the pulse generator glitch filter to outside the pulse
      generator
      - changed the conv_pulse_gen block to be able to properly reject
      pulses up to only 1/5 duty cycle, not more (I realized by simulation
      that when the glitch filter was enabled, it needed one extra cycle,
      thus the duty cycle of the pulse was not 1/5, but 1/5 + one clock cycle)
      - updated synthesis files for the Release project to add the new files,
      and the regtest and pulsetest due to the I2C bridge changes
      
      Simulation files:
      - conv_pulse_gen: changes for the aforementioned change test
      - added pulse_timetag sim files
      - added release top-level simulation, which at the moment does
      not contain a lot of stuff (only pulse rep test), but can be used as a
      starter to verify the design works appropriately
      
      Doc:
      - updated memory map with cute wbgen-ized memory map
      - added time-tagging core information
      - updated the Getting Around the Code section
      - added and updated figures
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
      64f1a255
  27. 27 Jan, 2014 1 commit
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  32. 18 Nov, 2013 1 commit