- 10 Mar, 2017 5 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 08 Mar, 2017 4 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Renamed some of conv-common-gw ports to avoid references to signal types (ttl or blo) are yet to be changed. this is not a priority for release 4 of the gateware.
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Doc: Updated hdl guide with additional note on inverter channel output LEDs. fixed a typo on conv-regs.
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- 07 Mar, 2017 2 commits
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Denia Bouhired-Ferrag authored
Small modification in p_inhibit_first_pulse process, now checks that all lines are low before end of 100us first pulse inhibit period.
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Denia Bouhired-Ferrag authored
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- 03 Mar, 2017 2 commits
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Denia Bouhired-Ferrag authored
UCF file adds some attributes to the input channel i/o to bypass the fact it is not a clock despite being used as a clock in the flancter
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Denia Bouhired-Ferrag authored
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- 28 Feb, 2017 1 commit
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Denia Bouhired-Ferrag authored
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- 17 Feb, 2017 1 commit
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Denia Bouhired-Ferrag authored
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- 13 Feb, 2017 3 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 07 Feb, 2017 1 commit
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Denia Bouhired-Ferrag authored
UCF file includes two extra pins for additional 2 bits identifying the pcb execution number. This is in addition to the 4 bits for the version number
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- 01 Feb, 2017 1 commit
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Denia Bouhired-Ferrag authored
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- 27 Jan, 2017 1 commit
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Grzegorz Daniluk authored
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- 26 Jan, 2017 7 commits
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Denia Bouhired-Ferrag authored
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 25 Jan, 2017 3 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Previous commit contained serious error, as accidentally modified blo-input nets. It is corrected now + right nets assigned for PCB versioning
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- 24 Jan, 2017 4 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Testbench for burst mode testing updated. The overall gateware testbench also updated to show burst mode operation for short pulses
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- 16 Jan, 2017 1 commit
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Denia Bouhired-Ferrag authored
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- 13 Jan, 2017 1 commit
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Denia Bouhired-Ferrag authored
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- 21 Dec, 2016 1 commit
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Denia Bouhired-Ferrag authored
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- 20 Dec, 2016 2 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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