Doc: Updated hdl guide with additional note on inverter channel output LEDs. fixed a typo on conv-regs.

Small modification in p_inhibit_first_pulse process, now checks that all lines are low before end of 100us first pulse inhibit period.

UCF file adds some attributes to the input channel i/o to bypass the fact it is not a clock despite being used as a clock in the flancter

UCF file includes two extra pins for additional 2 bits identifying the pcb execution number. This is in addition to the 4 bits for the version number

Previous commit contained serious error, as accidentally modified blo-input nets. It is corrected now + right nets assigned for PCB versioning

Testbench for burst mode testing updated. The overall gateware testbench also updated to show burst mode operation for short pulses

Added tcl script used in release 3 of the gateware. Should work for future releases, but care must be taken to modify the file list

Adds updated project with settings from tcl scrip also added. Top module modified to have correct LED output