The following sections were updated:
- 3.1 TTL input logic -- added reflection of no signal detect state in LSR
- 3.2 First pulse inhibit -- added delay before enabling the line to conv-common-gw
- 3.3 Line input logic -- added reflection of no signal detect state in LSR
- 3.4 Switches -- made figure more compact

Also updated ISE project file to test that nothing went wrong when these
modules were deleted.

The issue with the first pulse inhibit mechanism was (again) that it needs
to be disabled one clock cycle after the TTL-BAR no signal detect block is disabled,
otherwise the no signal detect block has no effect on the conv-common-gw block, due
to sub-modules still being in a reset state.

A one-clock-cycle delayed version of inhibit_first_pulse is now used to enable passing
the pulse signals to the conv-common-gw block.

In addition to this modification, the FRONTFS and FRONTINVFS bits were added
to the LSR inside conv-common-gw. The necessary additions were made here to
account for the changes in the conv-common-gw interface.

Also prepared the ISE project file for v3.0 release

This is done by lighting the LED red when the upper four bits of the gateeware
version are "0000".

This means we're close to g/w v2.3 (only lacking the documentation)

general-cores is a submodule of conv-common-gw, and it is from there that all
general-cores modules used on top-level are imported

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

gencores-suproj: fix bug in wb_i2c_slave
ctblo_pulse_gen.vhd: add pulse_err_o to signal when a pulse is rejected
conv_regs.vhd: add PMISSE and I2C_ERR bits
top-level: implement PMISSE and I2C_ERR bits and change error LED logic
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

hdl:
- substitute FIFO for ring buffer
- change pulse repetition duty cycle to 1/500
- renamed some files to make "generic" naming

sim:
- release: add I2C simulation capabilities
- conv_pulse_gen: change testbench.vhd for simulating 1/500 duty cycle

syn:
- update project file with new files
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>